diff --git a/src/amd/compiler/tests/test_regalloc.cpp b/src/amd/compiler/tests/test_regalloc.cpp
index ef93f991dab..b6f07c06ae4 100644
--- a/src/amd/compiler/tests/test_regalloc.cpp
+++ b/src/amd/compiler/tests/test_regalloc.cpp
@@ -58,3 +58,22 @@ BEGIN_TEST(regalloc.subdword_alloc.reuse_16bit_operands)
       }
    }
 END_TEST
+
+BEGIN_TEST(regalloc.32bit_partial_write)
+   //>> v1: %_:v[0], s2: %_:exec = p_startpgm
+   if (!setup_cs("v1", GFX10))
+      return;
+
+   /* ensure high 16 bits are occupied */
+   //! v2b: %_:v[0][0:16], v2b: %_:v[0][16:32] = p_split_vector %_:v[0]
+   Temp hi = bld.pseudo(aco_opcode::p_split_vector, bld.def(v2b), bld.def(v2b), inputs[0]).def(1).getTemp();
+
+   /* This test checks if this instruction uses SDWA. */
+   //! v2b: %_:v[0][0:16] = v_not_b32 0 dst_preserve
+   Temp lo = bld.vop1(aco_opcode::v_not_b32, bld.def(v2b), Operand(0u));
+
+   //! v1: %_:v[0] = p_create_vector %_:v[0][0:16], %_:v[0][16:32]
+   bld.pseudo(aco_opcode::p_create_vector, bld.def(v1), lo, hi);
+
+   finish_ra_test(ra_test_policy());
+END_TEST