diff --git a/src/amd/common/ac_cmdbuf.c b/src/amd/common/ac_cmdbuf.c
index 633eb7a6bcf..062d0165a25 100644
--- a/src/amd/common/ac_cmdbuf.c
+++ b/src/amd/common/ac_cmdbuf.c
@@ -878,17 +878,37 @@ ac_emit_cp_cond_exec(struct ac_cmdbuf *cs, enum amd_gfx_level gfx_level,
    ac_cmdbuf_end();
 }
 
+void
+ac_emit_cp_write_data_head(struct ac_cmdbuf *cs, uint32_t engine_sel,
+                           uint32_t dst_sel, uint64_t va, uint32_t size,
+                           bool predicate)
+{
+   ac_cmdbuf_begin(cs);
+   ac_cmdbuf_emit(PKT3(PKT3_WRITE_DATA, 2 + size, predicate));
+   ac_cmdbuf_emit(S_370_DST_SEL(dst_sel) |
+                  S_370_WR_CONFIRM(1) |
+                  S_370_ENGINE_SEL(engine_sel));
+   ac_cmdbuf_emit(va);
+   ac_cmdbuf_emit(va >> 32);
+   ac_cmdbuf_end();
+}
+
+void
+ac_emit_cp_write_data(struct ac_cmdbuf *cs, uint32_t engine_sel,
+                      uint32_t dst_sel, uint64_t va, uint32_t size,
+                      const uint32_t *data, bool predicate)
+{
+   ac_emit_cp_write_data_head(cs, engine_sel, dst_sel, va, size, predicate);
+   ac_cmdbuf_begin(cs);
+   ac_cmdbuf_emit_array(data, size);
+   ac_cmdbuf_end();
+}
+
 void
 ac_emit_cp_write_data_imm(struct ac_cmdbuf *cs, unsigned engine_sel,
                           uint64_t va, uint32_t value)
 {
-   ac_cmdbuf_begin(cs);
-   ac_cmdbuf_emit(PKT3(PKT3_WRITE_DATA, 3, 0));
-   ac_cmdbuf_emit(S_370_DST_SEL(V_370_MEM) | S_370_WR_CONFIRM(1) | S_370_ENGINE_SEL(engine_sel));
-   ac_cmdbuf_emit(va);
-   ac_cmdbuf_emit(va >> 32);
-   ac_cmdbuf_emit(value);
-   ac_cmdbuf_end();
+   ac_emit_cp_write_data(cs, engine_sel, V_370_MEM, va, 1, &value, false);
 }
 
 void
diff --git a/src/amd/common/ac_cmdbuf.h b/src/amd/common/ac_cmdbuf.h
index 9b072a9500f..97e68c78e7d 100644
--- a/src/amd/common/ac_cmdbuf.h
+++ b/src/amd/common/ac_cmdbuf.h
@@ -124,6 +124,16 @@ void
 ac_emit_cp_cond_exec(struct ac_cmdbuf *cs, enum amd_gfx_level gfx_level,
                      uint64_t va, uint32_t count);
 
+void
+ac_emit_cp_write_data_head(struct ac_cmdbuf *cs, uint32_t engine_sel,
+                           uint32_t dst_sel, uint64_t va, uint32_t size,
+                           bool predicate);
+
+void
+ac_emit_cp_write_data(struct ac_cmdbuf *cs, uint32_t engine_sel,
+                      uint32_t dst_sel, uint64_t va, uint32_t size,
+                      const uint32_t *data, bool predicate);
+
 void
 ac_emit_cp_write_data_imm(struct ac_cmdbuf *cs, unsigned engine_sel,
                           uint64_t va, uint32_t value);
diff --git a/src/amd/vulkan/meta/radv_meta_buffer.c b/src/amd/vulkan/meta/radv_meta_buffer.c
index 66fd17ab937..6e5ef01625a 100644
--- a/src/amd/vulkan/meta/radv_meta_buffer.c
+++ b/src/amd/vulkan/meta/radv_meta_buffer.c
@@ -414,13 +414,7 @@ radv_update_memory_cp(struct radv_cmd_buffer *cmd_buffer, uint64_t va, const voi
    radv_emit_cache_flush(cmd_buffer);
    radeon_check_space(device->ws, cs->b, words + 4);
 
-   radeon_begin(cs);
-   radeon_emit(PKT3(PKT3_WRITE_DATA, 2 + words, 0));
-   radeon_emit(S_370_DST_SEL(mec ? V_370_MEM : V_370_MEM_GRBM) | S_370_WR_CONFIRM(1) | S_370_ENGINE_SEL(V_370_ME));
-   radeon_emit(va);
-   radeon_emit(va >> 32);
-   radeon_emit_array(data, words);
-   radeon_end();
+   ac_emit_cp_write_data(cs->b, V_370_ME, mec ? V_370_MEM : V_370_MEM_GRBM, va, words, data, false);
 
    if (radv_device_fault_detection_enabled(device))
       radv_cmd_buffer_trace_emit(cmd_buffer);
diff --git a/src/amd/vulkan/radv_cs.h b/src/amd/vulkan/radv_cs.h
index 84e76ffb3f6..f373d164700 100644
--- a/src/amd/vulkan/radv_cs.h
+++ b/src/amd/vulkan/radv_cs.h
@@ -351,12 +351,7 @@ radv_cs_write_data_head(const struct radv_device *device, struct radv_cmd_stream
    const unsigned cdw_end = radeon_check_space(device->ws, cs->b, 4 + count);
 
    if (cs->hw_ip == AMD_IP_COMPUTE || cs->hw_ip == AMD_IP_GFX) {
-      radeon_begin(cs);
-      radeon_emit(PKT3(PKT3_WRITE_DATA, 2 + count, predicating));
-      radeon_emit(S_370_DST_SEL(V_370_MEM) | S_370_WR_CONFIRM(1) | S_370_ENGINE_SEL(engine_sel));
-      radeon_emit(va);
-      radeon_emit(va >> 32);
-      radeon_end();
+      ac_emit_cp_write_data_head(cs->b, engine_sel, V_370_MEM, va, count, predicating);
    } else if (cs->hw_ip == AMD_IP_SDMA) {
       radv_sdma_emit_write_data_head(cs, va, count);
    } else {
diff --git a/src/gallium/drivers/radeonsi/si_cp_dma.c b/src/gallium/drivers/radeonsi/si_cp_dma.c
index c8884597e26..7f71ab0469e 100644
--- a/src/gallium/drivers/radeonsi/si_cp_dma.c
+++ b/src/gallium/drivers/radeonsi/si_cp_dma.c
@@ -355,13 +355,8 @@ void si_cp_write_data(struct si_context *sctx, struct si_resource *buf, unsigned
    radeon_add_to_buffer_list(sctx, cs, buf, RADEON_USAGE_WRITE | RADEON_PRIO_CP_DMA);
    uint64_t va = buf->gpu_address + offset;
 
-   radeon_begin(cs);
-   radeon_emit(PKT3(PKT3_WRITE_DATA, 2 + size / 4, 0));
-   radeon_emit(S_370_DST_SEL(dst_sel) | S_370_WR_CONFIRM(1) | S_370_ENGINE_SEL(engine));
-   radeon_emit(va);
-   radeon_emit(va >> 32);
-   radeon_emit_array((const uint32_t *)data, size / 4);
-   radeon_end();
+   ac_emit_cp_write_data(&cs->current, engine, dst_sel, va, size / 4,
+                         (const uint32_t *)data, false);
 }
 
 void si_cp_copy_data(struct si_context *sctx, struct radeon_cmdbuf *cs, unsigned dst_sel,