diff --git a/src/freedreno/.gitlab-ci/reference/crash.log b/src/freedreno/.gitlab-ci/reference/crash.log
index 9d6d1f22623..2f4eee79837 100644
--- a/src/freedreno/.gitlab-ci/reference/crash.log
+++ b/src/freedreno/.gitlab-ci/reference/crash.log
@@ -5830,7 +5830,7 @@ clusters:
 	00000000	RB_BLIT_CLEAR_COLOR_DW1: 0
 	00000000	RB_BLIT_CLEAR_COLOR_DW2: 0
 	00000000	RB_BLIT_CLEAR_COLOR_DW3: 0
-	000000f2	RB_BLIT_INFO: { GMEM | CLEAR_MASK = 0xf | LAST = 0 | BUFFER_ID = 0 }
+	000000f2	RB_BLIT_INFO: { TYPE = BLIT_EVENT_CLEAR | CLEAR_MASK = 0xf | LAST = 0 | BUFFER_ID = 0 }
 	00000000	RB_DEPTH_FLAG_BUFFER_BASE: 0
 	00000000	RB_DEPTH_FLAG_BUFFER_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 }
 	00000000	RB_MRT_FLAG_BUFFER[0].ADDR: 0
@@ -6007,7 +6007,7 @@ WARNING: 64b discontinuity (no _LO dword for 8910)
 	00000000	RB_BLIT_CLEAR_COLOR_DW1: 0
 	00000000	RB_BLIT_CLEAR_COLOR_DW2: 0
 	00000000	RB_BLIT_CLEAR_COLOR_DW3: 0
-	000000f2	RB_BLIT_INFO: { GMEM | CLEAR_MASK = 0xf | LAST = 0 | BUFFER_ID = 0 }
+	000000f2	RB_BLIT_INFO: { TYPE = BLIT_EVENT_CLEAR | CLEAR_MASK = 0xf | LAST = 0 | BUFFER_ID = 0 }
 	00000000	RB_DEPTH_FLAG_BUFFER_BASE: 0
 	00000000	RB_DEPTH_FLAG_BUFFER_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 }
 	00000000	RB_MRT_FLAG_BUFFER[0].ADDR: 0
diff --git a/src/freedreno/.gitlab-ci/reference/crash_prefetch.log b/src/freedreno/.gitlab-ci/reference/crash_prefetch.log
index 2c671e67832..2ac1be33712 100644
--- a/src/freedreno/.gitlab-ci/reference/crash_prefetch.log
+++ b/src/freedreno/.gitlab-ci/reference/crash_prefetch.log
@@ -2328,7 +2328,7 @@ got cmdszdw=83
 !+	00000004				RB_BLIT_DST_PITCH: 256
 !+	100094000				RB_BLIT_FLAG_DST: 0x100094000
 !+	00004001				RB_BLIT_FLAG_DST_PITCH: { PITCH = 64 | ARRAY_PITCH = 1024 }
-!+	00000003				RB_BLIT_INFO: { UNK0 | GMEM | CLEAR_MASK = 0 | LAST = 0 | BUFFER_ID = 0 }
+!+	00000003				RB_BLIT_INFO: { TYPE = BLIT_EVENT_LOAD | CLEAR_MASK = 0 | LAST = 0 | BUFFER_ID = 0 }
  +	00000000				RB_UNKNOWN_88F0: 0
  +	00000001				RB_UNKNOWN_8E01: 0x1
  +	00100000				RB_DBG_ECO_CNTL: 0x100000
@@ -2380,7 +2380,7 @@ got cmdszdw=83
 !+	00000008				RB_BLIT_DST_PITCH: 512
 !+	10009c000				RB_BLIT_FLAG_DST: 0x10009c000
 !+	00000000				RB_BLIT_FLAG_DST_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 }
- +	00000003				RB_BLIT_INFO: { UNK0 | GMEM | CLEAR_MASK = 0 | LAST = 0 | BUFFER_ID = 0 }
+ +	00000003				RB_BLIT_INFO: { TYPE = BLIT_EVENT_LOAD | CLEAR_MASK = 0 | LAST = 0 | BUFFER_ID = 0 }
 0000000100227098:				0000: 70460001 0000001e
 				opcode: CP_EVENT_WRITE (46) (2 dwords)
 					{ EVENT = BLIT }
@@ -2395,7 +2395,7 @@ got cmdszdw=83
 !+	00000004				RB_BLIT_DST_PITCH: 256
 !+	1000ae000				RB_BLIT_FLAG_DST: 0x1000ae000
 !+	00004001				RB_BLIT_FLAG_DST_PITCH: { PITCH = 64 | ARRAY_PITCH = 1024 }
- +	00000003				RB_BLIT_INFO: { UNK0 | GMEM | CLEAR_MASK = 0 | LAST = 0 | BUFFER_ID = 0 }
+ +	00000003				RB_BLIT_INFO: { TYPE = BLIT_EVENT_LOAD | CLEAR_MASK = 0 | LAST = 0 | BUFFER_ID = 0 }
 00000001002270dc:				0000: 70460001 0000001e
 				opcode: CP_COND_REG_EXEC (47) (3 dwords)
 					{ MODE = RENDER_MODE | GMEM | SYSMEM }
@@ -3034,7 +3034,7 @@ got cmdszdw=83
 !+	00000008				RB_BLIT_DST_PITCH: 512
 !+	100082000				RB_BLIT_FLAG_DST: 0x100082000
 !+	00000000				RB_BLIT_FLAG_DST_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 }
-!+	00000000				RB_BLIT_INFO: { CLEAR_MASK = 0 | LAST = 0 | BUFFER_ID = 0 }
+!+	00000000				RB_BLIT_INFO: { TYPE = BLIT_EVENT_STORE | CLEAR_MASK = 0 | LAST = 0 | BUFFER_ID = 0 }
 0000000100227298:				0000: 70460001 0000001e
 				opcode: CP_COND_REG_EXEC (47) (3 dwords)
 					{ MODE = RENDER_MODE | GMEM }
@@ -3056,7 +3056,7 @@ got cmdszdw=83
  +	00000000				RB_BLIT_CLEAR_COLOR_DW1: 0
  +	00000000				RB_BLIT_CLEAR_COLOR_DW2: 0
  +	00000000				RB_BLIT_CLEAR_COLOR_DW3: 0
-!+	000000f2				RB_BLIT_INFO: { GMEM | CLEAR_MASK = 0xf | LAST = 0 | BUFFER_ID = 0 }
+!+	000000f2				RB_BLIT_INFO: { TYPE = BLIT_EVENT_CLEAR | CLEAR_MASK = 0xf | LAST = 0 | BUFFER_ID = 0 }
 00000001002272f4:				0000: 70460001 0000001e
 				opcode: CP_COND_REG_EXEC (47) (3 dwords)
 					{ MODE = RENDER_MODE | SYSMEM }
@@ -3748,7 +3748,7 @@ got cmdszdw=83
 !+	00000004				RB_BLIT_DST_PITCH: 256
 !+	100094000				RB_BLIT_FLAG_DST: 0x100094000
 !+	00004001				RB_BLIT_FLAG_DST_PITCH: { PITCH = 64 | ARRAY_PITCH = 1024 }
-!+	00000000				RB_BLIT_INFO: { CLEAR_MASK = 0 | LAST = 0 | BUFFER_ID = 0 }
+!+	00000000				RB_BLIT_INFO: { TYPE = BLIT_EVENT_STORE | CLEAR_MASK = 0 | LAST = 0 | BUFFER_ID = 0 }
 000000010022756c:				0000: 70460001 0000001e
 				opcode: CP_COND_REG_EXEC (47) (3 dwords)
 					{ MODE = RENDER_MODE | GMEM }
@@ -3770,7 +3770,7 @@ got cmdszdw=83
  +	00000000				RB_BLIT_CLEAR_COLOR_DW1: 0
  +	00000000				RB_BLIT_CLEAR_COLOR_DW2: 0
  +	00000000				RB_BLIT_CLEAR_COLOR_DW3: 0
-!+	000000f2				RB_BLIT_INFO: { GMEM | CLEAR_MASK = 0xf | LAST = 0 | BUFFER_ID = 0 }
+!+	000000f2				RB_BLIT_INFO: { TYPE = BLIT_EVENT_CLEAR | CLEAR_MASK = 0xf | LAST = 0 | BUFFER_ID = 0 }
 00000001002275c8:				0000: 70460001 0000001e
 				opcode: CP_COND_REG_EXEC (47) (3 dwords)
 					{ MODE = RENDER_MODE | SYSMEM }
@@ -17658,7 +17658,7 @@ clusters:
 	00000000	RB_BLIT_CLEAR_COLOR_DW1: 0
 	00000000	RB_BLIT_CLEAR_COLOR_DW2: 0
 	00000000	RB_BLIT_CLEAR_COLOR_DW3: 0
-	00000000	RB_BLIT_INFO: { CLEAR_MASK = 0 | LAST = 0 | BUFFER_ID = 0 }
+	00000000	RB_BLIT_INFO: { TYPE = BLIT_EVENT_STORE | CLEAR_MASK = 0 | LAST = 0 | BUFFER_ID = 0 }
 	00000000	RB_DEPTH_FLAG_BUFFER_BASE: 0
 	00000000	RB_DEPTH_FLAG_BUFFER_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 }
 	100094000	RB_MRT_FLAG_BUFFER[0].ADDR: 0x100094000
@@ -17835,7 +17835,7 @@ WARNING: 64b discontinuity (no _LO dword for 8910)
 	00000000	RB_BLIT_CLEAR_COLOR_DW1: 0
 	00000000	RB_BLIT_CLEAR_COLOR_DW2: 0
 	00000000	RB_BLIT_CLEAR_COLOR_DW3: 0
-	00000000	RB_BLIT_INFO: { CLEAR_MASK = 0 | LAST = 0 | BUFFER_ID = 0 }
+	00000000	RB_BLIT_INFO: { TYPE = BLIT_EVENT_STORE | CLEAR_MASK = 0 | LAST = 0 | BUFFER_ID = 0 }
 	00000000	RB_DEPTH_FLAG_BUFFER_BASE: 0
 	00000000	RB_DEPTH_FLAG_BUFFER_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 }
 	100094000	RB_MRT_FLAG_BUFFER[0].ADDR: 0x100094000
diff --git a/src/freedreno/.gitlab-ci/reference/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log b/src/freedreno/.gitlab-ci/reference/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log
index 8995d801208..40a685c845f 100644
--- a/src/freedreno/.gitlab-ci/reference/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log
+++ b/src/freedreno/.gitlab-ci/reference/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log
@@ -446,7 +446,7 @@ cmdstream[0]: 265 dwords
 				RB_BLIT_GMEM_MSAA_CNTL: { SAMPLES = MSAA_ONE }
 000000000115e018:			0000: 4088d501 00000000
 			write RB_BLIT_INFO (88e3)
-				RB_BLIT_INFO: { UNK0 | GMEM | CLEAR_MASK = 0 | LAST = 0 | BUFFER_ID = 0 }
+				RB_BLIT_INFO: { TYPE = BLIT_EVENT_LOAD | CLEAR_MASK = 0 | LAST = 0 | BUFFER_ID = 0 }
 000000000115e020:			0000: 4088e301 00000003
 			write RB_BLIT_DST_INFO (88d7)
 				RB_BLIT_DST_INFO: { TILE_MODE = TILE6_3 | FLAGS | SAMPLES = MSAA_ONE | COLOR_SWAP = WZYX | COLOR_FORMAT = FMT6_8_8_8_8_UNORM }
@@ -484,7 +484,7 @@ cmdstream[0]: 265 dwords
 !+	00000010			RB_BLIT_DST_PITCH: 1024
 !+	01012000			RB_BLIT_FLAG_DST: 0x1012000
 !+	00004001			RB_BLIT_FLAG_DST_PITCH: { PITCH = 64 | ARRAY_PITCH = 1024 }
-!+	00000003			RB_BLIT_INFO: { UNK0 | GMEM | CLEAR_MASK = 0 | LAST = 0 | BUFFER_ID = 0 }
+!+	00000003			RB_BLIT_INFO: { TYPE = BLIT_EVENT_LOAD | CLEAR_MASK = 0 | LAST = 0 | BUFFER_ID = 0 }
 !+	7c400000			RB_CCU_CNTL: { DEPTH_OFFSET_HI = 0 | COLOR_OFFSET_HI = 0 | DEPTH_CACHE_SIZE = CCU_CACHE_SIZE_FULL | DEPTH_OFFSET = 0 | COLOR_CACHE_SIZE = CCU_CACHE_SIZE_QUARTER | COLOR_OFFSET = 0xf8000 }
 !+	00000000			VPC_SO_DISABLE: { 0 }
  +	00000000			SP_TP_WINDOW_OFFSET: { X = 0 | Y = 0 }
@@ -1527,7 +1527,7 @@ cmdstream[0]: 265 dwords
 				RB_BLIT_GMEM_MSAA_CNTL: { SAMPLES = MSAA_ONE }
 000000000115c02c:			0000: 4088d501 00000000
 			write RB_BLIT_INFO (88e3)
-				RB_BLIT_INFO: { CLEAR_MASK = 0 | LAST = 0 | BUFFER_ID = 0 }
+				RB_BLIT_INFO: { TYPE = BLIT_EVENT_STORE | CLEAR_MASK = 0 | LAST = 0 | BUFFER_ID = 0 }
 000000000115c034:			0000: 4088e301 00000000
 			write RB_BLIT_DST_INFO (88d7)
 				RB_BLIT_DST_INFO: { TILE_MODE = TILE6_3 | FLAGS | SAMPLES = MSAA_ONE | COLOR_SWAP = WZYX | COLOR_FORMAT = FMT6_8_8_8_8_UNORM }
@@ -1556,7 +1556,7 @@ cmdstream[0]: 265 dwords
  +	00000010			RB_BLIT_DST_PITCH: 1024
  +	01012000			RB_BLIT_FLAG_DST: 0x1012000
  +	00004001			RB_BLIT_FLAG_DST_PITCH: { PITCH = 64 | ARRAY_PITCH = 1024 }
-!+	00000000			RB_BLIT_INFO: { CLEAR_MASK = 0 | LAST = 0 | BUFFER_ID = 0 }
+!+	00000000			RB_BLIT_INFO: { TYPE = BLIT_EVENT_STORE | CLEAR_MASK = 0 | LAST = 0 | BUFFER_ID = 0 }
 000000000115c068:			0000: 70460001 0000001e
 00000000010583c8:		0000: 70bf8003 0115c000 00000000 0000001c
 		write GRAS_LRZ_CNTL (8100)
diff --git a/src/freedreno/.gitlab-ci/reference/fd-clouds.log b/src/freedreno/.gitlab-ci/reference/fd-clouds.log
index 491c8a74cea..f615ee24895 100644
--- a/src/freedreno/.gitlab-ci/reference/fd-clouds.log
+++ b/src/freedreno/.gitlab-ci/reference/fd-clouds.log
@@ -1625,7 +1625,7 @@ cmdstream[0]: 1023 dwords
 				RB_BLIT_DST_INFO: { TILE_MODE = TILE6_LINEAR | SAMPLES = MSAA_ONE | COLOR_SWAP = WZYX | COLOR_FORMAT = FMT6_8_8_8_X8_UNORM }
 00000000011160dc:			0000: 4888d701 00001880
 			write RB_BLIT_INFO (88e3)
-				RB_BLIT_INFO: { GMEM | CLEAR_MASK = 0xf | LAST = 0 | BUFFER_ID = 0 }
+				RB_BLIT_INFO: { TYPE = BLIT_EVENT_CLEAR | CLEAR_MASK = 0xf | LAST = 0 | BUFFER_ID = 0 }
 00000000011160e4:			0000: 4088e301 000000f2
 			write RB_BLIT_BASE_GMEM (88d6)
 				RB_BLIT_BASE_GMEM: 0
@@ -1677,7 +1677,7 @@ cmdstream[0]: 1023 dwords
  +	00000000			RB_BLIT_CLEAR_COLOR_DW1: 0
  +	00000000			RB_BLIT_CLEAR_COLOR_DW2: 0
  +	00000000			RB_BLIT_CLEAR_COLOR_DW3: 0
-!+	000000f2			RB_BLIT_INFO: { GMEM | CLEAR_MASK = 0xf | LAST = 0 | BUFFER_ID = 0 }
+!+	000000f2			RB_BLIT_INFO: { TYPE = BLIT_EVENT_CLEAR | CLEAR_MASK = 0xf | LAST = 0 | BUFFER_ID = 0 }
  +	7c400004			RB_CCU_CNTL: { CONCURRENT_RESOLVE | DEPTH_OFFSET_HI = 0 | COLOR_OFFSET_HI = 0 | DEPTH_CACHE_SIZE = CCU_CACHE_SIZE_FULL | DEPTH_OFFSET = 0 | COLOR_CACHE_SIZE = CCU_CACHE_SIZE_QUARTER | COLOR_OFFSET = 0xf8000 }
 !+	00000001			VPC_SO_DISABLE: { DISABLE }
  +	00000001			PC_POWER_CNTL: 0x1
@@ -6794,7 +6794,7 @@ cmdstream[0]: 1023 dwords
 				RB_BLIT_SCISSOR_BR: { X = 2175 | Y = 1439 }
 0000000001116130:			0000: 4888d102 00000000 059f087f
 			write RB_BLIT_INFO (88e3)
-				RB_BLIT_INFO: { CLEAR_MASK = 0 | LAST = 0 | BUFFER_ID = 0 }
+				RB_BLIT_INFO: { TYPE = BLIT_EVENT_STORE | CLEAR_MASK = 0 | LAST = 0 | BUFFER_ID = 0 }
 000000000111613c:			0000: 4088e301 00000000
 			write RB_BLIT_DST_INFO (88d7)
 				RB_BLIT_DST_INFO: { TILE_MODE = TILE6_LINEAR | SAMPLES = MSAA_ONE | COLOR_SWAP = WXYZ | COLOR_FORMAT = FMT6_8_8_8_X8_UNORM }
@@ -6828,7 +6828,7 @@ cmdstream[0]: 1023 dwords
 !+	01125000			RB_BLIT_DST: 0x1125000
 !+	00000088			RB_BLIT_DST_PITCH: 8704
 !+	0002fd00			RB_BLIT_DST_ARRAY_PITCH: 12533760
-!+	00000000			RB_BLIT_INFO: { CLEAR_MASK = 0 | LAST = 0 | BUFFER_ID = 0 }
+!+	00000000			RB_BLIT_INFO: { TYPE = BLIT_EVENT_STORE | CLEAR_MASK = 0 | LAST = 0 | BUFFER_ID = 0 }
 0000000001116170:			0000: 70460001 0000001e
 			opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
 0000000001116178:			0000: 70268000
diff --git a/src/freedreno/.gitlab-ci/reference/prefetch-test.log b/src/freedreno/.gitlab-ci/reference/prefetch-test.log
index ee461065288..a4770c144b7 100644
--- a/src/freedreno/.gitlab-ci/reference/prefetch-test.log
+++ b/src/freedreno/.gitlab-ci/reference/prefetch-test.log
@@ -151637,7 +151637,7 @@ clusters:
 	00000000	RB_BLIT_CLEAR_COLOR_DW1: 0
 	00000000	RB_BLIT_CLEAR_COLOR_DW2: 0
 	00000000	RB_BLIT_CLEAR_COLOR_DW3: 0
-	00000000	RB_BLIT_INFO: { CLEAR_MASK = 0 | LAST = 0 | BUFFER_ID = 0 }
+	00000000	RB_BLIT_INFO: { TYPE = BLIT_EVENT_STORE | CLEAR_MASK = 0 | LAST = 0 | BUFFER_ID = 0 }
 	00000000	RB_DEPTH_FLAG_BUFFER_BASE: 0
 	00000000	RB_DEPTH_FLAG_BUFFER_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 }
 	103735000	RB_MRT_FLAG_BUFFER[0].ADDR: 0x103735000
@@ -151814,7 +151814,7 @@ WARNING: 64b discontinuity (no _LO dword for 8910)
 	00000000	RB_BLIT_CLEAR_COLOR_DW1: 0
 	00000000	RB_BLIT_CLEAR_COLOR_DW2: 0
 	00000000	RB_BLIT_CLEAR_COLOR_DW3: 0
-	00000000	RB_BLIT_INFO: { CLEAR_MASK = 0 | LAST = 0 | BUFFER_ID = 0 }
+	00000000	RB_BLIT_INFO: { TYPE = BLIT_EVENT_STORE | CLEAR_MASK = 0 | LAST = 0 | BUFFER_ID = 0 }
 	00000000	RB_DEPTH_FLAG_BUFFER_BASE: 0
 	00000000	RB_DEPTH_FLAG_BUFFER_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 }
 	103735000	RB_MRT_FLAG_BUFFER[0].ADDR: 0x103735000
diff --git a/src/freedreno/registers/adreno/a6xx.xml b/src/freedreno/registers/adreno/a6xx.xml
index 97608603ea6..3ef1b426bc1 100644
--- a/src/freedreno/registers/adreno/a6xx.xml
+++ b/src/freedreno/registers/adreno/a6xx.xml
@@ -3830,10 +3830,16 @@ to upconvert to 32b float internally?
 	<reg32 offset="0x88e1" name="RB_BLIT_CLEAR_COLOR_DW2" usage="rp_blit"/>
 	<reg32 offset="0x88e2" name="RB_BLIT_CLEAR_COLOR_DW3" usage="rp_blit"/>
 
+	<enum name="a6xx_blit_event_type">
+		<value value="0x0" name="BLIT_EVENT_STORE"/>
+		<value value="0x1" name="BLIT_EVENT_STORE_AND_CLEAR"/>
+		<value value="0x2" name="BLIT_EVENT_CLEAR"/>
+		<value value="0x3" name="BLIT_EVENT_LOAD"/>
+	</enum>
+
 	<!-- seems somewhat similar to what we called RB_CLEAR_CNTL on a5xx: -->
 	<reg32 offset="0x88e3" name="RB_BLIT_INFO" usage="rp_blit">
-		<bitfield name="UNK0" pos="0" type="boolean"/> <!-- s8 stencil restore/clear?  But also color restore? -->
-		<bitfield name="GMEM" pos="1" type="boolean"/> <!-- set for restore and clear to gmem? -->
+		<bitfield name="TYPE" low="0" high="1" type="a6xx_blit_event_type"/>
 		<bitfield name="SAMPLE_0" pos="2" type="boolean"/> <!-- takes sample 0 instead of averaging -->
 		<bitfield name="DEPTH" pos="3" type="boolean"/> <!-- z16/z32/z24s8/x24x8 clear or resolve? -->
 		<doc>
diff --git a/src/freedreno/vulkan/tu_clear_blit.cc b/src/freedreno/vulkan/tu_clear_blit.cc
index 53c93aa902c..641e0bddec0 100644
--- a/src/freedreno/vulkan/tu_clear_blit.cc
+++ b/src/freedreno/vulkan/tu_clear_blit.cc
@@ -3226,7 +3226,8 @@ clear_gmem_attachment(struct tu_cmd_buffer *cmd,
    tu_cs_emit(cs, A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(
             blit_base_format<CHIP>(format, false, true)));
 
-   tu_cs_emit_regs(cs, A6XX_RB_BLIT_INFO(.gmem = 1, .clear_mask = clear_mask));
+   tu_cs_emit_regs(cs, A6XX_RB_BLIT_INFO(.type = BLIT_EVENT_CLEAR,
+                                         .clear_mask = clear_mask));
 
    tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
    tu_cs_emit(cs, gmem_offset);
@@ -3525,8 +3526,7 @@ tu_emit_blit(struct tu_cmd_buffer *cmd,
                    A6XX_RB_BLIT_GMEM_MSAA_CNTL(tu_msaa_samples(attachment->samples)));
 
    tu_cs_emit_regs(cs, A6XX_RB_BLIT_INFO(
-      .unk0 = !resolve,
-      .gmem = !resolve,
+      .type = resolve ? BLIT_EVENT_STORE : BLIT_EVENT_LOAD,
       .sample_0 = vk_format_is_int(attachment->format) ||
          vk_format_is_depth_or_stencil(attachment->format),
       .depth = vk_format_is_depth_or_stencil(attachment->format),));
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.cc b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.cc
index 5c2504c162f..e2b0b36eab5 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.cc
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.cc
@@ -1356,8 +1356,7 @@ emit_restore_blit(struct fd_batch *batch, struct fd_ringbuffer *ring,
 
    OUT_REG(ring,
            A6XX_RB_BLIT_INFO(
-                 .unk0 = true,
-                 .gmem = true,
+                 .type = BLIT_EVENT_LOAD,
                  .sample_0 = util_format_is_pure_integer(psurf->format),
                  .depth = (buffer == FD_BUFFER_DEPTH),
            ),
@@ -1429,8 +1428,8 @@ emit_subpass_clears(struct fd_batch *batch, struct fd_batch_subpass *subpass)
                      A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(fd6_color_format(pfmt, TILE6_LINEAR)));
 
          OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
-         OUT_RING(ring,
-                  A6XX_RB_BLIT_INFO_GMEM | A6XX_RB_BLIT_INFO_CLEAR_MASK(0xf));
+         OUT_RING(ring, A6XX_RB_BLIT_INFO_TYPE(BLIT_EVENT_CLEAR) |
+                           A6XX_RB_BLIT_INFO_CLEAR_MASK(0xf));
 
          OUT_PKT4(ring, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
          OUT_RING(ring, gmem->cbuf_base[i]);
@@ -1484,8 +1483,7 @@ emit_subpass_clears(struct fd_batch *batch, struct fd_batch_subpass *subpass)
                   A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(fd6_color_format(pfmt, TILE6_LINEAR)));
 
       OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
-      OUT_RING(ring, A6XX_RB_BLIT_INFO_GMEM |
-                        // XXX UNK0 for separate stencil ??
+      OUT_RING(ring, A6XX_RB_BLIT_INFO_TYPE(BLIT_EVENT_CLEAR) |
                         A6XX_RB_BLIT_INFO_DEPTH |
                         A6XX_RB_BLIT_INFO_CLEAR_MASK(mask));
 
@@ -1510,8 +1508,7 @@ emit_subpass_clears(struct fd_batch *batch, struct fd_batch_subpass *subpass)
                         A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(FMT6_8_UINT));
 
       OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
-      OUT_RING(ring, A6XX_RB_BLIT_INFO_GMEM |
-                        // A6XX_RB_BLIT_INFO_UNK0 |
+      OUT_RING(ring, A6XX_RB_BLIT_INFO_TYPE(BLIT_EVENT_CLEAR) |
                         A6XX_RB_BLIT_INFO_DEPTH |
                         A6XX_RB_BLIT_INFO_CLEAR_MASK(0x1));
 
@@ -1699,13 +1696,14 @@ emit_resolve_blit(struct fd_batch *batch, struct fd_ringbuffer *ring,
 
    switch (buffer) {
    case FD_BUFFER_COLOR:
+      info = A6XX_RB_BLIT_INFO_TYPE(BLIT_EVENT_STORE);
       break;
    case FD_BUFFER_STENCIL:
-      info |= A6XX_RB_BLIT_INFO_UNK0;
+      info = A6XX_RB_BLIT_INFO_TYPE(BLIT_EVENT_STORE_AND_CLEAR);
       stencil = true;
       break;
    case FD_BUFFER_DEPTH:
-      info |= A6XX_RB_BLIT_INFO_DEPTH;
+      info = A6XX_RB_BLIT_INFO_TYPE(BLIT_EVENT_STORE) | A6XX_RB_BLIT_INFO_DEPTH;
       break;
    }