From 48da8eab55640603c408348d5ada3e03fec81352 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?= Date: Thu, 27 Jun 2024 14:06:39 -0700 Subject: [PATCH] intel/dev: Add comment documenting the PAT entries MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Like said in the past patch, coherency is not needed and there was a miss understating about caching used by CPU and GPU. With this new comment it much better explained. Ref: Bspec 45101 (r51017) Ref: Bspec 71582 (r59285) Reviewed-by: Jordan Justen Reviewed-by: Jianxun Zhang Signed-off-by: José Roberto de Souza Part-of: --- src/intel/dev/intel_device_info.c | 21 +++++++++++++++++++++ src/intel/dev/intel_device_info.py | 8 ++++++-- 2 files changed, 27 insertions(+), 2 deletions(-) diff --git a/src/intel/dev/intel_device_info.c b/src/intel/dev/intel_device_info.c index aabcd7056e5..29d83f1bed6 100644 --- a/src/intel/dev/intel_device_info.c +++ b/src/intel/dev/intel_device_info.c @@ -984,10 +984,15 @@ static const struct intel_device_info intel_device_info_ehl_2x4 = { .gt = _gt, .num_slices = _slices, .l3_banks = _l3, \ .simulator_id = 22, \ .max_eus_per_subslice = 16, \ + /* BSpec 45101 (r51017) */ \ .pat = { \ + /* CPU: WB, GPU: PAT 0 => WB, 2WAY */ \ .cached_coherent = PAT_ENTRY(0, WB), \ + /* CPU: WC, GPU: PAT 1 => WC */ \ .scanout = PAT_ENTRY(1, WC), \ + /* CPU: WB, GPU: PAT 0 => WB, 2WAY */ \ .writeback_incoherent = PAT_ENTRY(0, WB), \ + /* CPU: WC, GPU: PAT 1 => WC */ \ .writecombining = PAT_ENTRY(1, WC), \ }, \ .cooperative_matrix_configurations = { \ @@ -1129,10 +1134,15 @@ static const struct intel_device_info intel_device_info_sg1 = { .has_ray_tracing = true, \ .has_flat_ccs = true, \ /* There is no PAT table for DG2, using TGL ones */ \ + /* BSpec 45101 (r51017) */ \ .pat = { \ + /* CPU: WB, GPU: PAT 0 => WB, 2WAY */ \ .cached_coherent = PAT_ENTRY(0, WB), \ + /* CPU: WC, GPU: PAT 1 => WC */ \ .scanout = PAT_ENTRY(1, WC), \ + /* CPU: WB, GPU: PAT 0 => WB, 2WAY */ \ .writeback_incoherent = PAT_ENTRY(0, WB), \ + /* CPU: WC, GPU: PAT 1 => WC */ \ .writecombining = PAT_ENTRY(1, WC), \ } @@ -1172,10 +1182,15 @@ static const struct intel_device_info intel_device_info_atsm_g11 = { .has_coarse_pixel_primitive_and_cb = true, \ .has_mesh_shading = true, \ .has_ray_tracing = true, \ + /* BSpec 45101 (r51017) */ \ .pat = { \ + /* CPU: WB, GPU: PAT 3 => WB, 1WAY */ \ .cached_coherent = PAT_ENTRY(3, WB), \ + /* CPU: WC, GPU: PAT 1 => WC */ \ .scanout = PAT_ENTRY(1, WC), \ + /* CPU: WB, GPU: PAT 0 => WB, 0WAY */ \ .writeback_incoherent = PAT_ENTRY(0, WB), \ + /* CPU: WC, GPU: PAT 1 => WC */ \ .writecombining = PAT_ENTRY(1, WC), \ } @@ -1213,11 +1228,17 @@ static const struct intel_device_info intel_device_info_arl_h = { .has_mesh_shading = true, \ .has_ray_tracing = true, \ .has_indirect_unroll = true, \ + /* BSpec 71582 (r59285) */ \ .pat = { \ + /* CPU: WB, GPU: PAT 1 => WB, 1WAY */ \ .cached_coherent = PAT_ENTRY(1, WB), \ + /* CPU: WC, GPU: PAT 6 => XD */ \ .scanout = PAT_ENTRY(6, WC), \ + /* CPU: WB, GPU: PAT 0 => WB, 0WAY */ \ .writeback_incoherent = PAT_ENTRY(0, WB), \ + /* CPU: WC, GPU: PAT 6 => XD */ \ .writecombining = PAT_ENTRY(6, WC), \ + /* CPU: WC, GPU: PAT 11 => XD, compressed */ \ .compressed = PAT_ENTRY(11, WC) \ }, \ .cooperative_matrix_configurations = { \ diff --git a/src/intel/dev/intel_device_info.py b/src/intel/dev/intel_device_info.py index 8faa721f1a8..4f5ca265e17 100644 --- a/src/intel/dev/intel_device_info.py +++ b/src/intel/dev/intel_device_info.py @@ -143,8 +143,12 @@ Struct("intel_memory_class_instance", Enum("intel_device_info_mmap_mode", [EnumValue("INTEL_DEVICE_INFO_MMAP_MODE_UC", value=0), - "INTEL_DEVICE_INFO_MMAP_MODE_WC", - "INTEL_DEVICE_INFO_MMAP_MODE_WB" + EnumValue("INTEL_DEVICE_INFO_MMAP_MODE_WC"), + EnumValue("INTEL_DEVICE_INFO_MMAP_MODE_WB"), + EnumValue("INTEL_DEVICE_INFO_MMAP_MODE_XD", + comment=dedent("""\ + Xe2+ only. Only supported in GPU side and used for displayable + buffers.""")) ]) Struct("intel_device_info_pat_entry",