diff --git a/src/freedreno/.gitlab-ci/reference/crash.log b/src/freedreno/.gitlab-ci/reference/crash.log index 1cef3af2803..5450dd5b8ec 100644 --- a/src/freedreno/.gitlab-ci/reference/crash.log +++ b/src/freedreno/.gitlab-ci/reference/crash.log @@ -7239,7 +7239,7 @@ clusters: 00000000 VPC_VAR[0x1].DISABLE: 0 00000000 VPC_VAR[0x2].DISABLE: 0 00000000 VPC_VAR[0x3].DISABLE: 0 - 00000000 VPC_SO_CNTL: { 0 } + 00000000 VPC_SO_CNTL: { ADDR = 0 } 00000000 VPC_SO_STREAM_COUNTS_LO: 0 00000000 VPC_SO_STREAM_COUNTS_HI: 0 00000000 VPC_SO[0].BUFFER_BASE: 0 @@ -7276,7 +7276,7 @@ clusters: 00ff0001 VPC_GS_PACK: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 } 00ff0001 VPC_DS_PACK: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 } ff00ff00 VPC_CNTL_0: { NUMNONPOSVAR = 0 | PRIMIDLOC = 255 | VIEWIDLOC = 255 } - 00000000 VPC_SO_BUF_CNTL: { 0 } + 00000000 VPC_SO_STREAM_CNTL: { BUF0_STREAM = 0 | BUF1_STREAM = 0 | BUF2_STREAM = 0 | BUF3_STREAM = 0 | STREAM_ENABLE = 0 } 00000000 VPC_SO_DISABLE: { 0 } - context: 1 00000000 VPC_VARYING_INTERP[0].MODE: 0 @@ -7301,7 +7301,7 @@ clusters: 00000000 VPC_VAR[0x1].DISABLE: 0 00000000 VPC_VAR[0x2].DISABLE: 0 00000000 VPC_VAR[0x3].DISABLE: 0 - 00000000 VPC_SO_CNTL: { 0 } + 00000000 VPC_SO_CNTL: { ADDR = 0 } 00000000 VPC_SO_STREAM_COUNTS_LO: 0 00000000 VPC_SO_STREAM_COUNTS_HI: 0 00000000 VPC_SO[0].BUFFER_BASE: 0 @@ -7338,7 +7338,7 @@ clusters: 00ff0001 VPC_GS_PACK: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 } 00ff0001 VPC_DS_PACK: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 } ff00ff00 VPC_CNTL_0: { NUMNONPOSVAR = 0 | PRIMIDLOC = 255 | VIEWIDLOC = 255 } - 00000000 VPC_SO_BUF_CNTL: { 0 } + 00000000 VPC_SO_STREAM_CNTL: { BUF0_STREAM = 0 | BUF1_STREAM = 0 | BUF2_STREAM = 0 | BUF3_STREAM = 0 | STREAM_ENABLE = 0 } 00000000 VPC_SO_DISABLE: { 0 } - cluster-name: CLUSTER_FE - context: 0 @@ -7347,7 +7347,7 @@ clusters: 00ff0001 VPC_GS_PACK: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 } 00ff0001 VPC_DS_PACK: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 } ff00ff00 VPC_CNTL_0: { NUMNONPOSVAR = 0 | PRIMIDLOC = 255 | VIEWIDLOC = 255 } - 00000000 VPC_SO_BUF_CNTL: { 0 } + 00000000 VPC_SO_STREAM_CNTL: { BUF0_STREAM = 0 | BUF1_STREAM = 0 | BUF2_STREAM = 0 | BUF3_STREAM = 0 | STREAM_ENABLE = 0 } 00000000 VPC_SO_DISABLE: { 0 } 00000000 PC_TESS_NUM_VERTEX: 0 00000000 PC_HS_INPUT_SIZE: { SIZE = 0 } @@ -7607,7 +7607,7 @@ clusters: 00ff0001 VPC_GS_PACK: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 } 00ff0001 VPC_DS_PACK: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 } ff00ff00 VPC_CNTL_0: { NUMNONPOSVAR = 0 | PRIMIDLOC = 255 | VIEWIDLOC = 255 } - 00000000 VPC_SO_BUF_CNTL: { 0 } + 00000000 VPC_SO_STREAM_CNTL: { BUF0_STREAM = 0 | BUF1_STREAM = 0 | BUF2_STREAM = 0 | BUF3_STREAM = 0 | STREAM_ENABLE = 0 } 00000000 VPC_SO_DISABLE: { 0 } 00000000 PC_TESS_NUM_VERTEX: 0 00000000 PC_HS_INPUT_SIZE: { SIZE = 0 } @@ -7870,16 +7870,16 @@ clusters: 0000ffff VPC_VS_LAYER_CNTL: { LAYERLOC = 255 | VIEWLOC = 255 } 0000ffff VPC_GS_LAYER_CNTL: { LAYERLOC = 255 | VIEWLOC = 255 } 0000ffff VPC_DS_LAYER_CNTL: { LAYERLOC = 255 | VIEWLOC = 255 } - 00000000 VPC_UNKNOWN_9107: 0 + 00000000 VPC_UNKNOWN_9107: { 0 } 00000003 VPC_POLYGON_MODE: { MODE = POLYMODE6_TRIANGLES } 00000000 VPC_UNKNOWN_9300: 0 00ff0001 VPC_VS_PACK: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 } 00ff0001 VPC_GS_PACK: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 } 00ff0001 VPC_DS_PACK: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 } ff00ff00 VPC_CNTL_0: { NUMNONPOSVAR = 0 | PRIMIDLOC = 255 | VIEWIDLOC = 255 } - 00000000 VPC_SO_BUF_CNTL: { 0 } + 00000000 VPC_SO_STREAM_CNTL: { BUF0_STREAM = 0 | BUF1_STREAM = 0 | BUF2_STREAM = 0 | BUF3_STREAM = 0 | STREAM_ENABLE = 0 } 00000000 VPC_SO_DISABLE: { 0 } - 00000000 PC_UNKNOWN_9980: 0 + 00000000 PC_RASTER_CNTL: { STREAM = 0 } 00000003 PC_POLYGON_MODE: { MODE = POLYMODE6_TRIANGLES } 00000002 PC_PRIMITIVE_CNTL_0: { PROVOKING_VTX_LAST } 00000001 PC_VS_OUT_CNTL: { STRIDE_IN_VPC = 1 | CLIP_MASK = 0 } @@ -7897,16 +7897,16 @@ clusters: 0000ffff VPC_VS_LAYER_CNTL: { LAYERLOC = 255 | VIEWLOC = 255 } 0000ffff VPC_GS_LAYER_CNTL: { LAYERLOC = 255 | VIEWLOC = 255 } 0000ffff VPC_DS_LAYER_CNTL: { LAYERLOC = 255 | VIEWLOC = 255 } - 00000000 VPC_UNKNOWN_9107: 0 + 00000000 VPC_UNKNOWN_9107: { 0 } 00000003 VPC_POLYGON_MODE: { MODE = POLYMODE6_TRIANGLES } 00000000 VPC_UNKNOWN_9300: 0 00ff0001 VPC_VS_PACK: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 } 00ff0001 VPC_GS_PACK: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 } 00ff0001 VPC_DS_PACK: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 } ff00ff00 VPC_CNTL_0: { NUMNONPOSVAR = 0 | PRIMIDLOC = 255 | VIEWIDLOC = 255 } - 00000000 VPC_SO_BUF_CNTL: { 0 } + 00000000 VPC_SO_STREAM_CNTL: { BUF0_STREAM = 0 | BUF1_STREAM = 0 | BUF2_STREAM = 0 | BUF3_STREAM = 0 | STREAM_ENABLE = 0 } 00000000 VPC_SO_DISABLE: { 0 } - 00000000 PC_UNKNOWN_9980: 0 + 00000000 PC_RASTER_CNTL: { STREAM = 0 } 00000003 PC_POLYGON_MODE: { MODE = POLYMODE6_TRIANGLES } 00000002 PC_PRIMITIVE_CNTL_0: { PROVOKING_VTX_LAST } 00000001 PC_VS_OUT_CNTL: { STRIDE_IN_VPC = 1 | CLIP_MASK = 0 } diff --git a/src/freedreno/.gitlab-ci/reference/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log b/src/freedreno/.gitlab-ci/reference/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log index 99ef25fafe5..7bbaa5de1fd 100644 --- a/src/freedreno/.gitlab-ci/reference/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log +++ b/src/freedreno/.gitlab-ci/reference/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log @@ -127,7 +127,7 @@ t4 write RB_UNKNOWN_88F0 (88f0) RB_UNKNOWN_88F0: 0 000000000105813c: 0000: 4888f001 00000000 t4 write VPC_UNKNOWN_9107 (9107) - VPC_UNKNOWN_9107: 0 + VPC_UNKNOWN_9107: { 0 } 0000000001058144: 0000: 48910701 00000000 t4 write VPC_POINT_COORD_INVERT (9236) VPC_POINT_COORD_INVERT: { 0 } @@ -138,8 +138,8 @@ t4 write VPC_UNKNOWN_9300 (9300) t4 write VPC_SO_DISABLE (9306) VPC_SO_DISABLE: { DISABLE } 000000000105815c: 0000: 48930601 00000001 -t4 write PC_UNKNOWN_9980 (9980) - PC_UNKNOWN_9980: 0 +t4 write PC_RASTER_CNTL (9980) + PC_RASTER_CNTL: { STREAM = 0 } 0000000001058164: 0000: 40998001 00000000 t4 write PC_PRIMITIVE_CNTL_6 (9b06) PC_PRIMITIVE_CNTL_6: { STRIDE_IN_VPC = 0 } @@ -324,7 +324,7 @@ t7 opcode: CP_BLIT (2c) (2 dwords) + 00000000 RB_UNKNOWN_8E01: 0 !+ 00100000 RB_UNKNOWN_8E04: 0x100000 !+ 10000000 RB_CCU_CNTL: { OFFSET = 0x20000 } - + 00000000 VPC_UNKNOWN_9107: 0 + + 00000000 VPC_UNKNOWN_9107: { 0 } + 00000000 VPC_UNKNOWN_9210: 0 + 00000000 VPC_UNKNOWN_9211: 0 + 00000000 VPC_POINT_COORD_INVERT: { 0 } @@ -333,7 +333,7 @@ t7 opcode: CP_BLIT (2c) (2 dwords) + 00000000 VPC_UNKNOWN_9600: 0 + 00000000 VPC_UNKNOWN_9602: FALSE !+ 0000001f PC_MODE_CNTL: 0x1f - + 00000000 PC_UNKNOWN_9980: 0 + + 00000000 PC_RASTER_CNTL: { STREAM = 0 } + 00000000 PC_PRIMITIVE_CNTL_6: { STRIDE_IN_VPC = 0 } + 00000000 PC_MULTIVIEW_CNTL: { VIEWS = 0 } + 00000000 PC_UNKNOWN_9E72: 0 @@ -966,8 +966,8 @@ t4 write VPC_VAR[0].DISABLE (9212) VPC_VAR[0x3].DISABLE: 0xffffffff 000000000105427c: 0000: 40921204 fffffff0 ffffffff ffffffff ffffffff t7 opcode: CP_CONTEXT_REG_BUNCH (5c) (5 dwords) - VPC_SO_CNTL: { 0 } - VPC_SO_BUF_CNTL: { 0 } + VPC_SO_CNTL: { ADDR = 0 } + VPC_SO_STREAM_CNTL: { BUF0_STREAM = 0 | BUF1_STREAM = 0 | BUF2_STREAM = 0 | BUF3_STREAM = 0 | STREAM_ENABLE = 0 } 0000000001054290: 0000: 70dc0004 00009216 00000000 00009305 00000000 t4 write SP_VS_OUT[0].REG (a803) SP_VS_OUT[0].REG: { A_REGID = r2.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0xf } @@ -1446,10 +1446,10 @@ t7 opcode: CP_DRAW_INDIRECT_MULTI (2a) (12 dwords) !+ ffffffff VPC_VAR[0x1].DISABLE: 0xffffffff !+ ffffffff VPC_VAR[0x2].DISABLE: 0xffffffff !+ ffffffff VPC_VAR[0x3].DISABLE: 0xffffffff - + 00000000 VPC_SO_CNTL: { 0 } + + 00000000 VPC_SO_CNTL: { ADDR = 0 } !+ 00ff0408 VPC_VS_PACK: { STRIDE_IN_VPC = 8 | POSITIONLOC = 4 | PSIZELOC = 255 | EXTRAPOS = 0 } !+ ff01ff04 VPC_CNTL_0: { NUMNONPOSVAR = 4 | PRIMIDLOC = 255 | VARYING | VIEWIDLOC = 255 } - + 00000000 VPC_SO_BUF_CNTL: { 0 } + + 00000000 VPC_SO_STREAM_CNTL: { BUF0_STREAM = 0 | BUF1_STREAM = 0 | BUF2_STREAM = 0 | BUF3_STREAM = 0 | STREAM_ENABLE = 0 } !+ ffffffff PC_RESTART_INDEX: 4294967295 + 00000000 PC_PRIMID_PASSTHRU: FALSE !+ 00000003 PC_POLYGON_MODE: { MODE = POLYMODE6_TRIANGLES } diff --git a/src/freedreno/.gitlab-ci/reference/fd-clouds.log b/src/freedreno/.gitlab-ci/reference/fd-clouds.log index 2797eee1fb8..e2f0c7c9634 100644 --- a/src/freedreno/.gitlab-ci/reference/fd-clouds.log +++ b/src/freedreno/.gitlab-ci/reference/fd-clouds.log @@ -129,8 +129,8 @@ t4 write PC_PRIMID_PASSTHRU (9806) t4 write 0x9990 (9990) 0x9990: 00000000 0000000001d91144: 0000: 48999001 00000000 -t4 write PC_UNKNOWN_9980 (9980) - PC_UNKNOWN_9980: 0 +t4 write PC_RASTER_CNTL (9980) + PC_RASTER_CNTL: { STREAM = 0 } 0000000001d9114c: 0000: 40998001 00000000 t4 write PC_MULTIVIEW_CNTL (9b07) PC_MULTIVIEW_CNTL: { VIEWS = 0 } @@ -224,8 +224,8 @@ t7 opcode: CP_SET_DRAW_STATE (43) (4 dwords) { ADDR_LO = 0 } { ADDR_HI = 0 } 0000000001d91238: 0000: 70438003 00040000 00000000 00000000 -t4 write VPC_SO_BUF_CNTL (9305) - VPC_SO_BUF_CNTL: { 0 } +t4 write VPC_SO_STREAM_CNTL (9305) + VPC_SO_STREAM_CNTL: { BUF0_STREAM = 0 | BUF1_STREAM = 0 | BUF2_STREAM = 0 | BUF3_STREAM = 0 | STREAM_ENABLE = 0 } 0000000001d91248: 0000: 48930501 00000000 t4 write GRAS_LRZ_CNTL (8100) GRAS_LRZ_CNTL: { 0 } @@ -755,7 +755,7 @@ t4 write VPC_VS_CLIP_CNTL (9101) VPC_VS_CLIP_CNTL: { CLIP_MASK = 0 | CLIP_DIST_03_LOC = 255 | CLIP_DIST_47_LOC = 255 } 0000000001121140: 0000: 48910101 00ffff00 t4 write VPC_UNKNOWN_9107 (9107) - VPC_UNKNOWN_9107: 0 + VPC_UNKNOWN_9107: { 0 } 0000000001121148: 0000: 48910701 00000000 t4 write VFD_CONTROL_1 (a001) VFD_CONTROL_1: { REGID4VTX = r63.x | REGID4INST = r63.x | REGID4PRIMID = r63.x | REGID4VIEWID = r63.x } @@ -1041,7 +1041,7 @@ t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) !+ 7c400004 RB_CCU_CNTL: { OFFSET = 0xf8000 | GMEM | UNK2 } !+ 00ffff00 VPC_VS_CLIP_CNTL: { CLIP_MASK = 0 | CLIP_DIST_03_LOC = 255 | CLIP_DIST_47_LOC = 255 } !+ 0000ffff VPC_VS_LAYER_CNTL: { LAYERLOC = 255 | VIEWLOC = 255 } - + 00000000 VPC_UNKNOWN_9107: 0 + + 00000000 VPC_UNKNOWN_9107: { 0 } !+ 00000003 VPC_POLYGON_MODE: { MODE = POLYMODE6_TRIANGLES } + 00000000 VPC_UNKNOWN_9210: 0 + 00000000 VPC_UNKNOWN_9211: 0 @@ -1053,7 +1053,7 @@ t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) + 00000000 VPC_UNKNOWN_9300: 0 !+ 00ff0004 VPC_VS_PACK: { STRIDE_IN_VPC = 4 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 } !+ ff00ff00 VPC_CNTL_0: { NUMNONPOSVAR = 0 | PRIMIDLOC = 255 | VIEWIDLOC = 255 } - + 00000000 VPC_SO_BUF_CNTL: { 0 } + + 00000000 VPC_SO_STREAM_CNTL: { BUF0_STREAM = 0 | BUF1_STREAM = 0 | BUF2_STREAM = 0 | BUF3_STREAM = 0 | STREAM_ENABLE = 0 } + 00000000 VPC_SO_DISABLE: { 0 } + 00000000 VPC_UNKNOWN_9600: 0 + 00000000 VPC_UNKNOWN_9602: FALSE @@ -1061,7 +1061,7 @@ t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) !+ 0000001f PC_MODE_CNTL: 0x1f !+ 00000001 PC_UNKNOWN_9805: 0x1 + 00000000 PC_PRIMID_PASSTHRU: FALSE - + 00000000 PC_UNKNOWN_9980: 0 + + 00000000 PC_RASTER_CNTL: { STREAM = 0 } !+ 00000003 PC_POLYGON_MODE: { MODE = POLYMODE6_TRIANGLES } + 00000000 0x9990: 00000000 !+ 00000002 PC_PRIMITIVE_CNTL_0: { PROVOKING_VTX_LAST } @@ -2070,7 +2070,7 @@ t4 write VPC_VS_CLIP_CNTL (9101) VPC_VS_CLIP_CNTL: { CLIP_MASK = 0 | CLIP_DIST_03_LOC = 255 | CLIP_DIST_47_LOC = 255 } 0000000001120140: 0000: 48910101 00ffff00 t4 write VPC_UNKNOWN_9107 (9107) - VPC_UNKNOWN_9107: 0 + VPC_UNKNOWN_9107: { 0 } 0000000001120148: 0000: 48910701 00000000 t4 write SP_FS_INSTRLEN (ab05) SP_FS_INSTRLEN: 88 @@ -5272,7 +5272,7 @@ t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords) + 00000000 RB_STENCILWRMASK: { WRMASK = 0 | BFWRMASK = 0 } + 00ffff00 VPC_VS_CLIP_CNTL: { CLIP_MASK = 0 | CLIP_DIST_03_LOC = 255 | CLIP_DIST_47_LOC = 255 } + 0000ffff VPC_VS_LAYER_CNTL: { LAYERLOC = 255 | VIEWLOC = 255 } - + 00000000 VPC_UNKNOWN_9107: 0 + + 00000000 VPC_UNKNOWN_9107: { 0 } + 00000000 VPC_VARYING_INTERP[0].MODE: 0 + 00000000 VPC_VARYING_INTERP[0x1].MODE: 0 + 00000000 VPC_VARYING_INTERP[0x2].MODE: 0 diff --git a/src/freedreno/registers/adreno/a6xx.xml b/src/freedreno/registers/adreno/a6xx.xml index 7327ba6db8a..b15d66c59d3 100644 --- a/src/freedreno/registers/adreno/a6xx.xml +++ b/src/freedreno/registers/adreno/a6xx.xml @@ -2670,7 +2670,11 @@ to upconvert to 32b float internally? - + + + + + @@ -2692,9 +2696,32 @@ to upconvert to 32b float internally? - - - + + + + @@ -2769,14 +2796,15 @@ to upconvert to 32b float internally? - - - - - - - - + + + + + + + @@ -2852,7 +2880,13 @@ to upconvert to 32b float internally? - + + + + + + + diff --git a/src/freedreno/vulkan/tu_cmd_buffer.c b/src/freedreno/vulkan/tu_cmd_buffer.c index 8d85422d24b..a152965274c 100644 --- a/src/freedreno/vulkan/tu_cmd_buffer.c +++ b/src/freedreno/vulkan/tu_cmd_buffer.c @@ -778,7 +778,7 @@ tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs) tu_cs_emit_regs(cs, A6XX_VPC_SO_DISABLE(true)); - tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9980, 0); + tu_cs_emit_write_reg(cs, REG_A6XX_PC_RASTER_CNTL, 0); tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_A81B, 0); diff --git a/src/freedreno/vulkan/tu_pipeline.c b/src/freedreno/vulkan/tu_pipeline.c index 6fe57972eab..85911fd6edb 100644 --- a/src/freedreno/vulkan/tu_pipeline.c +++ b/src/freedreno/vulkan/tu_pipeline.c @@ -619,7 +619,7 @@ tu6_setup_streamout(struct tu_cs *cs, tu_cs_emit_pkt7(cs, CP_CONTEXT_REG_BUNCH, 4); tu_cs_emit(cs, REG_A6XX_VPC_SO_CNTL); tu_cs_emit(cs, 0); - tu_cs_emit(cs, REG_A6XX_VPC_SO_BUF_CNTL); + tu_cs_emit(cs, REG_A6XX_VPC_SO_STREAM_CNTL); tu_cs_emit(cs, 0); return; } @@ -664,19 +664,18 @@ tu6_setup_streamout(struct tu_cs *cs, } tu_cs_emit_pkt7(cs, CP_CONTEXT_REG_BUNCH, 12 + 2 * prog_count); - tu_cs_emit(cs, REG_A6XX_VPC_SO_BUF_CNTL); - tu_cs_emit(cs, A6XX_VPC_SO_BUF_CNTL_ENABLE | - COND(ncomp[0] > 0, A6XX_VPC_SO_BUF_CNTL_BUF0) | - COND(ncomp[1] > 0, A6XX_VPC_SO_BUF_CNTL_BUF1) | - COND(ncomp[2] > 0, A6XX_VPC_SO_BUF_CNTL_BUF2) | - COND(ncomp[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3)); + tu_cs_emit(cs, REG_A6XX_VPC_SO_STREAM_CNTL); + tu_cs_emit(cs, A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE(0x1) | + COND(ncomp[0] > 0, A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM(1)) | + COND(ncomp[1] > 0, A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM(1)) | + COND(ncomp[2] > 0, A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM(1)) | + COND(ncomp[3] > 0, A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM(1))); for (uint32_t i = 0; i < 4; i++) { tu_cs_emit(cs, REG_A6XX_VPC_SO_NCOMP(i)); tu_cs_emit(cs, ncomp[i]); } - /* note: "VPC_SO_CNTL" write seems to be responsible for resetting the SO_PROG */ tu_cs_emit(cs, REG_A6XX_VPC_SO_CNTL); - tu_cs_emit(cs, A6XX_VPC_SO_CNTL_ENABLE); + tu_cs_emit(cs, A6XX_VPC_SO_CNTL_RESET); for (uint32_t i = 0; i < prog_count; i++) { tu_cs_emit(cs, REG_A6XX_VPC_SO_PROG); tu_cs_emit(cs, prog[i]); diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_emit.c b/src/gallium/drivers/freedreno/a6xx/fd6_emit.c index e07abee9c9d..54c5d7bc28c 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_emit.c +++ b/src/gallium/drivers/freedreno/a6xx/fd6_emit.c @@ -772,7 +772,7 @@ fd6_emit_streamout(struct fd_ringbuffer *ring, struct fd6_emit *emit, struct ir3 OUT_PKT7(obj, CP_CONTEXT_REG_BUNCH, 4); OUT_RING(obj, REG_A6XX_VPC_SO_CNTL); OUT_RING(obj, 0); - OUT_RING(obj, REG_A6XX_VPC_SO_BUF_CNTL); + OUT_RING(obj, REG_A6XX_VPC_SO_STREAM_CNTL); OUT_RING(obj, 0); fd6_emit_take_group(emit, obj, FD6_GROUP_SO, ENABLE_ALL); @@ -1211,7 +1211,7 @@ fd6_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring) WRITE(REG_A6XX_VPC_SO_DISABLE, A6XX_VPC_SO_DISABLE(true).value); - WRITE(REG_A6XX_PC_UNKNOWN_9980, 0); + WRITE(REG_A6XX_PC_RASTER_CNTL, 0); WRITE(REG_A6XX_PC_MULTIVIEW_CNTL, 0); @@ -1256,8 +1256,8 @@ fd6_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring) OUT_RING(ring, CP_SET_DRAW_STATE__1_ADDR_LO(0)); OUT_RING(ring, CP_SET_DRAW_STATE__2_ADDR_HI(0)); - OUT_PKT4(ring, REG_A6XX_VPC_SO_BUF_CNTL, 1); - OUT_RING(ring, 0x00000000); /* VPC_SO_BUF_CNTL */ + OUT_PKT4(ring, REG_A6XX_VPC_SO_STREAM_CNTL, 1); + OUT_RING(ring, 0x00000000); /* VPC_SO_STREAM_CNTL */ OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_CNTL, 1); OUT_RING(ring, 0x00000000); diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_program.c b/src/gallium/drivers/freedreno/a6xx/fd6_program.c index 406ad0b54b0..2eff56f918d 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_program.c +++ b/src/gallium/drivers/freedreno/a6xx/fd6_program.c @@ -201,12 +201,12 @@ setup_stream_out(struct fd6_program_state *state, const struct ir3_shader_varian struct fd_ringbuffer *ring = state->streamout_stateobj; OUT_PKT7(ring, CP_CONTEXT_REG_BUNCH, 12 + (2 * prog_count)); - OUT_RING(ring, REG_A6XX_VPC_SO_BUF_CNTL); - OUT_RING(ring, A6XX_VPC_SO_BUF_CNTL_ENABLE | - COND(ncomp[0] > 0, A6XX_VPC_SO_BUF_CNTL_BUF0) | - COND(ncomp[1] > 0, A6XX_VPC_SO_BUF_CNTL_BUF1) | - COND(ncomp[2] > 0, A6XX_VPC_SO_BUF_CNTL_BUF2) | - COND(ncomp[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3)); + OUT_RING(ring, REG_A6XX_VPC_SO_STREAM_CNTL); + OUT_RING(ring, A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE(0x1) | + COND(ncomp[0] > 0, A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM(1)) | + COND(ncomp[1] > 0, A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM(1)) | + COND(ncomp[2] > 0, A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM(1)) | + COND(ncomp[3] > 0, A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM(1))); OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(0)); OUT_RING(ring, ncomp[0]); OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(1)); @@ -216,7 +216,7 @@ setup_stream_out(struct fd6_program_state *state, const struct ir3_shader_varian OUT_RING(ring, REG_A6XX_VPC_SO_NCOMP(3)); OUT_RING(ring, ncomp[3]); OUT_RING(ring, REG_A6XX_VPC_SO_CNTL); - OUT_RING(ring, A6XX_VPC_SO_CNTL_ENABLE); + OUT_RING(ring, A6XX_VPC_SO_CNTL_RESET); for (unsigned i = 0; i < prog_count; i++) { OUT_RING(ring, REG_A6XX_VPC_SO_PROG); OUT_RING(ring, prog[i]);