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all: rename gl_shader_stage_uses_workgroup to mesa_shader_stage_uses_workgroup

Browse Source 
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36569>
This commit is contained in:
Qiang Yu
2025-08-05 16:50:43 +08:00
parent 4ff341f2fc
commit 4847e0b380
24 changed files with 38 additions and 38 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/intel/compiler/brw_compiler.h
+1 -1
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@@ -1355,7 +1355,7 @@ DEFINE_PROG_DATA_DOWNCAST(tcs, prog_data->stage == MESA_SHADER_TESS_CTRL)
DEFINE_PROG_DATA_DOWNCAST(tes, prog_data->stage == MESA_SHADER_TESS_EVAL)
DEFINE_PROG_DATA_DOWNCAST(gs, prog_data->stage == MESA_SHADER_GEOMETRY)
DEFINE_PROG_DATA_DOWNCAST(wm, prog_data->stage == MESA_SHADER_FRAGMENT)
DEFINE_PROG_DATA_DOWNCAST(cs, gl_shader_stage_uses_workgroup(prog_data->stage))
DEFINE_PROG_DATA_DOWNCAST(cs, mesa_shader_stage_uses_workgroup(prog_data->stage))
DEFINE_PROG_DATA_DOWNCAST(bs, brw_shader_stage_is_bindless(prog_data->stage))
DEFINE_PROG_DATA_DOWNCAST(vue, prog_data->stage == MESA_SHADER_VERTEX ||
src/intel/compiler/brw_from_nir.cpp
+4 -4
View File
@@ -3032,7 +3032,7 @@ emit_barrier(nir_to_brw_state &ntb)
brw_shader &s = ntb.s;
/* We are getting the barrier ID from the compute shader header */
assert(gl_shader_stage_uses_workgroup(s.stage));
assert(mesa_shader_stage_uses_workgroup(s.stage));
/* Zero-initialize the payload */
brw_reg payload = hbld.MOV(brw_imm_ud(0u));
@@ -4674,7 +4674,7 @@ set_memory_address(nir_to_brw_state &ntb,
static unsigned
brw_workgroup_size(brw_shader &s)
{
assert(gl_shader_stage_uses_workgroup(s.stage));
assert(mesa_shader_stage_uses_workgroup(s.stage));
assert(!s.nir->info.workgroup_size_variable);
const struct brw_cs_prog_data *cs = brw_cs_prog_data(s.prog_data);
return cs->local_size[0] * cs->local_size[1] * cs->local_size[2];
@@ -4688,7 +4688,7 @@ brw_from_nir_emit_cs_intrinsic(nir_to_brw_state &ntb,
const brw_builder &bld = ntb.bld;
brw_shader &s = ntb.s;
assert(gl_shader_stage_uses_workgroup(s.stage));
assert(mesa_shader_stage_uses_workgroup(s.stage));
struct brw_cs_prog_data *cs_prog_data = brw_cs_prog_data(s.prog_data);
brw_reg dest;
@@ -6119,7 +6119,7 @@ brw_from_nir_emit_intrinsic(nir_to_brw_state &ntb,
break;
if (s.nir->info.shared_size > 0) {
assert(gl_shader_stage_uses_workgroup(s.stage));
assert(mesa_shader_stage_uses_workgroup(s.stage));
} else {
slm_fence = false;
}
src/intel/compiler/brw_nir_lower_cs_intrinsics.c
+1 -1
View File
@@ -326,7 +326,7 @@ brw_nir_lower_cs_intrinsics(nir_shader *nir,
const struct intel_device_info *devinfo,
struct brw_cs_prog_data *prog_data)
{
assert(gl_shader_stage_uses_workgroup(nir->info.stage));
assert(mesa_shader_stage_uses_workgroup(nir->info.stage));
struct lower_intrinsics_state state = {
.nir = nir,
src/intel/compiler/brw_shader.h
+1 -1
View File
@@ -180,7 +180,7 @@ public:
DEFINE_PAYLOAD_ACCESSOR(brw_gs_thread_payload, gs_payload, stage == MESA_SHADER_GEOMETRY);
DEFINE_PAYLOAD_ACCESSOR(brw_fs_thread_payload, fs_payload, stage == MESA_SHADER_FRAGMENT);
DEFINE_PAYLOAD_ACCESSOR(brw_cs_thread_payload, cs_payload,
gl_shader_stage_uses_workgroup(stage));
mesa_shader_stage_uses_workgroup(stage));
DEFINE_PAYLOAD_ACCESSOR(brw_task_mesh_thread_payload, task_mesh_payload,
stage == MESA_SHADER_TASK || stage == MESA_SHADER_MESH);
DEFINE_PAYLOAD_ACCESSOR(brw_bs_thread_payload, bs_payload,
src/intel/compiler/elk/elk_compiler.h
+1 -1
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@@ -1405,7 +1405,7 @@ DEFINE_PROG_DATA_DOWNCAST(tcs, prog_data->stage == MESA_SHADER_TESS_CTRL)
DEFINE_PROG_DATA_DOWNCAST(tes, prog_data->stage == MESA_SHADER_TESS_EVAL)
DEFINE_PROG_DATA_DOWNCAST(gs, prog_data->stage == MESA_SHADER_GEOMETRY)
DEFINE_PROG_DATA_DOWNCAST(wm, prog_data->stage == MESA_SHADER_FRAGMENT)
DEFINE_PROG_DATA_DOWNCAST(cs, gl_shader_stage_uses_workgroup(prog_data->stage))
DEFINE_PROG_DATA_DOWNCAST(cs, mesa_shader_stage_uses_workgroup(prog_data->stage))
DEFINE_PROG_DATA_DOWNCAST(vue, prog_data->stage == MESA_SHADER_VERTEX ||
prog_data->stage == MESA_SHADER_TESS_CTRL ||
src/intel/compiler/elk/elk_fs.cpp
+1 -1
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@@ -7204,7 +7204,7 @@ elk_fs_test_dispatch_packing(const fs_builder &bld)
unsigned
elk_fs_visitor::workgroup_size() const
{
assert(gl_shader_stage_uses_workgroup(stage));
assert(mesa_shader_stage_uses_workgroup(stage));
const struct elk_cs_prog_data *cs = elk_cs_prog_data(prog_data);
return cs->local_size[0] * cs->local_size[1] * cs->local_size[2];
}
src/intel/compiler/elk/elk_fs.h
+1 -1
View File
@@ -382,7 +382,7 @@ public:
};
elk_cs_thread_payload &cs_payload() {
assert(gl_shader_stage_uses_workgroup(stage));
assert(mesa_shader_stage_uses_workgroup(stage));
return *static_cast<elk_cs_thread_payload *>(this->payload_);
}
src/intel/compiler/elk/elk_fs_nir.cpp
+3 -3
View File
@@ -2663,7 +2663,7 @@ emit_barrier(nir_to_elk_state &ntb)
elk_fs_visitor &s = ntb.s;
/* We are getting the barrier ID from the compute shader header */
assert(gl_shader_stage_uses_workgroup(s.stage));
assert(mesa_shader_stage_uses_workgroup(s.stage));
elk_fs_reg payload = elk_fs_reg(VGRF, s.alloc.allocate(1), ELK_REGISTER_TYPE_UD);
@@ -3973,7 +3973,7 @@ fs_nir_emit_cs_intrinsic(nir_to_elk_state &ntb,
const fs_builder &bld = ntb.bld;
elk_fs_visitor &s = ntb.s;
assert(gl_shader_stage_uses_workgroup(s.stage));
assert(mesa_shader_stage_uses_workgroup(s.stage));
struct elk_cs_prog_data *cs_prog_data = elk_cs_prog_data(s.prog_data);
elk_fs_reg dest;
@@ -4821,7 +4821,7 @@ fs_nir_emit_intrinsic(nir_to_elk_state &ntb,
break;
if (s.nir->info.shared_size > 0) {
assert(gl_shader_stage_uses_workgroup(s.stage));
assert(mesa_shader_stage_uses_workgroup(s.stage));
} else {
slm_fence = false;
}
src/intel/compiler/elk/elk_nir.c
+1 -1
View File
@@ -1714,7 +1714,7 @@ get_subgroup_size(const struct shader_info *info, unsigned max_subgroup_size)
case SUBGROUP_SIZE_REQUIRE_8:
case SUBGROUP_SIZE_REQUIRE_16:
case SUBGROUP_SIZE_REQUIRE_32:
assert(gl_shader_stage_uses_workgroup(info->stage) ||
assert(mesa_shader_stage_uses_workgroup(info->stage) ||
(info->stage >= MESA_SHADER_RAYGEN && info->stage <= MESA_SHADER_CALLABLE));
/* These enum values are expressly chosen to be equal to the subgroup
* size that they require.
src/intel/compiler/elk/elk_nir_lower_cs_intrinsics.c
+1 -1
View File
@@ -297,7 +297,7 @@ elk_nir_lower_cs_intrinsics(nir_shader *nir,
const struct intel_device_info *devinfo,
struct elk_cs_prog_data *prog_data)
{
assert(gl_shader_stage_uses_workgroup(nir->info.stage));
assert(mesa_shader_stage_uses_workgroup(nir->info.stage));
struct lower_intrinsics_state state = {
.nir = nir,
src/intel/compiler/elk/elk_simd_selection.cpp
+1 -1
View File
@@ -31,7 +31,7 @@ unsigned
elk_required_dispatch_width(const struct shader_info *info)
{
if ((int)info->subgroup_size >= (int)SUBGROUP_SIZE_REQUIRE_8) {
assert(gl_shader_stage_uses_workgroup(info->stage));
assert(mesa_shader_stage_uses_workgroup(info->stage));
/* These enum values are expressly chosen to be equal to the subgroup
* size that they require.
*/
src/intel/vulkan/anv_pipeline.c
+2 -2
View File
@@ -1136,7 +1136,7 @@ anv_pipeline_lower_nir(struct anv_pipeline *pipeline,
NIR_PASS(_, nir, anv_nir_lower_resource_intel, pdevice,
stage->bind_map.layout_type);
if (gl_shader_stage_uses_workgroup(nir->info.stage)) {
if (mesa_shader_stage_uses_workgroup(nir->info.stage)) {
NIR_PASS(_, nir, nir_lower_vars_to_explicit_types,
nir_var_mem_shared, shared_type_info);
@@ -4489,7 +4489,7 @@ VkResult anv_GetPipelineExecutableStatisticsKHR(
"Number of bytes of workgroup shared memory used by this "
"shader including any padding.");
stat->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
if (gl_shader_stage_uses_workgroup(exe->stage))
if (mesa_shader_stage_uses_workgroup(exe->stage))
stat->value.u64 = prog_data->total_shared;
else
stat->value.u64 = 0;
src/intel/vulkan_hasvk/anv_pipeline.c
+2 -2
View File
@@ -554,7 +554,7 @@ anv_pipeline_lower_nir(struct anv_pipeline *pipeline,
pdevice, stage->key.base.robust_flags,
prog_data, &stage->bind_map, mem_ctx);
if (gl_shader_stage_uses_workgroup(nir->info.stage)) {
if (mesa_shader_stage_uses_workgroup(nir->info.stage)) {
NIR_PASS(_, nir, nir_lower_vars_to_explicit_types,
nir_var_mem_shared, shared_type_info);
@@ -2045,7 +2045,7 @@ VkResult anv_GetPipelineExecutableStatisticsKHR(
stat->value.u64 = prog_data->total_scratch;
}
if (gl_shader_stage_uses_workgroup(exe->stage)) {
if (mesa_shader_stage_uses_workgroup(exe->stage)) {
vk_outarray_append_typed(VkPipelineExecutableStatisticKHR, &out, stat) {
VK_COPY_STR(stat->name, "Workgroup Memory Size");
VK_COPY_STR(stat->description,