From 48080e5bdf2487484305547e1f0a4f2b24dc5446 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Wed, 10 Mar 2021 16:19:32 +1000 Subject: [PATCH] nir: lower 64-bit floats to 32-bit first. Reviewed-by: Jesse Natalie Acked-by: Adam Jackson Reviewed-by: Roland Scheidegger Part-of: --- src/compiler/nir/nir_lower_fp16_conv.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/compiler/nir/nir_lower_fp16_conv.c b/src/compiler/nir/nir_lower_fp16_conv.c index 4ff3cb74d4b..c2808a9ddd9 100644 --- a/src/compiler/nir/nir_lower_fp16_conv.c +++ b/src/compiler/nir/nir_lower_fp16_conv.c @@ -90,6 +90,9 @@ float_to_half_impl(nir_builder *b, nir_ssa_def *src, nir_rounding_mode mode) { nir_ssa_def *f32infinity = nir_imm_int(b, 255 << 23); nir_ssa_def *f16max = nir_imm_int(b, (127 + 16) << 23); + + if (src->bit_size == 64) + src = nir_f2f32(b, src); nir_ssa_def *sign = nir_iand(b, src, nir_imm_int(b, 0x80000000)); nir_ssa_def *one = nir_imm_int(b, 1); @@ -197,7 +200,6 @@ lower_fp16_cast_impl(nir_builder *b, nir_instr *instr, void *data) src = alu->src[0].src.ssa; swizzle = alu->src[0].swizzle; dst = &alu->dest.dest.ssa; - assert(src->bit_size == 32); switch (alu->op) { case nir_op_f2f16: case nir_op_f2f16_rtne: