diff --git a/src/amd/common/ac_cmdbuf.c b/src/amd/common/ac_cmdbuf.c
index a5347085191..942f664d931 100644
--- a/src/amd/common/ac_cmdbuf.c
+++ b/src/amd/common/ac_cmdbuf.c
@@ -1087,3 +1087,52 @@ ac_emit_cp_set_predication(struct ac_cmdbuf *cs, enum amd_gfx_level gfx_level,
    }
    ac_cmdbuf_end();
 }
+
+void
+ac_emit_cp_gfx11_ge_rings(struct ac_cmdbuf *cs, const struct radeon_info *info,
+                         uint64_t attr_ring_va, bool enable_gfx12_partial_hiz_wa)
+{
+   assert(info->gfx_level >= GFX11);
+   assert((attr_ring_va >> 32) == info->address32_hi);
+
+   ac_cmdbuf_begin(cs);
+
+   ac_cmdbuf_set_uconfig_reg_seq(R_031110_SPI_GS_THROTTLE_CNTL1, 4);
+   ac_cmdbuf_emit(0x12355123);
+   ac_cmdbuf_emit(0x1544D);
+   ac_cmdbuf_emit(attr_ring_va >> 16);
+   ac_cmdbuf_emit(S_03111C_MEM_SIZE((info->attribute_ring_size_per_se >> 16) - 1) |
+                  S_03111C_BIG_PAGE(info->discardable_allows_big_page) |
+                  S_03111C_L1_POLICY(1));
+
+   if (info->gfx_level >= GFX12) {
+      const uint64_t pos_va = attr_ring_va + info->pos_ring_offset;
+      const uint64_t prim_va = attr_ring_va + info->prim_ring_offset;
+
+      /* When one of these 4 registers is updated, all 4 must be updated. */
+      ac_cmdbuf_set_uconfig_reg_seq(R_0309A0_GE_POS_RING_BASE, 4);
+      ac_cmdbuf_emit(pos_va >> 16);
+      ac_cmdbuf_emit(S_0309A4_MEM_SIZE(info->pos_ring_size_per_se >> 5));
+      ac_cmdbuf_emit(prim_va >> 16);
+      ac_cmdbuf_emit(S_0309AC_MEM_SIZE(info->prim_ring_size_per_se >> 5) |
+                     S_0309AC_SCOPE(gfx12_scope_device) |
+                     S_0309AC_PAF_TEMPORAL(gfx12_store_high_temporal_stay_dirty) |
+                     S_0309AC_PAB_TEMPORAL(gfx12_load_last_use_discard) |
+                     S_0309AC_SPEC_DATA_READ(gfx12_spec_read_auto) |
+                     S_0309AC_FORCE_SE_SCOPE(1) |
+                     S_0309AC_PAB_NOFILL(1));
+
+      if (info->gfx_level == GFX12 && info->pfp_fw_version >= 2680) {
+         /* Mitigate the HiZ GPU hang by increasing a timeout when
+          * BOTTOM_OF_PIPE_TS is used as the workaround. This must be emitted
+          * when the gfx queue is idle.
+          */
+         const uint32_t timeout = enable_gfx12_partial_hiz_wa ? 0xfff : 0;
+
+         ac_cmdbuf_emit(PKT3(PKT3_UPDATE_DB_SUMMARIZER_TIMEOUT, 0, 0));
+         ac_cmdbuf_emit(S_EF1_SUMM_CNTL_EVICT_TIMEOUT(timeout));
+      }
+   }
+
+   ac_cmdbuf_end();
+}
diff --git a/src/amd/common/ac_cmdbuf.h b/src/amd/common/ac_cmdbuf.h
index 9ac058a9d76..7866ab58380 100644
--- a/src/amd/common/ac_cmdbuf.h
+++ b/src/amd/common/ac_cmdbuf.h
@@ -76,6 +76,11 @@ struct ac_cmdbuf {
 
 #define ac_cmdbuf_set_config_reg(reg, value) __ac_cmdbuf_set_reg(reg, 0, value, SI_CONFIG, PKT3_SET_CONFIG_REG)
 
+/* Packet building helpers for UCONFIG registers. */
+#define ac_cmdbuf_set_uconfig_reg_seq(reg, num) __ac_cmdbuf_set_reg_seq(reg, num, 0, CIK_UCONFIG, PKT3_SET_UCONFIG_REG, 0)
+
+#define ac_cmdbuf_set_uconfig_reg(reg, value) __ac_cmdbuf_set_reg(reg, 0, value, CIK_UCONFIG, PKT3_SET_UCONFIG_REG)
+
 struct ac_preamble_state {
    uint64_t border_color_va;
 
@@ -138,6 +143,10 @@ void
 ac_emit_cp_set_predication(struct ac_cmdbuf *cs, enum amd_gfx_level gfx_level,
                            uint64_t va, uint32_t op);
 
+void
+ac_emit_cp_gfx11_ge_rings(struct ac_cmdbuf *cs, const struct radeon_info *info,
+                          uint64_t attr_ring_va, bool enable_gfx12_partial_hiz_wa);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/src/amd/vulkan/radv_queue.c b/src/amd/vulkan/radv_queue.c
index 1b52bae81cf..e0ea464278d 100644
--- a/src/amd/vulkan/radv_queue.c
+++ b/src/amd/vulkan/radv_queue.c
@@ -636,7 +636,6 @@ radv_emit_ge_rings(struct radv_device *device, struct radv_cmd_stream *cs, struc
       return;
 
    va = radv_buffer_get_va(ge_rings_bo);
-   assert((va >> 32) == pdev->info.address32_hi);
 
    radv_cs_add_buffer(device->ws, cs->b, ge_rings_bo);
 
@@ -648,43 +647,7 @@ radv_emit_ge_rings(struct radv_device *device, struct radv_cmd_stream *cs, struc
    /* Wait for the PWS counter. */
    ac_emit_cp_acquire_mem_pws(cs->b, pdev->info.gfx_level, AMD_IP_GFX, V_028A90_BOTTOM_OF_PIPE_TS, V_580_CP_ME, 0, 0);
 
-   radeon_begin(cs);
-
-   /* The PS will read inputs from this address. */
-   radeon_set_uconfig_reg_seq(R_031110_SPI_GS_THROTTLE_CNTL1, 4);
-   radeon_emit(0x12355123); /* SPI_GS_THROTTLE_CNTL1 */
-   radeon_emit(0x1544D);    /* SPI_GS_THROTTLE_CNTL2 */
-   radeon_emit(va >> 16);   /* SPI_ATTRIBUTE_RING_BASE */
-   radeon_emit(S_03111C_MEM_SIZE((pdev->info.attribute_ring_size_per_se >> 16) - 1) |
-               S_03111C_BIG_PAGE(pdev->info.discardable_allows_big_page) |
-               S_03111C_L1_POLICY(1)); /* SPI_ATTRIBUTE_RING_SIZE */
-
-   if (pdev->info.gfx_level >= GFX12) {
-      const uint64_t pos_address = va + pdev->info.pos_ring_offset;
-      const uint64_t prim_address = va + pdev->info.prim_ring_offset;
-
-      /* When one of these 4 registers is updated, all 4 must be updated. */
-      radeon_set_uconfig_reg_seq(R_0309A0_GE_POS_RING_BASE, 4);
-      radeon_emit(pos_address >> 16);                                       /* R_0309A0_GE_POS_RING_BASE */
-      radeon_emit(S_0309A4_MEM_SIZE(pdev->info.pos_ring_size_per_se >> 5)); /* R_0309A4_GE_POS_RING_SIZE */
-      radeon_emit(prim_address >> 16);                                      /* R_0309A8_GE_PRIM_RING_BASE */
-      radeon_emit(S_0309AC_MEM_SIZE(pdev->info.prim_ring_size_per_se >> 5) | S_0309AC_SCOPE(gfx12_scope_device) |
-                  S_0309AC_PAF_TEMPORAL(gfx12_store_high_temporal_stay_dirty) |
-                  S_0309AC_PAB_TEMPORAL(gfx12_load_last_use_discard) | S_0309AC_SPEC_DATA_READ(gfx12_spec_read_auto) |
-                  S_0309AC_FORCE_SE_SCOPE(1) | S_0309AC_PAB_NOFILL(1)); /* R_0309AC_GE_PRIM_RING_SIZE */
-
-      if (pdev->info.gfx_level == GFX12 && pdev->info.pfp_fw_version >= 2680) {
-         /* Mitigate the HiZ GPU hang by increasing a timeout when BOTTOM_OF_PIPE_TS is used as the
-          * workaround. This must be emitted when the gfx queue is idle.
-          */
-         const uint32_t timeout = pdev->gfx12_hiz_wa == RADV_GFX12_HIZ_WA_PARTIAL ? 0xfff : 0;
-
-         radeon_emit(PKT3(PKT3_UPDATE_DB_SUMMARIZER_TIMEOUT, 0, 0));
-         radeon_emit(S_EF1_SUMM_CNTL_EVICT_TIMEOUT(timeout));
-      }
-   }
-
-   radeon_end();
+   ac_emit_cp_gfx11_ge_rings(cs->b, &pdev->info, va, pdev->gfx12_hiz_wa == RADV_GFX12_HIZ_WA_PARTIAL);
 }
 
 static void
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.cpp b/src/gallium/drivers/radeonsi/si_state_shaders.cpp
index ba6d6f502c2..b18c4c14c9f 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.cpp
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.cpp
@@ -5036,46 +5036,9 @@ static void si_emit_spi_ge_ring_state(struct si_context *sctx, unsigned index)
       uint64_t attr_address = sctx->ws->cs_is_secure(&sctx->gfx_cs) ?
          sscreen->attribute_pos_prim_ring_tmz->gpu_address :
          sscreen->attribute_pos_prim_ring->gpu_address;
-      assert((attr_address >> 32) == sscreen->info.address32_hi);
 
-      radeon_begin(&sctx->gfx_cs);
-      radeon_set_uconfig_reg_seq(R_031110_SPI_GS_THROTTLE_CNTL1, 4);
-      radeon_emit(0x12355123);      /* SPI_GS_THROTTLE_CNTL1 */
-      radeon_emit(0x1544D);         /* SPI_GS_THROTTLE_CNTL2 */
-      radeon_emit(attr_address >> 16); /* SPI_ATTRIBUTE_RING_BASE */
-      radeon_emit(S_03111C_MEM_SIZE((sscreen->info.attribute_ring_size_per_se >> 16) - 1) |
-                  S_03111C_BIG_PAGE(sscreen->info.discardable_allows_big_page) |
-                  S_03111C_L1_POLICY(1)); /* SPI_ATTRIBUTE_RING_SIZE */
-
-      if (sctx->gfx_level >= GFX12) {
-         uint64_t pos_address = attr_address + sscreen->info.pos_ring_offset;
-         uint64_t prim_address = attr_address + sscreen->info.prim_ring_offset;
-
-         /* When one of these 4 registers is updated, all 4 must be updated. */
-         radeon_set_uconfig_reg_seq(R_0309A0_GE_POS_RING_BASE, 4);
-         radeon_emit(pos_address >> 16);              /* R_0309A0_GE_POS_RING_BASE */
-         radeon_emit(S_0309A4_MEM_SIZE(sscreen->info.pos_ring_size_per_se >> 5)); /* R_0309A4_GE_POS_RING_SIZE */
-         radeon_emit(prim_address >> 16);             /* R_0309A8_GE_PRIM_RING_BASE */
-         radeon_emit(S_0309AC_MEM_SIZE(sscreen->info.prim_ring_size_per_se >> 5) |
-                     S_0309AC_SCOPE(gfx12_scope_device) |
-                     S_0309AC_PAF_TEMPORAL(gfx12_store_high_temporal_stay_dirty) |
-                     S_0309AC_PAB_TEMPORAL(gfx12_load_last_use_discard) |
-                     S_0309AC_SPEC_DATA_READ(gfx12_spec_read_auto) |
-                     S_0309AC_FORCE_SE_SCOPE(1) |
-                     S_0309AC_PAB_NOFILL(1));         /* R_0309AC_GE_PRIM_RING_SIZE */
-
-         if (sctx->gfx_level == GFX12 && sscreen->info.pfp_fw_version >= 2680) {
-            /* Mitigate the HiZ GPU hang by increasing a timeout when
-             * BOTTOM_OF_PIPE_TS is used as the workaround. This must be
-             * emitted when the gfx queue is idle.
-             */
-            const uint32_t timeout = sscreen->options.alt_hiz_logic ? 0xfff : 0;
-
-            radeon_emit(PKT3(PKT3_UPDATE_DB_SUMMARIZER_TIMEOUT, 0, 0));
-            radeon_emit(S_EF1_SUMM_CNTL_EVICT_TIMEOUT(timeout));
-         }
-      }
-      radeon_end();
+      ac_emit_cp_gfx11_ge_rings(&sctx->gfx_cs.current, &sscreen->info,
+                                attr_address, sscreen->options.alt_hiz_logic);
    }
 }