diff --git a/src/gallium/include/winsys/radeon_winsys.h b/src/gallium/include/winsys/radeon_winsys.h
index 9c26d8fc1ba..db431d5b5b0 100644
--- a/src/gallium/include/winsys/radeon_winsys.h
+++ b/src/gallium/include/winsys/radeon_winsys.h
@@ -45,6 +45,7 @@ enum radeon_bo_domain
   RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT,
   RADEON_DOMAIN_GDS = 8,
   RADEON_DOMAIN_OA = 16,
+  RADEON_DOMAIN_DOORBELL = 32,
 };
 
 enum radeon_bo_flag
@@ -891,6 +892,10 @@ static void radeon_canonicalize_bo_flags(enum radeon_bo_domain *_domain,
       flags |= RADEON_FLAG_NO_SUBALLOC | RADEON_FLAG_NO_CPU_ACCESS;
       flags &= ~RADEON_FLAG_SPARSE;
       break;
+   case RADEON_DOMAIN_DOORBELL:
+      flags |= RADEON_FLAG_NO_SUBALLOC;
+      flags &= ~RADEON_FLAG_SPARSE;
+      break;
    }
 
    /* Sparse buffers must have NO_CPU_ACCESS set. */
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
index ac304232361..b894813b8a3 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
@@ -484,7 +484,8 @@ static struct amdgpu_winsys_bo *amdgpu_create_bo(struct amdgpu_winsys *aws,
    /* VRAM or GTT must be specified, but not both at the same time. */
    assert(util_bitcount(initial_domain & (RADEON_DOMAIN_VRAM_GTT |
                                           RADEON_DOMAIN_GDS |
-                                          RADEON_DOMAIN_OA)) == 1);
+                                          RADEON_DOMAIN_OA |
+                                          RADEON_DOMAIN_DOORBELL)) == 1);
 
    alignment = amdgpu_get_optimal_alignment(aws, size, alignment);
 
@@ -532,6 +533,8 @@ static struct amdgpu_winsys_bo *amdgpu_create_bo(struct amdgpu_winsys *aws,
       request.preferred_heap |= AMDGPU_GEM_DOMAIN_GDS;
    if (initial_domain & RADEON_DOMAIN_OA)
       request.preferred_heap |= AMDGPU_GEM_DOMAIN_OA;
+   if (initial_domain & RADEON_DOMAIN_DOORBELL)
+      request.preferred_heap |= AMDGPU_GEM_DOMAIN_DOORBELL;
 
    if (flags & RADEON_FLAG_NO_CPU_ACCESS)
       request.flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
@@ -1435,8 +1438,9 @@ no_slab:
       alignment = align(alignment, aws->info.gart_page_size);
    }
 
-   bool use_reusable_pool = flags & RADEON_FLAG_NO_INTERPROCESS_SHARING &&
-                            !(flags & RADEON_FLAG_DISCARDABLE);
+   bool use_reusable_pool = !(domain & RADEON_DOMAIN_DOORBELL) &&
+      (flags & RADEON_FLAG_NO_INTERPROCESS_SHARING) &&
+      !(flags & RADEON_FLAG_DISCARDABLE);
 
    if (use_reusable_pool) {
        /* RADEON_FLAG_NO_SUBALLOC is irrelevant for the cache. */