v3d: add new flag dirty TMU cache at v3d_compiler

That we set for any TMU write on spills and general tmu. It is then
used as part of v3d_emit_gl_shader_state later.

v2: add a new flag instead at v3d_compiler instead of dirty the flag
    at v3dx if there is any spill (change suggested by Eric, added by
    Alejandro)

v3: set this for anything that is not a load and do it also in
    v3d40_vir_emit_image_load_store (Eric)

Reviewed-by: Eric Anholt <eric@anholt.net>

src/broadcom/compiler/nir_to_vir.c

@@ -208,6 +208,9 @@ ntq_emit_tmu_general(struct v3d_compile *c, nir_intrinsic_instr *instr,
                         instr->intrinsic == nir_intrinsic_load_scratch ||
                         instr->intrinsic == nir_intrinsic_load_shared);
 
+        if (!is_load)
+                c->tmu_dirty_rcl = true;
+
         bool has_index = !is_shared_or_scratch;
 
         int offset_src;

src/broadcom/compiler/v3d40_tex.c

@@ -410,4 +410,7 @@ v3d40_vir_emit_image_load_store(struct v3d_compile *c,
 
         if (nir_intrinsic_dest_components(instr) == 0)
                 vir_TMUWT(c);
+
+        if (instr->intrinsic != nir_intrinsic_image_deref_load)
+                c->tmu_dirty_rcl = true;
 }

src/broadcom/compiler/v3d_compiler.h

@@ -639,6 +639,8 @@ struct v3d_compile {
         bool lock_scoreboard_on_first_thrsw;
 
         bool failed;
+
+        bool tmu_dirty_rcl;
 };
 
 struct v3d_uniform_list {
@@ -658,6 +660,8 @@ struct v3d_prog_data {
          * after-final-THRSW state.
          */
         bool single_seg;
+
+        bool tmu_dirty_rcl;
 };
 
 struct v3d_vs_prog_data {

src/broadcom/compiler/vir.c

@@ -710,6 +710,7 @@ v3d_set_prog_data(struct v3d_compile *c,
         prog_data->threads = c->threads;
         prog_data->single_seg = !c->last_thrsw;
         prog_data->spill_size = c->spill_size;
+        prog_data->tmu_dirty_rcl = c->tmu_dirty_rcl;
 
         v3d_set_prog_data_uniforms(c, prog_data);
 

src/broadcom/compiler/vir_register_allocate.c

@@ -270,6 +270,7 @@ v3d_spill_reg(struct v3d_compile *c, int spill_temp)
                                 vir_emit_thrsw(c);
                                 vir_TMUWT(c);
                                 c->spills++;
+                                c->tmu_dirty_rcl = true;
                         }
                 }