freedreno/a6xx: Consolidate more of dword 0 building in fd6_draw_vbo
There's already a bit of duplicated logic here and tessellation will add more. Build up dword 0 in fd6_draw_vbo() and drop the a4xx in the process. Reviewed-by: Rob Clark <robdclark@gmail.com> Reviewed-by: Eric Anholt <eric@anholt.net>
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committed by
Rob Clark
parent
cae6b4d741
commit
4552162e2d
@@ -40,12 +40,9 @@
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#include "fd6_format.h"
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#include "fd6_zsa.h"
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/* some bits in common w/ a4xx: */
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#include "a4xx/fd4_draw.h"
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static void
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draw_emit_indirect(struct fd_batch *batch, struct fd_ringbuffer *ring,
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enum pc_di_primtype primtype,
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uint32_t draw0,
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const struct pipe_draw_info *info,
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unsigned index_offset)
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{
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@@ -56,9 +53,7 @@ draw_emit_indirect(struct fd_batch *batch, struct fd_ringbuffer *ring,
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unsigned max_indicies = idx->width0 / info->index_size;
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OUT_PKT7(ring, CP_DRAW_INDX_INDIRECT, 6);
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OUT_RINGP(ring, DRAW4(primtype, DI_SRC_SEL_DMA,
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fd4_size2indextype(info->index_size), 0),
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&batch->draw_patches);
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OUT_RINGP(ring, draw0, &batch->draw_patches);
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OUT_RELOC(ring, fd_resource(idx)->bo,
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index_offset, 0, 0);
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// XXX: Check A5xx vs A6xx
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@@ -66,15 +61,14 @@ draw_emit_indirect(struct fd_batch *batch, struct fd_ringbuffer *ring,
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OUT_RELOC(ring, ind->bo, info->indirect->offset, 0, 0);
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} else {
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OUT_PKT7(ring, CP_DRAW_INDIRECT, 3);
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OUT_RINGP(ring, DRAW4(primtype, DI_SRC_SEL_AUTO_INDEX, 0, 0),
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&batch->draw_patches);
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OUT_RINGP(ring, draw0, &batch->draw_patches);
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OUT_RELOC(ring, ind->bo, info->indirect->offset, 0, 0);
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}
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}
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static void
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draw_emit(struct fd_batch *batch, struct fd_ringbuffer *ring,
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enum pc_di_primtype primtype,
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uint32_t draw0,
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const struct pipe_draw_info *info,
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unsigned index_offset)
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{
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@@ -85,31 +79,16 @@ draw_emit(struct fd_batch *batch, struct fd_ringbuffer *ring,
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uint32_t idx_size = info->index_size * info->count;
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uint32_t idx_offset = index_offset + info->start * info->index_size;
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/* leave vis mode blank for now, it will be patched up when
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* we know if we are binning or not
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*/
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uint32_t draw = CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
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CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_DMA) |
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CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(fd4_size2indextype(info->index_size)) |
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0x2000;
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OUT_PKT7(ring, CP_DRAW_INDX_OFFSET, 7);
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OUT_RINGP(ring, draw, &batch->draw_patches);
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OUT_RINGP(ring, draw0, &batch->draw_patches);
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OUT_RING(ring, info->instance_count); /* NumInstances */
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OUT_RING(ring, info->count); /* NumIndices */
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OUT_RING(ring, 0x0); /* XXX */
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OUT_RELOC(ring, fd_resource(idx_buffer)->bo, idx_offset, 0, 0);
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OUT_RING (ring, idx_size);
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} else {
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/* leave vis mode blank for now, it will be patched up when
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* we know if we are binning or not
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*/
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uint32_t draw = CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
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CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_AUTO_INDEX) |
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0x2000;
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OUT_PKT7(ring, CP_DRAW_INDX_OFFSET, 3);
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OUT_RINGP(ring, draw, &batch->draw_patches);
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OUT_RINGP(ring, draw0, &batch->draw_patches);
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OUT_RING(ring, info->instance_count); /* NumInstances */
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OUT_RING(ring, info->count); /* NumIndices */
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}
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@@ -225,12 +204,26 @@ fd6_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info,
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*/
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emit_marker6(ring, 7);
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if (info->indirect) {
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draw_emit_indirect(ctx->batch, ring, primtype,
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info, index_offset);
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/* leave vis mode blank for now, it will be patched up when
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* we know if we are binning or not
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*/
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uint32_t draw0 =
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CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype) |
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0x2000;
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if (info->index_size) {
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draw0 |=
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CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_DMA) |
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CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(fd4_size2indextype(info->index_size));
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} else {
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draw_emit(ctx->batch, ring, primtype,
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info, index_offset);
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draw0 |=
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CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_AUTO_INDEX);
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}
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if (info->indirect) {
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draw_emit_indirect(ctx->batch, ring, draw0, info, index_offset);
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} else {
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draw_emit(ctx->batch, ring, draw0, info, index_offset);
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}
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emit_marker6(ring, 7);
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