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aco: emit packed 16bit instructions

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Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6680>
This commit is contained in:
Daniel Schürmann
2020-08-24 20:36:06 +01:00
committed by Marge Bot
parent 5ad52ac906
commit 454bbf8f23
2 changed files with 66 additions and 4 deletions
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src/amd/compiler/aco_instruction_selection_setup.cpp
+13 -4
View File
@@ -680,7 +680,7 @@ void init_context(isel_context *ctx, nir_shader *shader)
switch(instr->type) {
case nir_instr_type_alu: {
nir_alu_instr *alu_instr = nir_instr_as_alu(instr);
RegType type = RegType::sgpr;
RegType type = nir_dest_is_divergent(alu_instr->dest.dest) ? RegType::vgpr : RegType::sgpr;
switch(alu_instr->op) {
case nir_op_fmul:
case nir_op_fadd:
@@ -745,10 +745,19 @@ void init_context(isel_context *ctx, nir_shader *shader)
case nir_op_b2f16:
case nir_op_b2f32:
case nir_op_mov:
type = nir_dest_is_divergent(alu_instr->dest.dest) ? RegType::vgpr : RegType::sgpr;
break;
case nir_op_bcsel:
type = nir_dest_is_divergent(alu_instr->dest.dest) ? RegType::vgpr : RegType::sgpr;
case nir_op_iadd:
case nir_op_isub:
case nir_op_imul:
case nir_op_imin:
case nir_op_imax:
case nir_op_umin:
case nir_op_umax:
case nir_op_ishl:
case nir_op_ishr:
case nir_op_ushr:
/* packed 16bit instructions have to be VGPR */
type = alu_instr->dest.dest.ssa.num_components == 2 ? RegType::vgpr : type;
FALLTHROUGH;
default:
for (unsigned i = 0; i < nir_op_infos[alu_instr->op].num_inputs; i++) {