From 437bf4fccb8c54a9204ba6d13f389f6bcf86cb99 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Daniel=20Sch=C3=BCrmann?= Date: Thu, 22 Jun 2023 13:24:16 +0200 Subject: [PATCH] amd: move end-of-code marker padding to ACO. This makes it consistent between drivers and compilers. Part-of: --- src/amd/compiler/aco_assembler.cpp | 3 +++ src/amd/compiler/tests/test_assembler.cpp | 4 ++-- src/amd/vulkan/radv_pipeline_cache.c | 2 +- src/amd/vulkan/radv_shader.c | 27 +++-------------------- src/gallium/drivers/radeonsi/si_shader.c | 4 ---- 5 files changed, 9 insertions(+), 31 deletions(-) diff --git a/src/amd/compiler/aco_assembler.cpp b/src/amd/compiler/aco_assembler.cpp index 1fe3a20c158..074ac9d3d54 100644 --- a/src/amd/compiler/aco_assembler.cpp +++ b/src/amd/compiler/aco_assembler.cpp @@ -1297,6 +1297,9 @@ emit_program(Program* program, std::vector& code, std::vectorgfx_level >= GFX10) { /* Pad output with s_code_end so instruction prefetching doesn't cause * page faults */ diff --git a/src/amd/compiler/tests/test_assembler.cpp b/src/amd/compiler/tests/test_assembler.cpp index 7adddb3f673..bb2f733fc98 100644 --- a/src/amd/compiler/tests/test_assembler.cpp +++ b/src/amd/compiler/tests/test_assembler.cpp @@ -336,11 +336,11 @@ BEGIN_TEST(assembler.p_constaddr) dst1.setFixed(PhysReg(2)); //>> s_getpc_b64 s[0:1] ; be801c00 - //! s_add_u32 s0, s0, 24 ; 8000ff00 00000018 + //! s_add_u32 s0, s0, 44 ; 8000ff00 0000002c bld.pseudo(aco_opcode::p_constaddr, dst0, Operand::zero()); //! s_getpc_b64 s[2:3] ; be821c00 - //! s_add_u32 s2, s2, 44 ; 8002ff02 0000002c + //! s_add_u32 s2, s2, 64 ; 8002ff02 00000040 bld.pseudo(aco_opcode::p_constaddr, dst1, Operand::c32(32)); aco::lower_to_hw_instr(program.get()); diff --git a/src/amd/vulkan/radv_pipeline_cache.c b/src/amd/vulkan/radv_pipeline_cache.c index 2831b7d926a..fcbd57ef952 100644 --- a/src/amd/vulkan/radv_pipeline_cache.c +++ b/src/amd/vulkan/radv_pipeline_cache.c @@ -172,7 +172,7 @@ radv_shader_serialize(struct vk_pipeline_cache_object *object, struct blob *blob { struct radv_shader *shader = container_of(object, struct radv_shader, base); size_t stats_size = shader->statistics ? aco_num_statistics * sizeof(uint32_t) : 0; - size_t code_size = shader->code_size - 5 /* DEBUGGER_NUM_MARKERS */ * 4; + size_t code_size = shader->code_size; uint32_t total_size = sizeof(struct radv_shader_binary_legacy) + code_size + stats_size; struct radv_shader_binary_legacy binary = { diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index 47fc64eec3c..a2a3a9b71a2 100644 --- a/src/amd/vulkan/radv_shader.c +++ b/src/amd/vulkan/radv_shader.c @@ -1431,16 +1431,6 @@ radv_destroy_shader_upload_queue(struct radv_device *device) } } -/* For the UMR disassembler. */ -#define DEBUGGER_END_OF_CODE_MARKER 0xbf9f0000 /* invalid instruction */ -#define DEBUGGER_NUM_MARKERS 5 - -static unsigned -radv_get_shader_binary_size(size_t code_size) -{ - return code_size + DEBUGGER_NUM_MARKERS * 4; -} - static bool radv_should_use_wgp_mode(const struct radv_device *device, gl_shader_stage stage, const struct radv_shader_info *info) { @@ -1847,11 +1837,6 @@ radv_shader_binary_upload(struct radv_device *device, const struct radv_shader_b struct radv_shader_binary_legacy *bin = (struct radv_shader_binary_legacy *)binary; memcpy(dest_ptr, bin->data + bin->stats_size, bin->code_size); - /* Add end-of-code markers for the UMR disassembler. */ - uint32_t *ptr32 = (uint32_t *)dest_ptr + bin->code_size / 4; - for (unsigned i = 0; i < DEBUGGER_NUM_MARKERS; i++) - ptr32[i] = DEBUGGER_END_OF_CODE_MARKER; - if (shader->code) { memcpy(shader->code, bin->data + bin->stats_size, bin->code_size); } @@ -2063,7 +2048,7 @@ radv_shader_create_uncached(struct radv_device *device, const struct radv_shader } else { struct radv_shader_binary_legacy *bin = (struct radv_shader_binary_legacy *)binary; - shader->code_size = radv_get_shader_binary_size(bin->code_size); + shader->code_size = bin->code_size; shader->exec_size = bin->exec_size; if (bin->stats_size) { @@ -2131,13 +2116,12 @@ static bool radv_shader_part_binary_upload(struct radv_device *device, const struct radv_shader_part_binary *bin, struct radv_shader_part *shader_part) { - uint32_t code_size = radv_get_shader_binary_size(bin->code_size); struct radv_shader_dma_submission *submission = NULL; void *dest_ptr; if (device->shader_use_invisible_vram) { uint64_t va = radv_buffer_get_va(shader_part->alloc->arena->bo) + shader_part->alloc->offset; - submission = radv_shader_dma_get_submission(device, shader_part->alloc->arena->bo, va, code_size); + submission = radv_shader_dma_get_submission(device, shader_part->alloc->arena->bo, va, bin->code_size); if (!submission) return false; @@ -2147,10 +2131,6 @@ radv_shader_part_binary_upload(struct radv_device *device, const struct radv_sha } memcpy(dest_ptr, bin->data, bin->code_size); - /* Add end-of-code markers for the UMR disassembler. */ - uint32_t *ptr32 = (uint32_t *)dest_ptr + code_size / 4; - for (unsigned i = 0; i < DEBUGGER_NUM_MARKERS; i++) - ptr32[i] = DEBUGGER_END_OF_CODE_MARKER; if (device->shader_use_invisible_vram) { if (!radv_shader_dma_submit(device, submission, &shader_part->upload_seq)) @@ -2163,7 +2143,6 @@ radv_shader_part_binary_upload(struct radv_device *device, const struct radv_sha struct radv_shader_part * radv_shader_part_create(struct radv_device *device, struct radv_shader_part_binary *binary, unsigned wave_size) { - uint32_t code_size = radv_get_shader_binary_size(binary->code_size); struct radv_shader_part *shader_part; shader_part = calloc(1, sizeof(struct radv_shader_part)); @@ -2171,7 +2150,7 @@ radv_shader_part_create(struct radv_device *device, struct radv_shader_part_bina return NULL; shader_part->ref_count = 1; - shader_part->code_size = code_size; + shader_part->code_size = binary->code_size; shader_part->rsrc1 = S_00B848_VGPRS((binary->num_vgprs - 1) / (wave_size == 32 ? 8 : 4)) | S_00B228_SGPRS((binary->num_sgprs - 1) / 8); shader_part->disasm_string = binary->disasm_size ? strdup((const char *)(binary->data + binary->code_size)) : NULL; diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c index 45387d0b359..9f8566213b2 100644 --- a/src/gallium/drivers/radeonsi/si_shader.c +++ b/src/gallium/drivers/radeonsi/si_shader.c @@ -774,10 +774,6 @@ void si_init_shader_args(struct si_shader *shader, struct si_shader_args *args) shader->info.num_input_vgprs -= num_prolog_vgprs; } -/* For the UMR disassembler. */ -#define DEBUGGER_END_OF_CODE_MARKER 0xbf9f0000 /* invalid instruction */ -#define DEBUGGER_NUM_MARKERS 5 - static unsigned get_lds_granularity(struct si_screen *screen, gl_shader_stage stage) { return screen->info.gfx_level >= GFX11 && stage == MESA_SHADER_FRAGMENT ? 1024 :