diff --git a/src/amd/common/nir/ac_nir.h b/src/amd/common/nir/ac_nir.h index 0912021023e..75f17afd2d8 100644 --- a/src/amd/common/nir/ac_nir.h +++ b/src/amd/common/nir/ac_nir.h @@ -132,11 +132,8 @@ ac_nir_lower_tes_inputs_to_mem(nir_shader *shader, ac_nir_map_io_driver_location map); void -ac_nir_compute_tess_wg_info(const struct radeon_info *info, uint64_t outputs_read, uint64_t outputs_written, - uint32_t patch_outputs_read, uint32_t patch_outputs_written, - uint64_t tcs_cross_invocation_outputs_written, - uint64_t outputs_accessed_indirectly, unsigned tcs_vertices_out, - unsigned wave_size, bool tess_uses_primid, bool all_invocations_define_tess_levels, +ac_nir_compute_tess_wg_info(const struct radeon_info *info, const ac_nir_tess_io_info *io_info, + unsigned tcs_vertices_out, unsigned wave_size, bool tess_uses_primid, unsigned num_tcs_input_cp, unsigned lds_input_vertex_size, unsigned num_mem_tcs_outputs, unsigned num_mem_tcs_patch_outputs, unsigned *num_patches_per_wg, unsigned *hw_lds_size); diff --git a/src/amd/common/nir/ac_nir_lower_tess_io_to_mem.c b/src/amd/common/nir/ac_nir_lower_tess_io_to_mem.c index a5f615a662d..ef5c8fd04ed 100644 --- a/src/amd/common/nir/ac_nir_lower_tess_io_to_mem.c +++ b/src/amd/common/nir/ac_nir_lower_tess_io_to_mem.c @@ -1511,23 +1511,16 @@ ac_nir_lower_tes_inputs_to_mem(nir_shader *shader, } void -ac_nir_compute_tess_wg_info(const struct radeon_info *info, uint64_t outputs_read, uint64_t outputs_written, - uint32_t patch_outputs_read, uint32_t patch_outputs_written, - uint64_t tcs_cross_invocation_outputs_written, - uint64_t outputs_accessed_indirectly, unsigned tcs_vertices_out, - unsigned wave_size, bool tess_uses_primid, bool all_invocations_define_tess_levels, +ac_nir_compute_tess_wg_info(const struct radeon_info *info, const ac_nir_tess_io_info *io_info, + unsigned tcs_vertices_out, unsigned wave_size, bool tess_uses_primid, unsigned num_tcs_input_cp, unsigned lds_input_vertex_size, unsigned num_mem_tcs_outputs, unsigned num_mem_tcs_patch_outputs, unsigned *num_patches_per_wg, unsigned *hw_lds_size) { unsigned num_tcs_output_cp = tcs_vertices_out; - unsigned lds_output_vertex_size = - util_bitcount64((((outputs_read & outputs_written) | tcs_cross_invocation_outputs_written | - outputs_accessed_indirectly) & ~TESS_LVL_MASK)) * 16; - unsigned lds_perpatch_output_patch_size = - (util_bitcount64(all_invocations_define_tess_levels ? - 0 : outputs_written & TESS_LVL_MASK) + - util_bitcount(patch_outputs_read & patch_outputs_written)) * 16; + unsigned lds_output_vertex_size = util_bitcount64(io_info->lds_output_mask & ~TESS_LVL_MASK) * 16; + unsigned lds_perpatch_output_patch_size = (util_bitcount64(io_info->lds_output_mask & TESS_LVL_MASK) + + util_bitcount(io_info->lds_patch_output_mask)) * 16; unsigned lds_per_patch = num_tcs_input_cp * lds_input_vertex_size + num_tcs_output_cp * lds_output_vertex_size + diff --git a/src/amd/vulkan/nir/radv_nir_lower_io.c b/src/amd/vulkan/nir/radv_nir_lower_io.c index 76fa42983a4..89de70c6623 100644 --- a/src/amd/vulkan/nir/radv_nir_lower_io.c +++ b/src/amd/vulkan/nir/radv_nir_lower_io.c @@ -9,6 +9,7 @@ #include "ac_nir.h" #include "nir.h" #include "nir_builder.h" +#include "nir_tcs_info.h" #include "radv_device.h" #include "radv_nir.h" #include "radv_physical_device.h" @@ -238,8 +239,11 @@ radv_nir_lower_io_to_mem(struct radv_device *device, struct radv_shader_stage *s } else if (nir->info.stage == MESA_SHADER_TESS_CTRL) { NIR_PASS(_, nir, ac_nir_lower_hs_inputs_to_mem, map_input, pdev->info.gfx_level, info->vs.tcs_in_out_eq, info->vs.tcs_inputs_via_temp, info->vs.tcs_inputs_via_lds); - NIR_PASS(_, nir, ac_nir_lower_hs_outputs_to_mem, &info->tcs.info, map_output, pdev->info.gfx_level, - info->tcs.tes_inputs_read, info->tcs.tes_patch_inputs_read, info->wave_size); + + nir_tcs_info tcs_info; + nir_gather_tcs_info(nir, &tcs_info, nir->info.tess._primitive_mode, nir->info.tess.spacing); + NIR_PASS(_, nir, ac_nir_lower_hs_outputs_to_mem, &tcs_info, map_output, pdev->info.gfx_level, + info->tcs.tes_inputs_read, info->tcs.tes_patch_inputs_read, info->wave_size); return true; } else if (nir->info.stage == MESA_SHADER_TESS_EVAL) { diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 490aa974a00..d0400d31037 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -3616,25 +3616,10 @@ radv_emit_patch_control_points(struct radv_cmd_buffer *cmd_buffer) * is dynamic. */ if (cmd_buffer->state.uses_dynamic_patch_control_points) { - struct shader_info tcs_info; - - /* No other shader_info fields are needed. */ - tcs_info.tess.tcs_vertices_out = tcs->info.tcs.tcs_vertices_out; - /* These are only used to determine the LDS layout for TCS outputs. */ - tcs_info.outputs_read = tcs->info.tcs.tcs_outputs_read; - tcs_info.outputs_written = tcs->info.tcs.tcs_outputs_written; - /* "read" and "written" are OR'd by radv_get_tess_wg_info. */ - tcs_info.outputs_read_indirectly = tcs->info.tcs.tcs_outputs_accessed_indirectly; - tcs_info.outputs_written_indirectly = tcs->info.tcs.tcs_outputs_accessed_indirectly; - tcs_info.patch_outputs_read = tcs->info.tcs.tcs_patch_outputs_read; - tcs_info.patch_outputs_written = tcs->info.tcs.tcs_patch_outputs_written; - tcs_info.tess.tcs_cross_invocation_outputs_written = tcs->info.tcs.tcs_cross_invocation_outputs_written; - - radv_get_tess_wg_info(pdev, &tcs_info, d->vk.ts.patch_control_points, + radv_get_tess_wg_info(pdev, &tcs->info.tcs.io_info, tcs->info.tcs.tcs_vertices_out, d->vk.ts.patch_control_points, /* TODO: This should be only inputs in LDS (not VGPR inputs) to reduce LDS usage */ vs->info.vs.num_linked_outputs, tcs->info.tcs.num_linked_outputs, - tcs->info.tcs.num_linked_patch_outputs, - tcs->info.tcs.info.all_invocations_define_tess_levels, &cmd_buffer->state.tess_num_patches, + tcs->info.tcs.num_linked_patch_outputs, &cmd_buffer->state.tess_num_patches, &cmd_buffer->state.tess_lds_size); } diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index 246826944e6..1327e360747 100644 --- a/src/amd/vulkan/radv_shader.c +++ b/src/amd/vulkan/radv_shader.c @@ -3602,19 +3602,16 @@ radv_get_user_sgpr(const struct radv_shader *shader, int idx) } void -radv_get_tess_wg_info(const struct radv_physical_device *pdev, const struct shader_info *tcs_info, - unsigned tcs_num_input_vertices, unsigned tcs_num_lds_inputs, unsigned tcs_num_vram_outputs, - unsigned tcs_num_vram_patch_outputs, bool all_invocations_define_tess_levels, - unsigned *num_patches_per_wg, unsigned *hw_lds_size) +radv_get_tess_wg_info(const struct radv_physical_device *pdev, const ac_nir_tess_io_info *io_info, + unsigned tcs_vertices_out, unsigned tcs_num_input_vertices, unsigned tcs_num_lds_inputs, + unsigned tcs_num_vram_outputs, unsigned tcs_num_vram_patch_outputs, unsigned *num_patches_per_wg, + unsigned *hw_lds_size) { const uint32_t lds_input_vertex_size = get_tcs_input_vertex_stride(tcs_num_lds_inputs); - ac_nir_compute_tess_wg_info( - &pdev->info, tcs_info->outputs_read, tcs_info->outputs_written, tcs_info->patch_outputs_read, - tcs_info->patch_outputs_written, tcs_info->tess.tcs_cross_invocation_outputs_written, - tcs_info->outputs_read_indirectly | tcs_info->outputs_written_indirectly, tcs_info->tess.tcs_vertices_out, - pdev->ge_wave_size, false, all_invocations_define_tess_levels, tcs_num_input_vertices, lds_input_vertex_size, - tcs_num_vram_outputs, tcs_num_vram_patch_outputs, num_patches_per_wg, hw_lds_size); + ac_nir_compute_tess_wg_info(&pdev->info, io_info, tcs_vertices_out, pdev->ge_wave_size, false, + tcs_num_input_vertices, lds_input_vertex_size, tcs_num_vram_outputs, + tcs_num_vram_patch_outputs, num_patches_per_wg, hw_lds_size); } VkResult diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h index 135577f24e7..0ae3e8216f9 100644 --- a/src/amd/vulkan/radv_shader.h +++ b/src/amd/vulkan/radv_shader.h @@ -672,9 +672,9 @@ get_tcs_input_vertex_stride(unsigned tcs_num_inputs) return stride; } -void radv_get_tess_wg_info(const struct radv_physical_device *pdev, const struct shader_info *tcs_info, - unsigned tcs_num_input_vertices, unsigned tcs_num_lds_inputs, unsigned tcs_num_vram_outputs, - unsigned tcs_num_vram_patch_outputs, bool all_invocations_define_tess_levels, +void radv_get_tess_wg_info(const struct radv_physical_device *pdev, const ac_nir_tess_io_info *io_info, + unsigned tcs_vertices_out, unsigned tcs_num_input_vertices, unsigned tcs_num_lds_inputs, + unsigned tcs_num_vram_outputs, unsigned tcs_num_vram_patch_outputs, unsigned *num_patches_per_wg, unsigned *hw_lds_size); void radv_lower_ngg(struct radv_device *device, struct radv_shader_stage *ngg_stage, diff --git a/src/amd/vulkan/radv_shader_info.c b/src/amd/vulkan/radv_shader_info.c index 173529f4ac4..26d5e3aa2ac 100644 --- a/src/amd/vulkan/radv_shader_info.c +++ b/src/amd/vulkan/radv_shader_info.c @@ -7,6 +7,7 @@ #include "nir/nir.h" #include "nir/nir_xfb_info.h" #include "nir/radv_nir.h" +#include "nir_tcs_info.h" #include "radv_device.h" #include "radv_physical_device.h" #include "radv_pipeline_graphics.h" @@ -631,14 +632,10 @@ gather_shader_info_tcs(struct radv_device *device, const nir_shader *nir, { const struct radv_physical_device *pdev = radv_device_physical(device); - nir_gather_tcs_info(nir, &info->tcs.info, nir->info.tess._primitive_mode, nir->info.tess.spacing); + nir_tcs_info tcs_info; + nir_gather_tcs_info(nir, &tcs_info, nir->info.tess._primitive_mode, nir->info.tess.spacing); + ac_nir_get_tess_io_info(nir, &tcs_info, ~0ull, ~0, &info->tcs.io_info); - info->tcs.tcs_outputs_read = nir->info.outputs_read; - info->tcs.tcs_outputs_written = nir->info.outputs_written; - info->tcs.tcs_outputs_accessed_indirectly = nir->info.outputs_read_indirectly | nir->info.outputs_written_indirectly; - info->tcs.tcs_patch_outputs_read = nir->info.patch_outputs_read; - info->tcs.tcs_patch_outputs_written = nir->info.patch_outputs_written; - info->tcs.tcs_cross_invocation_outputs_written = nir->info.tess.tcs_cross_invocation_outputs_written; info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out; info->tcs.tes_inputs_read = ~0ULL; info->tcs.tes_patch_inputs_read = ~0ULL; @@ -653,12 +650,11 @@ gather_shader_info_tcs(struct radv_device *device, const nir_shader *nir, } if (gfx_state->ts.patch_control_points) { - - radv_get_tess_wg_info(pdev, &nir->info, gfx_state->ts.patch_control_points, + radv_get_tess_wg_info(pdev, &info->tcs.io_info, nir->info.tess.tcs_vertices_out, + gfx_state->ts.patch_control_points, /* TODO: This should be only inputs in LDS (not VGPR inputs) to reduce LDS usage */ info->tcs.num_linked_inputs, info->tcs.num_linked_outputs, - info->tcs.num_linked_patch_outputs, info->tcs.info.all_invocations_define_tess_levels, - &info->num_tess_patches, &info->tcs.num_lds_blocks); + info->tcs.num_linked_patch_outputs, &info->num_tess_patches, &info->tcs.num_lds_blocks); } } diff --git a/src/amd/vulkan/radv_shader_info.h b/src/amd/vulkan/radv_shader_info.h index d94cc850188..b8218b0b3fd 100644 --- a/src/amd/vulkan/radv_shader_info.h +++ b/src/amd/vulkan/radv_shader_info.h @@ -14,10 +14,10 @@ #include #include -#include "nir_tcs_info.h" +#include "util/set.h" +#include "ac_nir.h" #include "radv_constants.h" #include "radv_shader_args.h" -#include "util/set.h" struct radv_device; struct nir_shader; @@ -238,21 +238,15 @@ struct radv_shader_info { unsigned derivative_group : 2; } cs; struct { + ac_nir_tess_io_info io_info; uint64_t tes_inputs_read; uint64_t tes_patch_inputs_read; - uint64_t tcs_outputs_read; - uint64_t tcs_outputs_written; - uint64_t tcs_outputs_accessed_indirectly; - uint32_t tcs_patch_outputs_read; - uint32_t tcs_patch_outputs_written; - uint64_t tcs_cross_invocation_outputs_written; unsigned tcs_vertices_out; uint32_t num_lds_blocks; uint8_t num_linked_inputs; /* Number of reserved per-vertex input slots in LDS. */ uint8_t num_linked_outputs; /* Number of reserved per-vertex output slots in VRAM. */ uint8_t num_linked_patch_outputs; /* Number of reserved per-patch output slots in VRAM. */ bool tes_reads_tess_factors : 1; - nir_tcs_info info; } tcs; struct { enum mesa_prim output_prim; diff --git a/src/gallium/drivers/radeonsi/si_shader_info.c b/src/gallium/drivers/radeonsi/si_shader_info.c index be025f1b98a..10935c2c5a6 100644 --- a/src/gallium/drivers/radeonsi/si_shader_info.c +++ b/src/gallium/drivers/radeonsi/si_shader_info.c @@ -407,13 +407,6 @@ void si_nir_scan_shader(struct si_screen *sscreen, struct nir_shader *nir, info->base.writes_memory = nir->info.writes_memory; info->base.subgroup_size = nir->info.subgroup_size; - info->base.outputs_read = nir->info.outputs_read; - info->base.outputs_written = nir->info.outputs_written; - info->base.patch_outputs_read = nir->info.patch_outputs_read; - info->base.patch_outputs_written = nir->info.patch_outputs_written; - info->base.outputs_read_indirectly = nir->info.outputs_read_indirectly; - info->base.outputs_written_indirectly = nir->info.outputs_written_indirectly; - info->base.num_ubos = nir->info.num_ubos; info->base.num_ssbos = nir->info.num_ssbos; info->base.num_images = nir->info.num_images; @@ -442,8 +435,6 @@ void si_nir_scan_shader(struct si_screen *sscreen, struct nir_shader *nir, info->base.tess.tcs_vertices_out = nir->info.tess.tcs_vertices_out; info->base.tess.ccw = nir->info.tess.ccw; info->base.tess.point_mode = nir->info.tess.point_mode; - info->base.tess.tcs_cross_invocation_outputs_read = nir->info.tess.tcs_cross_invocation_outputs_read; - info->base.tess.tcs_cross_invocation_outputs_written = nir->info.tess.tcs_cross_invocation_outputs_written; break; case MESA_SHADER_GEOMETRY: @@ -508,8 +499,7 @@ void si_nir_scan_shader(struct si_screen *sscreen, struct nir_shader *nir, nir_tcs_info tcs_info; nir_gather_tcs_info(nir, &tcs_info, nir->info.tess._primitive_mode, nir->info.tess.spacing); - - info->tessfactors_are_def_in_all_invocs = tcs_info.all_invocations_define_tess_levels; + ac_nir_get_tess_io_info(nir, &tcs_info, ~0ull, ~0, &info->tess_io_info); } /* tess factors are loaded as input instead of system value */ diff --git a/src/gallium/drivers/radeonsi/si_shader_info.h b/src/gallium/drivers/radeonsi/si_shader_info.h index f961100657a..49058d26b9a 100644 --- a/src/gallium/drivers/radeonsi/si_shader_info.h +++ b/src/gallium/drivers/radeonsi/si_shader_info.h @@ -30,13 +30,6 @@ struct si_shader_info { bool writes_memory:1; enum gl_subgroup_size subgroup_size; - uint64_t outputs_read; - uint64_t outputs_written; - uint32_t patch_outputs_read; - uint32_t patch_outputs_written; - uint64_t outputs_read_indirectly; - uint64_t outputs_written_indirectly; - uint8_t num_ubos; uint8_t num_ssbos; uint8_t num_images; @@ -64,8 +57,6 @@ struct si_shader_info { uint8_t tcs_vertices_out; bool ccw:1; bool point_mode:1; - uint64_t tcs_cross_invocation_outputs_read; - uint64_t tcs_cross_invocation_outputs_written; } tess; struct { @@ -93,6 +84,8 @@ struct si_shader_info { }; } base; + ac_nir_tess_io_info tess_io_info; + uint32_t options; /* bitmask of SI_PROFILE_* */ uint8_t num_inputs; @@ -179,9 +172,6 @@ struct si_shader_info { bool uses_bindless_images; bool has_divergent_loop; - /** Whether all codepaths write tess factors in all invocations. */ - bool tessfactors_are_def_in_all_invocs; - /* A flag to check if vrs2x2 can be enabled to reduce number of * fragment shader invocations if flat shading. */ diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.cpp b/src/gallium/drivers/radeonsi/si_state_shaders.cpp index 1bab3b9e20d..2eb1b2075c0 100644 --- a/src/gallium/drivers/radeonsi/si_state_shaders.cpp +++ b/src/gallium/drivers/radeonsi/si_state_shaders.cpp @@ -4817,15 +4817,9 @@ void si_update_tess_io_layout_state(struct si_context *sctx) unsigned num_patches, lds_size; /* Compute NUM_PATCHES and LDS_SIZE. */ - ac_nir_compute_tess_wg_info(&sctx->screen->info, tcs->info.base.outputs_read, - tcs->info.base.outputs_written, tcs->info.base.patch_outputs_read, - tcs->info.base.patch_outputs_written, - tcs->info.base.tess.tcs_cross_invocation_outputs_written, - tcs->info.base.outputs_read_indirectly | - tcs->info.base.outputs_written_indirectly, + ac_nir_compute_tess_wg_info(&sctx->screen->info, &tcs->info.tess_io_info, tcs->info.base.tess.tcs_vertices_out, ls_current->wave_size, - tess_uses_primid, tcs->info.tessfactors_are_def_in_all_invocs, - num_tcs_input_cp, lds_input_vertex_size, + tess_uses_primid, num_tcs_input_cp, lds_input_vertex_size, num_mem_tcs_outputs, num_mem_tcs_patch_outputs, &num_patches, &lds_size);