From 41619da3977eb1b1cc7299ac045d784cea9980e7 Mon Sep 17 00:00:00 2001 From: Konstantin Seurer Date: Thu, 27 Jun 2024 09:17:18 +0200 Subject: [PATCH] radv: Handle AS access bits like shader storage access bits Acceleration structures are accessed directly from shaders or via PKT3_WRITE_DATA. Reviewed-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/radv_cmd_buffer.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 49c815d472a..2420c8b0914 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -7032,6 +7032,7 @@ radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer, VkPipelineStageFlags2 flush_bits |= RADV_CMD_FLAG_INV_L2; break; case VK_ACCESS_2_SHADER_STORAGE_WRITE_BIT: + case VK_ACCESS_2_ACCELERATION_STRUCTURE_WRITE_BIT_KHR: /* since the STORAGE bit isn't set we know that this is a meta operation. * on the dst flush side we skip CB/DB flushes without the STORAGE bit, so * set it here. */ @@ -7046,7 +7047,6 @@ radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer, VkPipelineStageFlags2 if (!image_is_coherent) flush_bits |= RADV_CMD_FLAG_INV_L2; break; - case VK_ACCESS_2_ACCELERATION_STRUCTURE_WRITE_BIT_KHR: case VK_ACCESS_2_TRANSFORM_FEEDBACK_WRITE_BIT_EXT: case VK_ACCESS_2_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT: if (!image_is_coherent) @@ -7145,6 +7145,7 @@ radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer, VkPipelineStageFlags2 break; case VK_ACCESS_2_SHADER_BINDING_TABLE_READ_BIT_KHR: case VK_ACCESS_2_SHADER_STORAGE_READ_BIT: + case VK_ACCESS_2_ACCELERATION_STRUCTURE_READ_BIT_KHR: /* Unlike LLVM, ACO uses SMEM for SSBOs and we have to * invalidate the scalar cache. */ if (!pdev->use_llvm && !image) @@ -7158,7 +7159,6 @@ radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer, VkPipelineStageFlags2 flush_bits |= RADV_CMD_FLAG_INV_L2; break; case VK_ACCESS_2_COMMAND_PREPROCESS_READ_BIT_NV: - case VK_ACCESS_2_ACCELERATION_STRUCTURE_READ_BIT_KHR: flush_bits |= RADV_CMD_FLAG_INV_VCACHE; if (pdev->info.gfx_level < GFX9) flush_bits |= RADV_CMD_FLAG_INV_L2;