diff --git a/src/amd/common/sid.h b/src/amd/common/sid.h
index 6558e863ac4..b3e6b4b59a0 100644
--- a/src/amd/common/sid.h
+++ b/src/amd/common/sid.h
@@ -389,13 +389,25 @@
 
 #define SDMA_NOP_PAD SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0) /* header-only version */
 
-/* SDMA DCC tilings for GFX12+ */
-#define SDMA_DCC_DATA_FORMAT(x) ((x) & 0x3f)
-#define SDMA_DCC_NUM_TYPE(x)    (((x) & 0x7) << 9)
-#define SDMA_DCC_READ_CM(x)     (((x) & 0x3) << 16) /* 0: bypass DCC, 2: decompress reads if PTE.D */
-#define SDMA_DCC_WRITE_CM(x)    (((x) & 0x3) << 18) /* 0: bypass DCC, 1: write compressed if PTE.D, 2: write uncompressed if PTE.D */
-#define SDMA_DCC_MAX_COM(x)     (((x) & 0x3) << 24)
-#define SDMA_DCC_MAX_UCOM(x)    (((x) & 0x1) << 26) /* 1: max uncompressed block size 256B */
+/* SDMA DCC settings for GFX10+ */
+#define SDMA5_DCC_DATA_FORMAT(x)       ((x) & 0x7f)
+#define SDMA5_DCC_ALPHA_IS_ON_MSB(x)   (((x) & 0x1) << 8)
+#define SDMA5_DCC_NUM_TYPE(x)          (((x) & 0x7) << 9)
+#define SDMA5_DCC_SURF_TYPE(x)         (((x) & 0x3) << 12) /* 0: color, 1: Z, 2: stencil, 3: FMASK */
+#define SDMA5_DCC_LLC_NOALLOC(x)       (((x) & 0x1) << 14) /* don't cache in MALL */
+#define SDMA5_DCC_MAX_COM(x)           (((x) & 0x3) << 24) /* max compressed block size, 0: 64B, 1: 128B, 2: 256B */
+#define SDMA5_DCC_MAX_UCOM(x)          (((x) & 0x3) << 26) /* max uncompressed block size, 0: 64B, 1: 128B, 2: 256B */
+#define SDMA5_DCC_WRITE_COMPRESS(x)    (((x) & 0x1) << 28) /* DCC write compression enabled, dst must be tiled */
+#define SDMA5_DCC_TMZ(x)               (((x) & 0x1) << 29) /* metadata is TMZ */
+#define SDMA5_DCC_PIPE_ALIGNED(x)      (((x) & 0x1) << 31)
+
+/* SDMA DCC settings for GFX12+ */
+#define SDMA7_DCC_DATA_FORMAT(x)       ((x) & 0x3f)
+#define SDMA7_DCC_NUM_TYPE(x)          (((x) & 0x7) << 9)
+#define SDMA7_DCC_READ_CM(x)           (((x) & 0x3) << 16) /* 0: bypass DCC, 2: decompress reads if PTE.D */
+#define SDMA7_DCC_WRITE_CM(x)          (((x) & 0x3) << 18) /* 0: bypass DCC, 1: write compressed if PTE.D, 2: write uncompressed if PTE.D */
+#define SDMA7_DCC_MAX_COM(x)           (((x) & 0x3) << 24)
+#define SDMA7_DCC_MAX_UCOM(x)          (((x) & 0x1) << 26) /* 1: max uncompressed block size 256B */
 
 enum amd_cmp_class_flags
 {
diff --git a/src/gallium/drivers/radeonsi/si_sdma_copy_image.c b/src/gallium/drivers/radeonsi/si_sdma_copy_image.c
index f0b7a5096ba..fd719f59733 100644
--- a/src/gallium/drivers/radeonsi/si_sdma_copy_image.c
+++ b/src/gallium/drivers/radeonsi/si_sdma_copy_image.c
@@ -168,26 +168,29 @@ static bool si_sdma_v4_v5_copy_texture(struct si_context *sctx, struct si_textur
       if (dcc) {
          unsigned data_format = ac_get_cb_format(sctx->gfx_level, tiled->buffer.b.b.format);
          unsigned number_type = ac_get_cb_number_type(tiled->buffer.b.b.format);
-         uint64_t md_address = tiled_address + tiled->surface.meta_offset;
 
          if (is_v7) {
-            radeon_emit(SDMA_DCC_DATA_FORMAT(data_format) |
-                        SDMA_DCC_NUM_TYPE(number_type) |
-                        SDMA_DCC_READ_CM(2) |
-                        SDMA_DCC_WRITE_CM(1) |
-                        SDMA_DCC_MAX_COM(tiled->surface.u.gfx9.color.dcc.max_compressed_block_size) |
-                        SDMA_DCC_MAX_UCOM(1));
+            radeon_emit(SDMA7_DCC_DATA_FORMAT(data_format) |
+                        SDMA7_DCC_NUM_TYPE(number_type) |
+                        SDMA7_DCC_READ_CM(2) |
+                        SDMA7_DCC_WRITE_CM(1) |
+                        SDMA7_DCC_MAX_COM(tiled->surface.u.gfx9.color.dcc.max_compressed_block_size) |
+                        SDMA7_DCC_MAX_UCOM(1));
          } else {
             /* Add metadata */
+            uint64_t md_address = tiled_address + tiled->surface.meta_offset;
+
             radeon_emit((uint32_t)md_address);
             radeon_emit((uint32_t)(md_address >> 32));
-            radeon_emit(data_format |
-                        ac_alpha_is_on_msb(&sctx->screen->info, tiled->buffer.b.b.format) << 8 |
-                        number_type << 9 |
-                        tiled->surface.u.gfx9.color.dcc.max_compressed_block_size << 24 |
-                        V_028C78_MAX_BLOCK_SIZE_256B << 26 |
-                        tmz << 29 |
-                        tiled->surface.u.gfx9.color.dcc.pipe_aligned << 31);
+            radeon_emit(SDMA5_DCC_DATA_FORMAT(data_format) |
+                        SDMA5_DCC_ALPHA_IS_ON_MSB(ac_alpha_is_on_msb(&sctx->screen->info, tiled->buffer.b.b.format)) |
+                        SDMA5_DCC_NUM_TYPE(number_type) |
+                        SDMA5_DCC_SURF_TYPE(0) |
+                        SDMA5_DCC_MAX_COM(tiled->surface.u.gfx9.color.dcc.max_compressed_block_size) |
+                        SDMA5_DCC_MAX_UCOM(V_028C78_MAX_BLOCK_SIZE_256B) |
+                        SDMA5_DCC_WRITE_COMPRESS(tiled == sdst) |
+                        SDMA5_DCC_TMZ(tmz) |
+                        SDMA5_DCC_PIPE_ALIGNED(tiled->surface.u.gfx9.color.dcc.pipe_aligned));
          }
       }
       radeon_end();