From 3f747fcbfc2722b29858f0cc4695e84012f752fa Mon Sep 17 00:00:00 2001 From: Sagar Ghuge Date: Wed, 22 Nov 2023 20:50:47 -0800 Subject: [PATCH] iris: Init aux map state for compute engine MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We need to write the aux map address during the batch initialization for compute engine as well otherwise we would run into gpu hang with compression enabled. Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10194 Signed-off-by: Sagar Ghuge Reviewed-by: Tapani Pälli Reviewed-by: José Roberto de Souza Part-of: --- src/gallium/drivers/iris/iris_state.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index 97121b2adc0..df7c044c78f 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -6153,14 +6153,22 @@ static void init_aux_map_state(struct iris_batch *batch) { struct iris_screen *screen = batch->screen; + const struct intel_device_info *devinfo = screen->devinfo; void *aux_map_ctx = iris_bufmgr_get_aux_map_context(screen->bufmgr); if (!aux_map_ctx) return; uint64_t base_addr = intel_aux_map_get_base(aux_map_ctx); assert(base_addr != 0 && align64(base_addr, 32 * 1024) == base_addr); - iris_load_register_imm64(batch, GENX(GFX_AUX_TABLE_BASE_ADDR_num), - base_addr); + + bool use_compute_reg = batch->name == IRIS_BATCH_COMPUTE && + devinfo->has_compute_engine && + debug_get_bool_option("INTEL_COMPUTE_CLASS", false); + + uint32_t reg = use_compute_reg ? GENX(COMPCS0_AUX_TABLE_BASE_ADDR_num) : + GENX(GFX_AUX_TABLE_BASE_ADDR_num); + + iris_load_register_imm64(batch, reg, base_addr); } #endif