diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c
index 817cfa328f6..22e512a9461 100644
--- a/src/gallium/drivers/iris/iris_state.c
+++ b/src/gallium/drivers/iris/iris_state.c
@@ -1477,6 +1477,51 @@ iris_init_compute_context(struct iris_batch *batch)
    init_aux_map_state(batch);
 #endif
 
+#if GFX_VERx10 >= 125
+   /* Wa_14015782607 - Issue pipe control with HDC_flush and
+    * untyped cache flush set to 1 when CCS has NP state update with
+    * STATE_COMPUTE_MODE.
+    */
+   if (intel_needs_workaround(devinfo, 14015782607))
+      iris_emit_pipe_control_flush(batch, "Wa_14015782607",
+                                   PIPE_CONTROL_CS_STALL |
+                                   PIPE_CONTROL_UNTYPED_DATAPORT_CACHE_FLUSH |
+                                   PIPE_CONTROL_FLUSH_HDC);
+
+   /* Wa_14014427904/22013045878 - We need additional invalidate/flush when
+    * emitting NP state commands with ATS-M in compute mode.
+    */
+   if (intel_device_info_is_atsm(devinfo))
+      iris_emit_pipe_control_flush(batch, "Wa_14014427904/22013045878",
+                                   PIPE_CONTROL_CS_STALL |
+                                   PIPE_CONTROL_STATE_CACHE_INVALIDATE |
+                                   PIPE_CONTROL_CONST_CACHE_INVALIDATE |
+                                   PIPE_CONTROL_UNTYPED_DATAPORT_CACHE_FLUSH |
+                                   PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
+                                   PIPE_CONTROL_INSTRUCTION_INVALIDATE |
+                                   PIPE_CONTROL_FLUSH_HDC);
+
+   iris_emit_cmd(batch, GENX(STATE_COMPUTE_MODE), cm) {
+#if GFX_VER >= 20
+      cm.AsyncComputeThreadLimit = ACTL_Max8;
+      cm.ZPassAsyncComputeThreadLimit = ZPACTL_Max60;
+      cm.ZAsyncThrottlesettings = ZATS_DefertoAsyncComputeThreadLimit;
+      cm.AsyncComputeThreadLimitMask = 0x7;
+      cm.ZPassAsyncComputeThreadLimitMask = 0x7;
+      cm.ZAsyncThrottlesettingsMask = 0x3;
+#else
+      cm.PixelAsyncComputeThreadLimit = PACTL_Max24;
+      cm.ZPassAsyncComputeThreadLimit = ZPACTL_Max60;
+      cm.PixelAsyncComputeThreadLimitMask = 0x7;
+      cm.ZPassAsyncComputeThreadLimitMask = 0x7;
+      if (intel_device_info_is_mtl_or_arl(devinfo)) {
+         cm.ZAsyncThrottlesettings = ZATS_DefertoPixelAsyncComputeThreadLimit;
+         cm.ZAsyncThrottlesettingsMask = 0x3;
+      }
+#endif
+   }
+#endif
+
 #if GFX_VERx10 >= 125
    iris_emit_cmd(batch, GENX(CFE_STATE), cfe) {
       cfe.MaximumNumberofThreads =