From 3df6c19a228f2e7c555c3587aa343c6357c058b7 Mon Sep 17 00:00:00 2001
From: Connor Abbott <cwabbott0@gmail.com>
Date: Thu, 7 Dec 2023 20:59:06 +0100
Subject: [PATCH] virtio/drm: Update header

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26578>
---
 src/virtio/virtio-gpu/drm_hw.h | 17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/src/virtio/virtio-gpu/drm_hw.h b/src/virtio/virtio-gpu/drm_hw.h
index 45a2f4f49e0..33a90842738 100644
--- a/src/virtio/virtio-gpu/drm_hw.h
+++ b/src/virtio/virtio-gpu/drm_hw.h
@@ -6,13 +6,18 @@
 #ifndef DRM_HW_H_
 #define DRM_HW_H_
 
+#ifdef ENABLE_DRM_AMDGPU
+#include <amdgpu.h>
+#endif
+
 struct virgl_renderer_capset_drm {
    uint32_t wire_format_version;
    /* Underlying drm device version: */
    uint32_t version_major;
    uint32_t version_minor;
    uint32_t version_patchlevel;
-#define VIRTGPU_DRM_CONTEXT_MSM   1
+#define VIRTGPU_DRM_CONTEXT_MSM      1
+#define VIRTGPU_DRM_CONTEXT_AMDGPU   2
    uint32_t context_type;
    uint32_t pad;
    union {
@@ -26,7 +31,17 @@ struct virgl_renderer_capset_drm {
          uint64_t gmem_base;
          uint64_t chip_id;
          uint32_t max_freq;
+         uint32_t highest_bank_bit;
       } msm;  /* context_type == VIRTGPU_DRM_CONTEXT_MSM */
+      struct {
+         uint32_t address32_hi;
+         uint32_t __pad;
+#ifdef ENABLE_DRM_AMDGPU
+         struct amdgpu_buffer_size_alignments alignments;
+         struct amdgpu_gpu_info gpu_info;
+#endif
+         char marketing_name[128];
+      } amdgpu;   /* context_type == VIRTGPU_DRM_CONTEXT_AMDGPU */
    } u;
 };