From 3dc9c1a91e347f52e8018beb1d9dda9f17e86851 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Wed, 24 Sep 2025 19:47:22 +0200 Subject: [PATCH] ac/nir/ngg: Remove dead code for 64-bit mesh shader variables We already lower all 64-bit I/O to 32-bit before this pass, and the rest of the code here already asserts that I/O variables must be 32-bit or smaller. Part-of: --- src/amd/common/nir/ac_nir_lower_ngg_mesh.c | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/src/amd/common/nir/ac_nir_lower_ngg_mesh.c b/src/amd/common/nir/ac_nir_lower_ngg_mesh.c index c166a7a8106..96f71d4b7b1 100644 --- a/src/amd/common/nir/ac_nir_lower_ngg_mesh.c +++ b/src/amd/common/nir/ac_nir_lower_ngg_mesh.c @@ -332,15 +332,7 @@ ms_store_arrayed_output(nir_builder *b, .access = ACCESS_COHERENT | ACCESS_IS_SWIZZLED_AMD, .align_mul = 16, .align_offset = const_off % 16u); } else if (out_mode == ms_out_mode_var) { - unsigned write_mask_32 = write_mask; - if (store_val->bit_size > 32) { - /* Split 64-bit store values to 32-bit components. */ - store_val = nir_bitcast_vector(b, store_val, 32); - /* Widen the write mask so it is in 32-bit components. */ - write_mask_32 = util_widen_mask(write_mask, store_val->bit_size / 32); - } - - u_foreach_bit(comp, write_mask_32) { + u_foreach_bit(comp, write_mask) { unsigned idx = io_sem.location * 4 + comp + component_offset; nir_def *val = nir_channel(b, store_val, comp); nir_def *v = nir_load_var(b, s->out_variables[idx]);