diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp
index f72dda532f7..cdb2bc4eebe 100644
--- a/src/amd/compiler/aco_instruction_selection.cpp
+++ b/src/amd/compiler/aco_instruction_selection.cpp
@@ -4123,8 +4123,9 @@ bool store_output_to_temps(isel_context *ctx, nir_intrinsic_instr *instr)
    unsigned write_mask = nir_intrinsic_write_mask(instr);
    unsigned component = nir_intrinsic_component(instr);
    unsigned idx = nir_intrinsic_base(instr) * 4u + component;
+   nir_src offset = *nir_get_io_offset_src(instr);
 
-   if (!nir_src_is_const(instr->src[1]) || nir_src_as_uint(instr->src[1]))
+   if (!nir_src_is_const(offset) || nir_src_as_uint(offset))
       return false;
 
    Temp src = get_ssa_temp(ctx, instr->src[0].ssa);
@@ -4507,10 +4508,12 @@ void visit_load_input(isel_context *ctx, nir_intrinsic_instr *instr)
 {
    Builder bld(ctx->program, ctx->block);
    Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
+   nir_src offset = *nir_get_io_offset_src(instr);
+
    if (ctx->shader->info.stage == MESA_SHADER_VERTEX) {
 
-      if (!nir_src_is_const(instr->src[0]) || nir_src_as_uint(instr->src[0]))
-         isel_err(instr->src[0].ssa->parent_instr, "Unimplemented non-zero nir_intrinsic_load_input offset");
+      if (!nir_src_is_const(offset) || nir_src_as_uint(offset))
+         isel_err(offset.ssa->parent_instr, "Unimplemented non-zero nir_intrinsic_load_input offset");
 
       Temp vertex_buffers = convert_pointer_to_64_bit(ctx, get_arg(ctx, ctx->args->vertex_buffers));
 
@@ -4716,9 +4719,8 @@ void visit_load_input(isel_context *ctx, nir_intrinsic_instr *instr)
             ctx->allocated_vec.emplace(dst.id(), elems);
       }
    } else if (ctx->shader->info.stage == MESA_SHADER_FRAGMENT) {
-      nir_src *off_src = nir_get_io_offset_src(instr);
-      if (!nir_src_is_const(*off_src) || nir_src_as_uint(*off_src))
-         isel_err(off_src->ssa->parent_instr, "Unimplemented non-zero nir_intrinsic_load_input offset");
+      if (!nir_src_is_const(offset) || nir_src_as_uint(offset))
+         isel_err(offset.ssa->parent_instr, "Unimplemented non-zero nir_intrinsic_load_input offset");
 
       Temp prim_mask = get_arg(ctx, ctx->args->ac.prim_mask);