From 3beb088490858e679f1755130f50e9ee5acce3c1 Mon Sep 17 00:00:00 2001 From: Lionel Landwerlin Date: Mon, 21 Feb 2022 14:15:14 +0200 Subject: [PATCH] intel/mi_builder: allow half GP registers for dereferencing Some of the GRL metakernels will generate 64bit value in a register, then use only half of that as the last operation on that value. v2: Add comment (Caio) Signed-off-by: Lionel Landwerlin Reviewed-by: Caio Oliveira Part-of: --- src/intel/common/mi_builder.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/intel/common/mi_builder.h b/src/intel/common/mi_builder.h index b9a245c7d7c..43b54e8f122 100644 --- a/src/intel/common/mi_builder.h +++ b/src/intel/common/mi_builder.h @@ -208,7 +208,11 @@ static inline uint32_t _mi_value_as_gpr(struct mi_value val) { assert(mi_value_is_gpr(val)); - assert(val.reg % 8 == 0); + /* Some of the GRL metakernels will generate 64bit value in a GP register, + * then use only half of that as the last operation on that value. So allow + * unref on part of a GP register. + */ + assert(val.reg % 4 == 0); return (val.reg - _MI_BUILDER_GPR_BASE) / 8; }