From 3bd8a2568d5fa65d42f1f3d47ec3c05e63a374a9 Mon Sep 17 00:00:00 2001 From: Faith Ekstrand Date: Fri, 19 Apr 2024 11:57:14 -0500 Subject: [PATCH] nouveau: Import the hwref headers from Nvidia OGK Part-of: --- .../nvidia/hwref/ampere/ga100/dev_fault.h | 480 +++++++++++ .../nvidia/hwref/ampere/ga100/dev_runlist.h | 782 ++++++++++++++++++ .../nvidia/hwref/hopper/gh100/dev_fault.h | 508 ++++++++++++ .../nvidia/hwref/hopper/gh100/dev_mmu.h | 560 +++++++++++++ .../nvidia/hwref/maxwell/gm107/dev_mmu.h | 339 ++++++++ .../nvidia/hwref/pascal/gp100/dev_fault.h | 203 +++++ .../nvidia/hwref/pascal/gp100/dev_fb.h | 71 ++ .../nvidia/hwref/pascal/gp100/dev_mmu.h | 625 ++++++++++++++ .../nvidia/hwref/turing/tu102/dev_fault.h | 400 +++++++++ .../nvidia/hwref/turing/tu102/dev_mmu.h | 649 +++++++++++++++ .../nvidia/hwref/volta/gv100/dev_fault.h | 263 ++++++ .../headers/nvidia/hwref/volta/gv100/dev_fb.h | 103 +++ .../nvidia/hwref/volta/gv100/dev_mmu.h | 661 +++++++++++++++ 13 files changed, 5644 insertions(+) create mode 100644 src/nouveau/headers/nvidia/hwref/ampere/ga100/dev_fault.h create mode 100644 src/nouveau/headers/nvidia/hwref/ampere/ga100/dev_runlist.h create mode 100644 src/nouveau/headers/nvidia/hwref/hopper/gh100/dev_fault.h create mode 100644 src/nouveau/headers/nvidia/hwref/hopper/gh100/dev_mmu.h create mode 100644 src/nouveau/headers/nvidia/hwref/maxwell/gm107/dev_mmu.h create mode 100644 src/nouveau/headers/nvidia/hwref/pascal/gp100/dev_fault.h create mode 100644 src/nouveau/headers/nvidia/hwref/pascal/gp100/dev_fb.h create mode 100644 src/nouveau/headers/nvidia/hwref/pascal/gp100/dev_mmu.h create mode 100644 src/nouveau/headers/nvidia/hwref/turing/tu102/dev_fault.h create mode 100644 src/nouveau/headers/nvidia/hwref/turing/tu102/dev_mmu.h create mode 100644 src/nouveau/headers/nvidia/hwref/volta/gv100/dev_fault.h create mode 100644 src/nouveau/headers/nvidia/hwref/volta/gv100/dev_fb.h create mode 100644 src/nouveau/headers/nvidia/hwref/volta/gv100/dev_mmu.h diff --git a/src/nouveau/headers/nvidia/hwref/ampere/ga100/dev_fault.h b/src/nouveau/headers/nvidia/hwref/ampere/ga100/dev_fault.h new file mode 100644 index 00000000000..1c8ebde45cc --- /dev/null +++ b/src/nouveau/headers/nvidia/hwref/ampere/ga100/dev_fault.h @@ -0,0 +1,480 @@ +/******************************************************************************* + Copyright (c) 2003-2016 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + + +#ifndef __ga100_dev_fault_h__ +#define __ga100_dev_fault_h__ +/* This file is autogenerated. Do not edit */ +#define NV_PFAULT /* ----G */ +#define NV_PFAULT_MMU_ENG_ID_GRAPHICS 64 /* */ +#define NV_PFAULT_MMU_ENG_ID_DISPLAY 1 /* */ +#define NV_PFAULT_MMU_ENG_ID_GSP 2 /* */ +#define NV_PFAULT_MMU_ENG_ID_IFB 9 /* */ +#define NV_PFAULT_MMU_ENG_ID_FLA 4 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1 128 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2 192 /* */ +#define NV_PFAULT_MMU_ENG_ID_SEC 14 /* */ +#define NV_PFAULT_MMU_ENG_ID_PERF 8 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVDEC 25 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVDEC0 25 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVDEC1 26 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVDEC2 27 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVDEC3 28 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVDEC4 29 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVJPG0 30 /* */ +#define NV_PFAULT_MMU_ENG_ID_GRCOPY 15 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE0 15 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE1 16 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE2 17 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE3 18 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE4 19 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE5 20 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE6 21 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE7 22 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE8 23 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE9 24 /* */ +#define NV_PFAULT_MMU_ENG_ID_PWR_PMU 6 /* */ +#define NV_PFAULT_MMU_ENG_ID_PTP 3 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVENC0 11 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVENC1 12 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVENC2 13 /* */ +#define NV_PFAULT_MMU_ENG_ID_OFA0 10 /* */ +#define NV_PFAULT_MMU_ENG_ID_PHYSICAL 31 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST0 32 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST1 33 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST2 34 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST3 35 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST4 36 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST5 37 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST6 38 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST7 39 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST8 40 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST9 41 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST10 42 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST11 43 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST12 44 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST13 45 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST14 46 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST15 47 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST16 48 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST17 49 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST18 50 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST19 51 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST20 52 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST21 53 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST22 54 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST23 55 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST24 56 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST25 57 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST26 58 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST27 59 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST28 60 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST29 61 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST30 62 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST31 63 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN0 128 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN1 129 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN2 130 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN3 131 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN4 132 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN5 133 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN6 134 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN7 135 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN8 136 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN9 137 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN10 138 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN11 139 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN12 140 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN13 141 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN14 142 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN15 143 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN16 144 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN17 145 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN18 146 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN19 147 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN20 148 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN21 149 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN22 150 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN23 151 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN24 152 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN25 153 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN26 154 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN27 155 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN28 156 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN29 157 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN30 158 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN31 159 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN32 160 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN33 161 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN34 162 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN35 163 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN36 164 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN37 165 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN38 166 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN39 167 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN40 168 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN41 169 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN42 170 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN43 171 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN44 172 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN45 173 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN46 174 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN47 175 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN48 176 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN49 177 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN50 178 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN51 179 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN52 180 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN53 181 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN54 182 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN55 183 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN56 184 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN57 185 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN58 186 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN59 187 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN60 188 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN61 189 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN62 190 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN63 191 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN0 192 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN1 193 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN2 194 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN3 195 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN4 196 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN5 197 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN6 198 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN7 199 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN8 200 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN9 201 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN10 202 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN11 203 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN12 204 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN13 205 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN14 206 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN15 207 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN16 208 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN17 209 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN18 210 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN19 211 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN20 212 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN21 213 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN22 214 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN23 215 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN24 216 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN25 217 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN26 218 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN27 219 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN28 220 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN29 221 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN30 222 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN31 223 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN32 224 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN33 225 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN34 226 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN35 227 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN36 228 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN37 229 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN38 230 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN39 231 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN40 232 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN41 233 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN42 234 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN43 235 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN44 236 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN45 237 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN46 238 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN47 239 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN48 240 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN49 241 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN50 242 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN51 243 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN52 244 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN53 245 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN54 246 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN55 247 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN56 248 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN57 249 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN58 250 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN59 251 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN60 252 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN61 253 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN62 254 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN63 255 /* */ +#define NV_PFAULT_FAULT_TYPE 4:0 /* */ +#define NV_PFAULT_FAULT_TYPE_PDE 0x00000000 /* */ +#define NV_PFAULT_FAULT_TYPE_PDE_SIZE 0x00000001 /* */ +#define NV_PFAULT_FAULT_TYPE_PTE 0x00000002 /* */ +#define NV_PFAULT_FAULT_TYPE_VA_LIMIT_VIOLATION 0x00000003 /* */ +#define NV_PFAULT_FAULT_TYPE_UNBOUND_INST_BLOCK 0x00000004 /* */ +#define NV_PFAULT_FAULT_TYPE_PRIV_VIOLATION 0x00000005 /* */ +#define NV_PFAULT_FAULT_TYPE_RO_VIOLATION 0x00000006 /* */ +#define NV_PFAULT_FAULT_TYPE_WO_VIOLATION 0x00000007 /* */ +#define NV_PFAULT_FAULT_TYPE_PITCH_MASK_VIOLATION 0x00000008 /* */ +#define NV_PFAULT_FAULT_TYPE_WORK_CREATION 0x00000009 /* */ +#define NV_PFAULT_FAULT_TYPE_UNSUPPORTED_APERTURE 0x0000000a /* */ +#define NV_PFAULT_FAULT_TYPE_COMPRESSION_FAILURE 0x0000000b /* */ +#define NV_PFAULT_FAULT_TYPE_UNSUPPORTED_KIND 0x0000000c /* */ +#define NV_PFAULT_FAULT_TYPE_REGION_VIOLATION 0x0000000d /* */ +#define NV_PFAULT_FAULT_TYPE_POISONED 0x0000000e /* */ +#define NV_PFAULT_FAULT_TYPE_ATOMIC_VIOLATION 0x0000000f /* */ +#define NV_PFAULT_CLIENT 14:8 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_0 0x00000000 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_1 0x00000001 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_2 0x00000002 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_3 0x00000003 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_4 0x00000004 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_5 0x00000005 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_6 0x00000006 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_7 0x00000007 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_0 0x00000008 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_1 0x00000009 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_2 0x0000000A /* */ +#define NV_PFAULT_CLIENT_GPC_PE_3 0x0000000B /* */ +#define NV_PFAULT_CLIENT_GPC_PE_4 0x0000000C /* */ +#define NV_PFAULT_CLIENT_GPC_PE_5 0x0000000D /* */ +#define NV_PFAULT_CLIENT_GPC_PE_6 0x0000000E /* */ +#define NV_PFAULT_CLIENT_GPC_PE_7 0x0000000F /* */ +#define NV_PFAULT_CLIENT_GPC_RAST 0x00000010 /* */ +#define NV_PFAULT_CLIENT_GPC_GCC 0x00000011 /* */ +#define NV_PFAULT_CLIENT_GPC_GPCCS 0x00000012 /* */ +#define NV_PFAULT_CLIENT_GPC_PROP_0 0x00000013 /* */ +#define NV_PFAULT_CLIENT_GPC_PROP_1 0x00000014 /* */ +#define NV_PFAULT_CLIENT_GPC_PROP_2 0x00000015 /* */ +#define NV_PFAULT_CLIENT_GPC_PROP_3 0x00000016 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_8 0x00000021 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_9 0x00000022 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_10 0x00000023 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_11 0x00000024 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_12 0x00000025 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_13 0x00000026 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_14 0x00000027 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_15 0x00000028 /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_0 0x00000029 /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_1 0x0000002A /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_2 0x0000002B /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_3 0x0000002C /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_4 0x0000002D /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_5 0x0000002E /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_6 0x0000002F /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_7 0x00000030 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_8 0x00000031 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_9 0x00000032 /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_8 0x00000033 /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_9 0x00000034 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_16 0x00000035 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_17 0x00000036 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_18 0x00000037 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_19 0x00000038 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_10 0x00000039 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_11 0x0000003A /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_10 0x0000003B /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_11 0x0000003C /* */ +#define NV_PFAULT_CLIENT_GPC_T1_20 0x0000003D /* */ +#define NV_PFAULT_CLIENT_GPC_T1_21 0x0000003E /* */ +#define NV_PFAULT_CLIENT_GPC_T1_22 0x0000003F /* */ +#define NV_PFAULT_CLIENT_GPC_T1_23 0x00000040 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_12 0x00000041 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_13 0x00000042 /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_12 0x00000043 /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_13 0x00000044 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_24 0x00000045 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_25 0x00000046 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_26 0x00000047 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_27 0x00000048 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_14 0x00000049 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_15 0x0000004A /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_14 0x0000004B /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_15 0x0000004C /* */ +#define NV_PFAULT_CLIENT_GPC_T1_28 0x0000004D /* */ +#define NV_PFAULT_CLIENT_GPC_T1_29 0x0000004E /* */ +#define NV_PFAULT_CLIENT_GPC_T1_30 0x0000004F /* */ +#define NV_PFAULT_CLIENT_GPC_T1_31 0x00000050 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_16 0x00000051 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_17 0x00000052 /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_16 0x00000053 /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_17 0x00000054 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_32 0x00000055 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_33 0x00000056 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_34 0x00000057 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_35 0x00000058 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_18 0x00000059 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_19 0x0000005A /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_18 0x0000005B /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_19 0x0000005C /* */ +#define NV_PFAULT_CLIENT_GPC_T1_36 0x0000005D /* */ +#define NV_PFAULT_CLIENT_GPC_T1_37 0x0000005E /* */ +#define NV_PFAULT_CLIENT_GPC_T1_38 0x0000005F /* */ +#define NV_PFAULT_CLIENT_GPC_T1_39 0x00000060 /* */ +#define NV_PFAULT_CLIENT_GPC_ROP_0 0x00000070 /* */ +#define NV_PFAULT_CLIENT_GPC_ROP_1 0x00000071 /* */ +#define NV_PFAULT_CLIENT_GPC_ROP_2 0x00000072 /* */ +#define NV_PFAULT_CLIENT_GPC_ROP_3 0x00000073 /* */ +#define NV_PFAULT_CLIENT_GPC_GPM 0x00000017 /* */ +#define NV_PFAULT_CLIENT_GPC_LTP_UTLB_0 0x00000018 /* */ +#define NV_PFAULT_CLIENT_GPC_LTP_UTLB_1 0x00000019 /* */ +#define NV_PFAULT_CLIENT_GPC_LTP_UTLB_2 0x0000001A /* */ +#define NV_PFAULT_CLIENT_GPC_LTP_UTLB_3 0x0000001B /* */ +#define NV_PFAULT_CLIENT_GPC_LTP_UTLB_4 0x0000001C /* */ +#define NV_PFAULT_CLIENT_GPC_LTP_UTLB_5 0x0000001D /* */ +#define NV_PFAULT_CLIENT_GPC_LTP_UTLB_6 0x0000001E /* */ +#define NV_PFAULT_CLIENT_GPC_LTP_UTLB_7 0x0000001F /* */ +#define NV_PFAULT_CLIENT_GPC_RGG_UTLB 0x00000020 /* */ +#define NV_PFAULT_CLIENT_GPC_LTP_UTLB_8 0x00000031 /* */ +#define NV_PFAULT_CLIENT_GPC_LTP_UTLB_9 0x00000032 /* */ +#define NV_PFAULT_CLIENT_GPC_LTP_UTLB_10 0x00000033 /* */ +#define NV_PFAULT_CLIENT_GPC_LTP_UTLB_11 0x00000034 /* */ +#define NV_PFAULT_CLIENT_GPC_LTP_UTLB_12 0x00000035 /* */ +#define NV_PFAULT_CLIENT_GPC_LTP_UTLB_13 0x00000036 /* */ +#define NV_PFAULT_CLIENT_GPC_LTP_UTLB_14 0x00000037 /* */ +#define NV_PFAULT_CLIENT_GPC_LTP_UTLB_15 0x00000038 /* */ +#define NV_PFAULT_CLIENT_HUB_VIP 0x00000000 /* */ +#define NV_PFAULT_CLIENT_HUB_CE0 0x00000001 /* */ +#define NV_PFAULT_CLIENT_HUB_CE1 0x00000002 /* */ +#define NV_PFAULT_CLIENT_HUB_DNISO 0x00000003 /* */ +#define NV_PFAULT_CLIENT_HUB_DISPNISO 0x00000003 /* */ +#define NV_PFAULT_CLIENT_HUB_FE0 0x00000004 /* */ +#define NV_PFAULT_CLIENT_HUB_FE 0x00000004 /* */ +#define NV_PFAULT_CLIENT_HUB_FECS0 0x00000005 /* */ +#define NV_PFAULT_CLIENT_HUB_FECS 0x00000005 /* */ +#define NV_PFAULT_CLIENT_HUB_HOST 0x00000006 /* */ +#define NV_PFAULT_CLIENT_HUB_HOST_CPU 0x00000007 /* */ +#define NV_PFAULT_CLIENT_HUB_HOST_CPU_NB 0x00000008 /* */ +#define NV_PFAULT_CLIENT_HUB_ISO 0x00000009 /* */ +#define NV_PFAULT_CLIENT_HUB_MMU 0x0000000A /* */ +#define NV_PFAULT_CLIENT_HUB_NVDEC0 0x0000000B /* */ +#define NV_PFAULT_CLIENT_HUB_NVDEC 0x0000000B /* */ +#define NV_PFAULT_CLIENT_HUB_NVENC1 0x0000000D /* */ +#define NV_PFAULT_CLIENT_HUB_NISO 0x0000000E /* */ +#define NV_PFAULT_CLIENT_HUB_ACTRS 0x0000000E /* */ +#define NV_PFAULT_CLIENT_HUB_P2P 0x0000000F /* */ +#define NV_PFAULT_CLIENT_HUB_PD 0x00000010 /* */ +#define NV_PFAULT_CLIENT_HUB_PERF0 0x00000011 /* */ +#define NV_PFAULT_CLIENT_HUB_PERF 0x00000011 /* */ +#define NV_PFAULT_CLIENT_HUB_PMU 0x00000012 /* */ +#define NV_PFAULT_CLIENT_HUB_RASTERTWOD 0x00000013 /* */ +#define NV_PFAULT_CLIENT_HUB_SCC 0x00000014 /* */ +#define NV_PFAULT_CLIENT_HUB_SCC_NB 0x00000015 /* */ +#define NV_PFAULT_CLIENT_HUB_SEC 0x00000016 /* */ +#define NV_PFAULT_CLIENT_HUB_SSYNC 0x00000017 /* */ +#define NV_PFAULT_CLIENT_HUB_GRCOPY 0x00000018 /* */ +#define NV_PFAULT_CLIENT_HUB_CE2 0x00000018 /* */ +#define NV_PFAULT_CLIENT_HUB_XV 0x00000019 /* */ +#define NV_PFAULT_CLIENT_HUB_MMU_NB 0x0000001A /* */ +#define NV_PFAULT_CLIENT_HUB_NVENC0 0x0000001B /* */ +#define NV_PFAULT_CLIENT_HUB_NVENC 0x0000001B /* */ +#define NV_PFAULT_CLIENT_HUB_DFALCON 0x0000001C /* */ +#define NV_PFAULT_CLIENT_HUB_SKED0 0x0000001D /* */ +#define NV_PFAULT_CLIENT_HUB_SKED 0x0000001D /* */ +#define NV_PFAULT_CLIENT_HUB_AFALCON 0x0000001E /* */ +#define NV_PFAULT_CLIENT_HUB_DONT_CARE 0x0000001F /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE0 0x00000020 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE1 0x00000021 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE2 0x00000022 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE3 0x00000023 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE4 0x00000024 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE5 0x00000025 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE6 0x00000026 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE7 0x00000027 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE8 0x00000028 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE9 0x00000029 /* */ +#define NV_PFAULT_CLIENT_HUB_HSHUB 0x0000002A /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X0 0x0000002B /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X1 0x0000002C /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X2 0x0000002D /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X3 0x0000002E /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X4 0x0000002F /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X5 0x00000030 /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X6 0x00000031 /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X7 0x00000032 /* */ +#define NV_PFAULT_CLIENT_HUB_NVENC2 0x00000033 /* */ +#define NV_PFAULT_CLIENT_HUB_VPR_SCRUBBER0 0x00000034 /* */ +#define NV_PFAULT_CLIENT_HUB_VPR_SCRUBBER1 0x00000035 /* */ +#define NV_PFAULT_CLIENT_HUB_DWBIF 0x00000036 /* */ +#define NV_PFAULT_CLIENT_HUB_FBFALCON 0x00000037 /* */ +#define NV_PFAULT_CLIENT_HUB_CE_SHIM 0x00000038 /* */ +#define NV_PFAULT_CLIENT_HUB_GSP 0x00000039 /* */ +#define NV_PFAULT_CLIENT_HUB_NVDEC1 0x0000003A /* */ +#define NV_PFAULT_CLIENT_HUB_NVDEC2 0x0000003B /* */ +#define NV_PFAULT_CLIENT_HUB_NVJPG0 0x0000003C /* */ +#define NV_PFAULT_CLIENT_HUB_NVDEC3 0x0000003D /* */ +#define NV_PFAULT_CLIENT_HUB_NVDEC4 0x0000003E /* */ +#define NV_PFAULT_CLIENT_HUB_OFA0 0x0000003F /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE10 0x00000040 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE11 0x00000041 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE12 0x00000042 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE13 0x00000043 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE14 0x00000044 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE15 0x00000045 /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X8 0x00000046 /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X9 0x00000047 /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X10 0x00000048 /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X11 0x00000049 /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X12 0x0000004A /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X13 0x0000004B /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X14 0x0000004C /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X15 0x0000004D /* */ +#define NV_PFAULT_CLIENT_HUB_FE1 0x0000004E /* */ +#define NV_PFAULT_CLIENT_HUB_FE2 0x0000004F /* */ +#define NV_PFAULT_CLIENT_HUB_FE3 0x00000050 /* */ +#define NV_PFAULT_CLIENT_HUB_FE4 0x00000051 /* */ +#define NV_PFAULT_CLIENT_HUB_FE5 0x00000052 /* */ +#define NV_PFAULT_CLIENT_HUB_FE6 0x00000053 /* */ +#define NV_PFAULT_CLIENT_HUB_FE7 0x00000054 /* */ +#define NV_PFAULT_CLIENT_HUB_FECS1 0x00000055 /* */ +#define NV_PFAULT_CLIENT_HUB_FECS2 0x00000056 /* */ +#define NV_PFAULT_CLIENT_HUB_FECS3 0x00000057 /* */ +#define NV_PFAULT_CLIENT_HUB_FECS4 0x00000058 /* */ +#define NV_PFAULT_CLIENT_HUB_FECS5 0x00000059 /* */ +#define NV_PFAULT_CLIENT_HUB_FECS6 0x0000005A /* */ +#define NV_PFAULT_CLIENT_HUB_FECS7 0x0000005B /* */ +#define NV_PFAULT_CLIENT_HUB_SKED1 0x0000005C /* */ +#define NV_PFAULT_CLIENT_HUB_SKED2 0x0000005D /* */ +#define NV_PFAULT_CLIENT_HUB_SKED3 0x0000005E /* */ +#define NV_PFAULT_CLIENT_HUB_SKED4 0x0000005F /* */ +#define NV_PFAULT_CLIENT_HUB_SKED5 0x00000060 /* */ +#define NV_PFAULT_CLIENT_HUB_SKED6 0x00000061 /* */ +#define NV_PFAULT_CLIENT_HUB_SKED7 0x00000062 /* */ +#define NV_PFAULT_CLIENT_HUB_ESC 0x00000063 /* */ +#define NV_PFAULT_ACCESS_TYPE 19:16 /* */ +#define NV_PFAULT_ACCESS_TYPE_READ 0x00000000 /* */ +#define NV_PFAULT_ACCESS_TYPE_WRITE 0x00000001 /* */ +#define NV_PFAULT_ACCESS_TYPE_ATOMIC 0x00000002 /* */ +#define NV_PFAULT_ACCESS_TYPE_PREFETCH 0x00000003 /* */ +#define NV_PFAULT_ACCESS_TYPE_VIRT_READ 0x00000000 /* */ +#define NV_PFAULT_ACCESS_TYPE_VIRT_WRITE 0x00000001 /* */ +#define NV_PFAULT_ACCESS_TYPE_VIRT_ATOMIC 0x00000002 /* */ +#define NV_PFAULT_ACCESS_TYPE_VIRT_ATOMIC_STRONG 0x00000002 /* */ +#define NV_PFAULT_ACCESS_TYPE_VIRT_PREFETCH 0x00000003 /* */ +#define NV_PFAULT_ACCESS_TYPE_VIRT_ATOMIC_WEAK 0x00000004 /* */ +#define NV_PFAULT_ACCESS_TYPE_PHYS_READ 0x00000008 /* */ +#define NV_PFAULT_ACCESS_TYPE_PHYS_WRITE 0x00000009 /* */ +#define NV_PFAULT_ACCESS_TYPE_PHYS_ATOMIC 0x0000000a /* */ +#define NV_PFAULT_ACCESS_TYPE_PHYS_PREFETCH 0x0000000b /* */ +#define NV_PFAULT_MMU_CLIENT_TYPE 20:20 /* */ +#define NV_PFAULT_MMU_CLIENT_TYPE_GPC 0x00000000 /* */ +#define NV_PFAULT_MMU_CLIENT_TYPE_HUB 0x00000001 /* */ +#define NV_PFAULT_GPC_ID 28:24 /* */ +#define NV_PFAULT_PROTECTED_MODE 29:29 /* */ +#define NV_PFAULT_REPLAYABLE_FAULT_EN 30:30 /* */ +#define NV_PFAULT_VALID 31:31 /* */ +#endif // __ga100_dev_fault_h__ diff --git a/src/nouveau/headers/nvidia/hwref/ampere/ga100/dev_runlist.h b/src/nouveau/headers/nvidia/hwref/ampere/ga100/dev_runlist.h new file mode 100644 index 00000000000..e38e49dda5d --- /dev/null +++ b/src/nouveau/headers/nvidia/hwref/ampere/ga100/dev_runlist.h @@ -0,0 +1,782 @@ +/******************************************************************************* + Copyright (c) 2003-2016 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + + +#ifndef __ga100_dev_runlist_h__ +#define __ga100_dev_runlist_h__ +/* This file is autogenerated. Do not edit */ +#define NV_RUNLIST 0x000003ff:0x00000000 /* RW--D */ +#define NV_CHRAM 0x00001fff:0x00000000 /* RW--D */ +#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK 0x040 /* RW-4R */ +#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ +#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWI-V */ +#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ +#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ +#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ +#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ +#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ +#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ +#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ +#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ +#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ +#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ +#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ +#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ +#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ +#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ +#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ +#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 8 /* RWI-V */ +#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0F /* RW--V */ +#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x08 /* RW--V */ +#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ +#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ +#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ +#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ +#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ +#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ +#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ +#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ +#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ +#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ +#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ +#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ +#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ +#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ +#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ +#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ +#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ +#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ +#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ +#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ +#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ +#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ +#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ +#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ +#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ +#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */ +#define NV_RUNLIST_INT_CYA_SPARE 0x044 /* RW-4R */ +#define NV_RUNLIST_INT_CYA_SPARE__PRIV_LEVEL_MASK 0x040 /* */ +#define NV_RUNLIST_INT_CYA_SPARE_DATA 31:0 /* RWIUF */ +#define NV_RUNLIST_INT_CYA_SPARE_DATA_INIT 0x00000000 /* RWI-V */ +#define NV_RUNLIST_INT_CYA_SPARE_FORCE_FE_MTHD_THROTTLE 0:0 /* */ +#define NV_RUNLIST_INT_CYA_SPARE_FORCE_FE_MTHD_THROTTLE_VAL 1:1 /* */ +#define NV_RUNLIST_INT_CYA_SPARE_FORCE_FE_MTHD_THROTTLE_VAL_1MTHD 0x00000000 /* */ +#define NV_RUNLIST_INT_CYA_SPARE_FORCE_FE_MTHD_THROTTLE_VAL_2MTHD 0x00000001 /* */ +#define NV_RUNLIST_CONFIG 0x000 /* RW-4R */ +#define NV_RUNLIST_CONFIG_SEM_ACQ_STRENGTH 0:0 /* RWIVF */ +#define NV_RUNLIST_CONFIG_SEM_ACQ_STRENGTH_WEAK 0x00000000 /* RWI-V */ +#define NV_RUNLIST_CONFIG_SEM_ACQ_STRENGTH_STRONG 0x00000001 /* RW--V */ +#define NV_RUNLIST_CONFIG_SEM_REL_STRENGTH 4:4 /* RWIVF */ +#define NV_RUNLIST_CONFIG_SEM_REL_STRENGTH_WEAK 0x00000000 /* RW--V */ +#define NV_RUNLIST_CONFIG_SEM_REL_STRENGTH_STRONG 0x00000001 /* RWI-V */ +#define NV_RUNLIST_CONFIG_L2_EVICT 9:8 /* RWIVF */ +#define NV_RUNLIST_CONFIG_L2_EVICT_FIRST 0x00000000 /* RWI-V */ +#define NV_RUNLIST_CONFIG_L2_EVICT_NORMAL 0x00000001 /* RW--V */ +#define NV_RUNLIST_CONFIG_L2_EVICT_LAST 0x00000002 /* RW--V */ +#define NV_RUNLIST_CONFIG_SUBCH4 10:10 /* RWXVF */ +#define NV_RUNLIST_CONFIG_SUBCH4_INACTIVE 0x00000000 /* RW--V */ +#define NV_RUNLIST_CONFIG_SUBCH4_ACTIVE 0x00000001 /* RW--V */ +#define NV_RUNLIST_CHANNEL_CONFIG 0x004 /* R--4R */ +#define NV_RUNLIST_CHANNEL_CONFIG_NUM_CHANNELS_LOG2 3:0 /* C--UF */ +#define NV_RUNLIST_CHANNEL_CONFIG_NUM_CHANNELS_LOG2_2K 11 /* C---V */ +#define NV_RUNLIST_CHANNEL_CONFIG_CHRAM_BAR0_OFFSET 31:4 /* R-XVF */ +#define NV_RUNLIST_DOORBELL_CONFIG 0x008 /* R--4R */ +#define NV_RUNLIST_DOORBELL_CONFIG_ID 31:16 /* R-XVF */ +#define NV_RUNLIST_FB_CONFIG 0x00C /* R--4R */ +#define NV_RUNLIST_FB_CONFIG_FB_THREAD_ID 7:0 /* R-XVF */ +#define NV_RUNLIST_FB_CONFIG_ESC_ID 15:8 /* R-XVF */ +#define NV_RUNLIST_VIRTUAL_CHANNEL_CFG(i) (0x300+(i)*4) /* RW-4A */ +#define NV_RUNLIST_VIRTUAL_CHANNEL_CFG__SIZE_1 64 /* */ +#define NV_RUNLIST_VIRTUAL_CHANNEL_CFG_MASK 11:0 /* */ +#define NV_RUNLIST_VIRTUAL_CHANNEL_CFG_MASK_HW 10:0 /* RWIVF */ +#define NV_RUNLIST_VIRTUAL_CHANNEL_CFG_MASK_HW_INIT 2047 /* RWI-V */ +#define NV_RUNLIST_VIRTUAL_CHANNEL_CFG_SET 27:16 /* */ +#define NV_RUNLIST_VIRTUAL_CHANNEL_CFG_SET_HW 26:16 /* RWIVF */ +#define NV_RUNLIST_VIRTUAL_CHANNEL_CFG_SET_HW_INIT 0x0 /* RWI-V */ +#define NV_RUNLIST_VIRTUAL_CHANNEL_CFG_PENDING_ENABLE 31:31 /* RWIVF */ +#define NV_RUNLIST_VIRTUAL_CHANNEL_CFG_PENDING_ENABLE_TRUE 1 /* RW--V */ +#define NV_RUNLIST_VIRTUAL_CHANNEL_CFG_PENDING_ENABLE_FALSE 0 /* RWI-V */ +#define NV_RUNLIST_PBDMA_CONFIG(i) (0x010+(i)*4) /* R--4A */ +#define NV_RUNLIST_PBDMA_CONFIG__SIZE_1 2 /* */ +#define NV_RUNLIST_PBDMA_CONFIG_PBDMA_ID 7:0 /* R-XUF */ +#define NV_RUNLIST_PBDMA_CONFIG_PBDMA_BAR0_OFFSET 25:10 /* R-XUF */ +#define NV_RUNLIST_PBDMA_CONFIG_VALID 31:31 /* R-XUF */ +#define NV_RUNLIST_PBDMA_CONFIG_VALID_TRUE 0x00000001 /* R---V */ +#define NV_RUNLIST_PBDMA_CONFIG_VALID_FALSE 0x00000000 /* R---V */ +#define NV_RUNLIST_ACQ_PRETEST 0x020 /* RW-4R */ +#define NV_RUNLIST_ACQ_PRETEST_TIMEOUT 7:0 /* RWIUF */ +#define NV_RUNLIST_ACQ_PRETEST_TIMEOUT_8 0x00000008 /* RWI-V */ +#define NV_RUNLIST_ACQ_PRETEST_TIMESCALE 15:12 /* RWIUF */ +#define NV_RUNLIST_ACQ_PRETEST_TIMESCALE_0 0x00000000 /* RWI-V */ +#define NV_RUNLIST_ACQ_PRETEST_TIMESCALE_10 0x0000000a /* RW--V */ +#define NV_RUNLIST_IDLE_FILTER 0x024 /* RW-4R */ +#define NV_RUNLIST_IDLE_FILTER_PERIOD 7:0 /* RWIUF */ +#define NV_RUNLIST_IDLE_FILTER_PERIOD_INIT 0x00000050 /* RWI-V */ +#define NV_RUNLIST_IDLE_FILTER_PERIOD__PROD 0x00000064 /* RW--V */ +#define NV_RUNLIST_IDLE_FILTER_PERIOD_8 0x00000008 /* RW--V */ +#define NV_RUNLIST_IDLE_FILTER_PERIOD_32 0x00000020 /* RW--V */ +#define NV_RUNLIST_USERD_WRITEBACK 0x028 /* RW-4R */ +#define NV_RUNLIST_USERD_WRITEBACK_TIMER 7:0 /* RWIUF */ +#define NV_RUNLIST_USERD_WRITEBACK_TIMER_DISABLED 0x00000000 /* RW--V */ +#define NV_RUNLIST_USERD_WRITEBACK_TIMER_SHORT 0x00000003 /* RW--V */ +#define NV_RUNLIST_USERD_WRITEBACK_TIMER_100US 0x00000064 /* RWI-V */ +#define NV_RUNLIST_USERD_WRITEBACK_TIMESCALE 15:12 /* RWIUF */ +#define NV_RUNLIST_USERD_WRITEBACK_TIMESCALE_0 0x00000000 /* RWI-V */ +#define NV_RUNLIST_USERD_WRITEBACK_TIMESCALE_SHORT 0x00000000 /* */ +#define NV_RUNLIST_USERD_WRITEBACK_TIMESCALE_100US 0x00000000 /* */ +#define NV_RUNLIST_ESCHED_CONFIG 0x02c /* C--4R */ +#define NV_RUNLIST_ESCHED_CONFIG_ESCHED_CLASS_ID 15:0 /* C--UF */ +#define NV_RUNLIST_ESCHED_CONFIG_ESCHED_CLASS_ID_VALUE 50543 /* C---V */ +#define NV_CHRAM_CHANNEL(i) (0x000+(i)*4) /* RW-4A */ +#define NV_CHRAM_CHANNEL__SIZE_1 2048 /* */ +#define NV_CHRAM_CHANNEL_WRITE_CONTROL 0:0 /* -WIVF */ +#define NV_CHRAM_CHANNEL_WRITE_CONTROL_ONES_SET_BITS 0x00000000 /* -WI-V */ +#define NV_CHRAM_CHANNEL_WRITE_CONTROL_ONES_CLEAR_BITS 0x00000001 /* -W--V */ +#define NV_CHRAM_CHANNEL_ENABLE 1:1 /* RWIVF */ +#define NV_CHRAM_CHANNEL_ENABLE_NOT_IN_USE 0x00000000 /* RWI-V */ +#define NV_CHRAM_CHANNEL_ENABLE_IN_USE 0x00000001 /* RW--V */ +#define NV_CHRAM_CHANNEL_NEXT 2:2 /* RWIVF */ +#define NV_CHRAM_CHANNEL_NEXT_FALSE 0x00000000 /* RWI-V */ +#define NV_CHRAM_CHANNEL_NEXT_TRUE 0x00000001 /* RW--V */ +#define NV_CHRAM_CHANNEL_BUSY 3:3 /* R-IVF */ +#define NV_CHRAM_CHANNEL_BUSY_FALSE 0x00000000 /* R-I-V */ +#define NV_CHRAM_CHANNEL_BUSY_TRUE 0x00000001 /* R---V */ +#define NV_CHRAM_CHANNEL_PBDMA_FAULTED 4:4 /* RWIVF */ +#define NV_CHRAM_CHANNEL_PBDMA_FAULTED_FALSE 0x00000000 /* RWI-V */ +#define NV_CHRAM_CHANNEL_PBDMA_FAULTED_TRUE 0x00000001 /* RW--V */ +#define NV_CHRAM_CHANNEL_ENG_FAULTED 5:5 /* RWIVF */ +#define NV_CHRAM_CHANNEL_ENG_FAULTED_FALSE 0x00000000 /* RWI-V */ +#define NV_CHRAM_CHANNEL_ENG_FAULTED_TRUE 0x00000001 /* RW--V */ +#define NV_CHRAM_CHANNEL_ON_PBDMA 6:6 /* R-IVF */ +#define NV_CHRAM_CHANNEL_ON_PBDMA_FALSE 0x00000000 /* R-I-V */ +#define NV_CHRAM_CHANNEL_ON_PBDMA_TRUE 0x00000001 /* R---V */ +#define NV_CHRAM_CHANNEL_ON_ENG 7:7 /* R-IVF */ +#define NV_CHRAM_CHANNEL_ON_ENG_FALSE 0x00000000 /* R-I-V */ +#define NV_CHRAM_CHANNEL_ON_ENG_TRUE 0x00000001 /* R---V */ +#define NV_CHRAM_CHANNEL_PENDING 8:8 /* RWIVF */ +#define NV_CHRAM_CHANNEL_PENDING_FALSE 0x00000000 /* RWI-V */ +#define NV_CHRAM_CHANNEL_PENDING_TRUE 0x00000001 /* RW--V */ +#define NV_CHRAM_CHANNEL_CTX_RELOAD 9:9 /* RWIVF */ +#define NV_CHRAM_CHANNEL_CTX_RELOAD_FALSE 0x00000000 /* RWI-V */ +#define NV_CHRAM_CHANNEL_CTX_RELOAD_TRUE 0x00000001 /* RW--V */ +#define NV_CHRAM_CHANNEL_PBDMA_BUSY 10:10 /* R-IVF */ +#define NV_CHRAM_CHANNEL_PBDMA_BUSY_FALSE 0x00000000 /* R-I-V */ +#define NV_CHRAM_CHANNEL_PBDMA_BUSY_TRUE 0x00000001 /* R---V */ +#define NV_CHRAM_CHANNEL_ENG_BUSY 11:11 /* R-IVF */ +#define NV_CHRAM_CHANNEL_ENG_BUSY_FALSE 0x00000000 /* R-I-V */ +#define NV_CHRAM_CHANNEL_ENG_BUSY_TRUE 0x00000001 /* R---V */ +#define NV_CHRAM_CHANNEL_ACQUIRE_FAIL 12:12 /* RWIVF */ +#define NV_CHRAM_CHANNEL_ACQUIRE_FAIL_FALSE 0x00000000 /* RWI-V */ +#define NV_CHRAM_CHANNEL_ACQUIRE_FAIL_TRUE 0x00000001 /* RW--V */ +#define NV_CHRAM_CHANNEL_STATUS 12:8 /* */ +#define NV_CHRAM_CHANNEL_STATUS_IDLE 0x00000000 /* */ +#define NV_CHRAM_CHANNEL_STATUS_PENDING 0x00000001 /* */ +#define NV_CHRAM_CHANNEL_STATUS_PENDING_CTX_RELOAD 0x00000003 /* */ +#define NV_CHRAM_CHANNEL_STATUS_PENDING_ACQUIRE_FAIL 0x00000011 /* */ +#define NV_CHRAM_CHANNEL_STATUS_PENDING_ACQUIRE_FAIL_CTX_RELOAD 0x00000013 /* */ +#define NV_CHRAM_CHANNEL_STATUS_PBDMA_BUSY 0x00000004 /* */ +#define NV_CHRAM_CHANNEL_STATUS_PBDMA_BUSY_AND_ENG_BUSY 0x0000000C /* */ +#define NV_CHRAM_CHANNEL_STATUS_ENG_BUSY 0x00000008 /* */ +#define NV_CHRAM_CHANNEL_STATUS_ENG_BUSY_PENDING_ACQUIRE_FAIL 0x00000019 /* */ +#define NV_CHRAM_CHANNEL_STATUS_ENG_BUSY_PENDING 0x00000009 /* */ +#define NV_CHRAM_CHANNEL_STATUS_PBDMA_BUSY_CTX_RELOAD 0x00000006 /* */ +#define NV_CHRAM_CHANNEL_STATUS_PBDMA_BUSY_ENG_BUSY_CTX_RELOAD 0x0000000E /* */ +#define NV_CHRAM_CHANNEL_STATUS_ENG_BUSY_CTX_RELOAD 0x0000000A /* */ +#define NV_CHRAM_CHANNEL_STATUS_ENG_BUSY_PENDING_CTX_RELOAD 0x0000000B /* */ +#define NV_CHRAM_CHANNEL_STATUS_ENG_BUSY_PENDING_ACQUIRE_FAIL_CTX_RELOAD 0x0000001B /* */ +#define NV_CHRAM_CHANNEL_UPDATE 31:0 /* */ +#define NV_CHRAM_CHANNEL_UPDATE_ENABLE_CHANNEL 0x00000002 /* */ +#define NV_CHRAM_CHANNEL_UPDATE_DISABLE_CHANNEL 0x00000003 /* */ +#define NV_CHRAM_CHANNEL_UPDATE_FORCE_CTX_RELOAD 0x00000200 /* */ +#define NV_CHRAM_CHANNEL_UPDATE_RESET_PBDMA_FAULTED 0x00000011 /* */ +#define NV_CHRAM_CHANNEL_UPDATE_RESET_ENG_FAULTED 0x00000021 /* */ +#define NV_CHRAM_CHANNEL_UPDATE_CLEAR_CHANNEL 0xFFFFFFFF /* */ +#define NV_RUNLIST_SUBMIT_BASE_LO 0x080 /* RW-4R */ +#define NV_RUNLIST_SUBMIT_BASE_LO_PTR_LO 31:12 /* RWIUF */ +#define NV_RUNLIST_SUBMIT_BASE_LO_PTR_LO_NULL 0x00000000 /* RWI-V */ +#define NV_RUNLIST_SUBMIT_BASE_LO_TARGET 1:0 /* RWIVF */ +#define NV_RUNLIST_SUBMIT_BASE_LO_TARGET_VID_MEM 0x0 /* RWI-V */ +#define NV_RUNLIST_SUBMIT_BASE_LO_TARGET_SYS_MEM_COHERENT 0x2 /* RW--V */ +#define NV_RUNLIST_SUBMIT_BASE_LO_TARGET_SYS_MEM_NONCOHERENT 0x3 /* RW--V */ +#define NV_RUNLIST_SUBMIT_BASE_LO_PTR_ALIGN_SHIFT 12 /* */ +#define NV_RUNLIST_SUBMIT_BASE_HI 0x084 /* RW-4R */ +#define NV_RUNLIST_SUBMIT_BASE_HI_PTR_HI 7:0 /* RWIUF */ +#define NV_RUNLIST_SUBMIT_BASE_HI_PTR_HI_NULL 0x00000000 /* RWI-V */ +#define NV_RUNLIST_SUBMIT 0x088 /* RW-4R */ +#define NV_RUNLIST_SUBMIT_LENGTH 15:0 /* RWIUF */ +#define NV_RUNLIST_SUBMIT_LENGTH_ZERO 0x00000000 /* RWI-V */ +#define NV_RUNLIST_SUBMIT_LENGTH_MAX 0x0000ffff /* RW--V */ +#define NV_RUNLIST_SUBMIT_OFFSET 31:16 /* RWIVF */ +#define NV_RUNLIST_SUBMIT_OFFSET_ZERO 0x00000000 /* RWI-V */ +#define NV_RUNLIST_SUBMIT_INFO 0x08C /* R--4R */ +#define NV_RUNLIST_SUBMIT_INFO_PREEMPTED_TSGID 13:0 /* */ +#define NV_RUNLIST_SUBMIT_INFO_PREEMPTED_TSGID_HW 10:0 /* R-IUF */ +#define NV_RUNLIST_SUBMIT_INFO_PREEMPTED_TSGID_HW_DEFAULT 0x00000000 /* R-I-V */ +#define NV_RUNLIST_SUBMIT_INFO_PREEMPTED_TSGID_VALID 14:14 /* R-IUF */ +#define NV_RUNLIST_SUBMIT_INFO_PREEMPTED_TSGID_VALID_FALSE 0x00000000 /* R-I-V */ +#define NV_RUNLIST_SUBMIT_INFO_PREEMPTED_TSGID_VALID_TRUE 0x00000001 /* R---V */ +#define NV_RUNLIST_SUBMIT_INFO_PENDING 15:15 /* R-IVF */ +#define NV_RUNLIST_SUBMIT_INFO_PENDING_FALSE 0x00000000 /* R-I-V */ +#define NV_RUNLIST_SUBMIT_INFO_PENDING_TRUE 0x00000001 /* R---V */ +#define NV_RUNLIST_SUBMIT_INFO_PREEMPTED_OFFSET 31:16 /* R-IVF */ +#define NV_RUNLIST_SUBMIT_INFO_PREEMPTED_OFFSET_ZERO 0x00000000 /* R-I-V */ +#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK(i) (0x190+(i)*4) /* RW-4A */ +#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK__SIZE_1 2 /* */ +#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ +#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWI-V */ +#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ +#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ +#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ +#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ +#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ +#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ +#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ +#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ +#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ +#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ +#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ +#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ +#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ +#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ +#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ +#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWI-V */ +#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0F /* RW--V */ +#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x08 /* RW--V */ +#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ +#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ +#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ +#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ +#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ +#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ +#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ +#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ +#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ +#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ +#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ +#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ +#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ +#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ +#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ +#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ +#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ +#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ +#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ +#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ +#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ +#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ +#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ +#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ +#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ +#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */ +#define NV_RUNLIST_INTR_VECTORID(i) (0x160+(i)*4) /* RW-4A */ +#define NV_RUNLIST_INTR_VECTORID__SIZE_1 2 /* */ +#define NV_RUNLIST_INTR_VECTORID__PRIV_LEVEL_MASK "NV_RUNLIST_INTR_PRIV_LEVEL_MASK" /* */ +#define NV_RUNLIST_INTR_VECTORID_VECTOR 11:0 /* RWXUF */ +#define NV_RUNLIST_INTR_VECTORID_GSP 30:30 /* RWIUF */ +#define NV_RUNLIST_INTR_VECTORID_GSP_DISABLE 0 /* RW--V */ +#define NV_RUNLIST_INTR_VECTORID_GSP_ENABLE 1 /* RWI-V */ +#define NV_RUNLIST_INTR_VECTORID_CPU 31:31 /* RWIUF */ +#define NV_RUNLIST_INTR_VECTORID_CPU_DISABLE 0 /* RW--V */ +#define NV_RUNLIST_INTR_VECTORID_CPU_ENABLE 1 /* RWI-V */ +#define NV_RUNLIST_INTR_RETRIGGER(i) (0x180+(i)*4) /* -W-4A */ +#define NV_RUNLIST_INTR_RETRIGGER__SIZE_1 2 /* */ +#define NV_RUNLIST_INTR_RETRIGGER__PRIV_LEVEL_MASK "NV_RUNLIST_INTR_PRIV_LEVEL_MASK" /* */ +#define NV_RUNLIST_INTR_RETRIGGER_TRIGGER 0:0 /* -W-VF */ +#define NV_RUNLIST_INTR_RETRIGGER_TRIGGER_TRUE 1 /* -W--V */ +#define NV_RUNLIST_INTR_0 0x100 /* RW-4R */ +#define NV_RUNLIST_INTR_0_CTXSW_TIMEOUT_ENG0 0:0 /* RWIVF */ +#define NV_RUNLIST_INTR_0_CTXSW_TIMEOUT_ENG0_NOT_PENDING 0x00000000 /* R-I-V */ +#define NV_RUNLIST_INTR_0_CTXSW_TIMEOUT_ENG0_PENDING 0x00000001 /* R---V */ +#define NV_RUNLIST_INTR_0_CTXSW_TIMEOUT_ENG0_RESET 0x00000001 /* -W--V */ +#define NV_RUNLIST_INTR_0_CTXSW_TIMEOUT_ENG1 1:1 /* RWIVF */ +#define NV_RUNLIST_INTR_0_CTXSW_TIMEOUT_ENG1_NOT_PENDING 0x00000000 /* R-I-V */ +#define NV_RUNLIST_INTR_0_CTXSW_TIMEOUT_ENG1_PENDING 0x00000001 /* R---V */ +#define NV_RUNLIST_INTR_0_CTXSW_TIMEOUT_ENG1_RESET 0x00000001 /* -W--V */ +#define NV_RUNLIST_INTR_0_CTXSW_TIMEOUT_ENG2 2:2 /* RWIVF */ +#define NV_RUNLIST_INTR_0_CTXSW_TIMEOUT_ENG2_NOT_PENDING 0x00000000 /* R-I-V */ +#define NV_RUNLIST_INTR_0_CTXSW_TIMEOUT_ENG2_PENDING 0x00000001 /* R---V */ +#define NV_RUNLIST_INTR_0_CTXSW_TIMEOUT_ENG2_RESET 0x00000001 /* -W--V */ +#define NV_RUNLIST_INTR_0_CTXSW_TIMEOUT_ENG(i) (i):(i) /* */ +#define NV_RUNLIST_INTR_0_CTXSW_TIMEOUT_ENG__SIZE_1 3 /* */ +#define NV_RUNLIST_INTR_0_CTXSW_TIMEOUT_ENG_NOT_PENDING 0x00000000 /* */ +#define NV_RUNLIST_INTR_0_CTXSW_TIMEOUT_ENG_PENDING 0x00000001 /* */ +#define NV_RUNLIST_INTR_0_CTXSW_TIMEOUT_ENG_RESET 0x00000001 /* */ +#define NV_RUNLIST_INTR_0_CTXSW_TIMEOUT_GRCE(i) ((i)+1):((i)+1) /* */ +#define NV_RUNLIST_INTR_0_CTXSW_TIMEOUT_GRCE__SIZE_1 2 /* */ +#define NV_RUNLIST_INTR_0_CTXSW_TIMEOUT_GRCE_NOT_PENDING 0x00000000 /* */ +#define NV_RUNLIST_INTR_0_CTXSW_TIMEOUT_GRCE_PENDING 0x00000001 /* */ +#define NV_RUNLIST_INTR_0_CTXSW_TIMEOUT_GRCE_RESET 0x00000001 /* */ +#define NV_RUNLIST_INTR_0_RUNLIST_IDLE 4:4 /* RWIVF */ +#define NV_RUNLIST_INTR_0_RUNLIST_IDLE_NOT_PENDING 0x00000000 /* R-I-V */ +#define NV_RUNLIST_INTR_0_RUNLIST_IDLE_PENDING 0x00000001 /* R---V */ +#define NV_RUNLIST_INTR_0_RUNLIST_IDLE_RESET 0x00000001 /* -W--V */ +#define NV_RUNLIST_INTR_0_RUNLIST_AND_ENG_IDLE 5:5 /* RWXVF */ +#define NV_RUNLIST_INTR_0_RUNLIST_AND_ENG_IDLE_NOT_PENDING 0x00000000 /* R---V */ +#define NV_RUNLIST_INTR_0_RUNLIST_AND_ENG_IDLE_PENDING 0x00000001 /* R---V */ +#define NV_RUNLIST_INTR_0_RUNLIST_AND_ENG_IDLE_RESET 0x00000001 /* -W--V */ +#define NV_RUNLIST_INTR_0_RUNLIST_ACQUIRE 6:6 /* RWXVF */ +#define NV_RUNLIST_INTR_0_RUNLIST_ACQUIRE_NOT_PENDING 0x00000000 /* R---V */ +#define NV_RUNLIST_INTR_0_RUNLIST_ACQUIRE_PENDING 0x00000001 /* R---V */ +#define NV_RUNLIST_INTR_0_RUNLIST_ACQUIRE_RESET 0x00000001 /* -W--V */ +#define NV_RUNLIST_INTR_0_RUNLIST_ACQUIRE_AND_ENG_IDLE 7:7 /* RWXVF */ +#define NV_RUNLIST_INTR_0_RUNLIST_ACQUIRE_AND_ENG_IDLE_NOT_PENDING 0x00000000 /* R---V */ +#define NV_RUNLIST_INTR_0_RUNLIST_ACQUIRE_AND_ENG_IDLE_PENDING 0x00000001 /* R---V */ +#define NV_RUNLIST_INTR_0_RUNLIST_ACQUIRE_AND_ENG_IDLE_RESET 0x00000001 /* -W--V */ +#define NV_RUNLIST_INTR_0_BAD_TSG 12:12 /* RWIVF */ +#define NV_RUNLIST_INTR_0_BAD_TSG_NOT_PENDING 0x00000000 /* R-I-V */ +#define NV_RUNLIST_INTR_0_BAD_TSG_PENDING 0x00000001 /* R---V */ +#define NV_RUNLIST_INTR_0_BAD_TSG_RESET 0x00000001 /* -W--V */ +#define NV_RUNLIST_INTR_0_TSG_PREEMPT_COMPLETE 8:8 /* RWIVF */ +#define NV_RUNLIST_INTR_0_TSG_PREEMPT_COMPLETE_NOT_PENDING 0x00000000 /* R-I-V */ +#define NV_RUNLIST_INTR_0_TSG_PREEMPT_COMPLETE_PENDING 0x00000001 /* R---V */ +#define NV_RUNLIST_INTR_0_TSG_PREEMPT_COMPLETE_RESET 0x00000001 /* -W--V */ +#define NV_RUNLIST_INTR_0_PBDMA0_INTR_TREE_0 16:16 /* R-XVF */ +#define NV_RUNLIST_INTR_0_PBDMA0_INTR_TREE_0_NOT_PENDING 0x00000000 /* R---V */ +#define NV_RUNLIST_INTR_0_PBDMA0_INTR_TREE_0_PENDING 0x00000001 /* R---V */ +#define NV_RUNLIST_INTR_0_PBDMA1_INTR_TREE_0 17:17 /* R-XVF */ +#define NV_RUNLIST_INTR_0_PBDMA1_INTR_TREE_0_NOT_PENDING 0x00000000 /* R---V */ +#define NV_RUNLIST_INTR_0_PBDMA1_INTR_TREE_0_PENDING 0x00000001 /* R---V */ +#define NV_RUNLIST_INTR_0_PBDMA0_INTR_TREE_1 18:18 /* R-XVF */ +#define NV_RUNLIST_INTR_0_PBDMA0_INTR_TREE_1_NOT_PENDING 0x00000000 /* R---V */ +#define NV_RUNLIST_INTR_0_PBDMA0_INTR_TREE_1_PENDING 0x00000001 /* R---V */ +#define NV_RUNLIST_INTR_0_PBDMA1_INTR_TREE_1 19:19 /* R-XVF */ +#define NV_RUNLIST_INTR_0_PBDMA1_INTR_TREE_1_NOT_PENDING 0x00000000 /* R---V */ +#define NV_RUNLIST_INTR_0_PBDMA1_INTR_TREE_1_PENDING 0x00000001 /* R---V */ +#define NV_RUNLIST_INTR_0_PBDMAi_INTR_TREE_j(i,j) (16+(i)+(j)*2):(16+(i)+(j)*2) /* */ +#define NV_RUNLIST_INTR_0_PBDMAi_INTR_TREE_j__SIZE_1 2 /* */ +#define NV_RUNLIST_INTR_0_PBDMAi_INTR_TREE_j__SIZE_2 2 /* */ +#define NV_RUNLIST_INTR_0_PBDMAi_INTR_TREE_j_NOT_PENDING 0x00000000 /* */ +#define NV_RUNLIST_INTR_0_PBDMAi_INTR_TREE_j_PENDING 0x00000001 /* */ +#define NV_RUNLIST_INTR_0_RUNLIST_PREEMPT_COMPLETE 9:9 /* RWIVF */ +#define NV_RUNLIST_INTR_0_RUNLIST_PREEMPT_COMPLETE_NOT_PENDING 0x00000000 /* R-I-V */ +#define NV_RUNLIST_INTR_0_RUNLIST_PREEMPT_COMPLETE_PENDING 0x00000001 /* R---V */ +#define NV_RUNLIST_INTR_0_RUNLIST_PREEMPT_COMPLETE_RESET 0x00000001 /* -W--V */ +#define NV_RUNLIST_INTR_0_RUNLIST_EVENT 9:9 /* */ +#define NV_RUNLIST_INTR_0_MASK_SET 0x110 /* RW-4R */ +#define NV_RUNLIST_INTR_0_MASK_SET_TSG_PREEMPT_COMPLETE 8:8 /* RWIVF */ +#define NV_RUNLIST_INTR_0_MASK_SET_TSG_PREEMPT_COMPLETE_DISABLED 0x00000000 /* RWI-V */ +#define NV_RUNLIST_INTR_0_MASK_SET_TSG_PREEMPT_COMPLETE_ENABLED 0x00000001 /* RW--V */ +#define NV_RUNLIST_INTR_0_MASK_CLEAR 0x118 /* RW-4R */ +#define NV_RUNLIST_INTR_0_MASK_CLEAR_TSG_PREEMPT_COMPLETE 8:8 /* RWIVF */ +#define NV_RUNLIST_INTR_0_MASK_CLEAR_TSG_PREEMPT_COMPLETE_DISABLED 0x00000000 /* RWI-V */ +#define NV_RUNLIST_INTR_0_MASK_CLEAR_TSG_PREEMPT_COMPLETE_ENABLED 0x00000001 /* RW--V */ +#define NV_RUNLIST_INTR_0_EN_SET_TREE(i) (0x120+(i)*8) /* RW-4A */ +#define NV_RUNLIST_INTR_0_EN_SET_TREE__SIZE_1 2 /* */ +#define NV_RUNLIST_INTR_0_EN_SET_TREE__PRIV_LEVEL_MASK "NV_RUNLIST_INTR_PRIV_LEVEL_MASK" /* */ +#define NV_RUNLIST_INTR_0_EN_SET_TREE_CTXSW_TIMEOUT_ENG0 0:0 /* RWIVF */ +#define NV_RUNLIST_INTR_0_EN_SET_TREE_CTXSW_TIMEOUT_ENG0_DISABLED 0x00000000 /* RWI-V */ +#define NV_RUNLIST_INTR_0_EN_SET_TREE_CTXSW_TIMEOUT_ENG0_ENABLED 0x00000001 /* RW--V */ +#define NV_RUNLIST_INTR_0_EN_SET_TREE_CTXSW_TIMEOUT_ENG1 1:1 /* RWIVF */ +#define NV_RUNLIST_INTR_0_EN_SET_TREE_CTXSW_TIMEOUT_ENG1_DISABLED 0x00000000 /* RWI-V */ +#define NV_RUNLIST_INTR_0_EN_SET_TREE_CTXSW_TIMEOUT_ENG1_ENABLED 0x00000001 /* RW--V */ +#define NV_RUNLIST_INTR_0_EN_SET_TREE_CTXSW_TIMEOUT_ENG2 2:2 /* RWIVF */ +#define NV_RUNLIST_INTR_0_EN_SET_TREE_CTXSW_TIMEOUT_ENG2_DISABLED 0x00000000 /* RWI-V */ +#define NV_RUNLIST_INTR_0_EN_SET_TREE_CTXSW_TIMEOUT_ENG2_ENABLED 0x00000001 /* RW--V */ +#define NV_RUNLIST_INTR_0_EN_SET_TREE_CTXSW_TIMEOUT_ENG(i) (i):(i) /* */ +#define NV_RUNLIST_INTR_0_EN_SET_TREE_CTXSW_TIMEOUT_ENG__SIZE_1 3 /* */ +#define NV_RUNLIST_INTR_0_EN_SET_TREE_CTXSW_TIMEOUT_ENG_DISABLED 0x00000000 /* */ +#define NV_RUNLIST_INTR_0_EN_SET_TREE_CTXSW_TIMEOUT_ENG_ENABLED 0x00000001 /* */ +#define NV_RUNLIST_INTR_0_EN_SET_TREE_CTXSW_TIMEOUT_GRCE(i) ((i)+1):((i)+1) /* */ +#define NV_RUNLIST_INTR_0_EN_SET_TREE_CTXSW_TIMEOUT_GRCE__SIZE_1 2 /* */ +#define NV_RUNLIST_INTR_0_EN_SET_TREE_CTXSW_TIMEOUT_GRCE_DISABLED 0x00000000 /* */ +#define NV_RUNLIST_INTR_0_EN_SET_TREE_CTXSW_TIMEOUT_GRCE_ENABLED 0x00000001 /* */ +#define NV_RUNLIST_INTR_0_EN_SET_TREE_RUNLIST_IDLE 4:4 /* RWIVF */ +#define NV_RUNLIST_INTR_0_EN_SET_TREE_RUNLIST_IDLE_DISABLED 0x00000000 /* RWI-V */ +#define NV_RUNLIST_INTR_0_EN_SET_TREE_RUNLIST_IDLE_ENABLED 0x00000001 /* RW--V */ +#define NV_RUNLIST_INTR_0_EN_SET_TREE_RUNLIST_AND_ENG_IDLE 5:5 /* RWIVF */ +#define NV_RUNLIST_INTR_0_EN_SET_TREE_RUNLIST_AND_ENG_IDLE_DISABLED 0x00000000 /* RWI-V */ +#define NV_RUNLIST_INTR_0_EN_SET_TREE_RUNLIST_AND_ENG_IDLE_ENABLED 0x00000001 /* RW--V */ +#define NV_RUNLIST_INTR_0_EN_SET_TREE_RUNLIST_ACQUIRE 6:6 /* RWIVF */ +#define NV_RUNLIST_INTR_0_EN_SET_TREE_RUNLIST_ACQUIRE_DISABLED 0x00000000 /* RWI-V */ +#define NV_RUNLIST_INTR_0_EN_SET_TREE_RUNLIST_ACQUIRE_ENABLED 0x00000001 /* RW--V */ +#define NV_RUNLIST_INTR_0_EN_SET_TREE_RUNLIST_ACQUIRE_AND_ENG_IDLE 7:7 /* RWIVF */ +#define NV_RUNLIST_INTR_0_EN_SET_TREE_RUNLIST_ACQUIRE_AND_ENG_IDLE_DISABLED 0x00000000 /* RWI-V */ +#define NV_RUNLIST_INTR_0_EN_SET_TREE_RUNLIST_ACQUIRE_AND_ENG_IDLE_ENABLED 0x00000001 /* RW--V */ +#define NV_RUNLIST_INTR_0_EN_SET_TREE_TSG_PREEMPT_COMPLETE 8:8 /* RWIVF */ +#define NV_RUNLIST_INTR_0_EN_SET_TREE_TSG_PREEMPT_COMPLETE_DISABLED 0x00000000 /* RWI-V */ +#define NV_RUNLIST_INTR_0_EN_SET_TREE_TSG_PREEMPT_COMPLETE_ENABLED 0x00000001 /* RW--V */ +#define NV_RUNLIST_INTR_0_EN_SET_TREE_RUNLIST_PREEMPT_COMPLETE 9:9 /* RWIVF */ +#define NV_RUNLIST_INTR_0_EN_SET_TREE_RUNLIST_PREEMPT_COMPLETE_DISABLED 0x00000000 /* RWI-V */ +#define NV_RUNLIST_INTR_0_EN_SET_TREE_RUNLIST_PREEMPT_COMPLETE_ENABLED 0x00000001 /* RW--V */ +#define NV_RUNLIST_INTR_0_EN_SET_TREE_BAD_TSG 12:12 /* RWIVF */ +#define NV_RUNLIST_INTR_0_EN_SET_TREE_BAD_TSG_DISABLED 0x00000000 /* RWI-V */ +#define NV_RUNLIST_INTR_0_EN_SET_TREE_BAD_TSG_ENABLED 0x00000001 /* RW--V */ +#define NV_RUNLIST_INTR_0_EN_SET_TREE_PBDMA0_INTR_TREE_0 16:16 /* RWIVF */ +#define NV_RUNLIST_INTR_0_EN_SET_TREE_PBDMA0_INTR_TREE_0_DISABLED 0x00000000 /* RWI-V */ +#define NV_RUNLIST_INTR_0_EN_SET_TREE_PBDMA0_INTR_TREE_0_ENABLED 0x00000001 /* RW--V */ +#define NV_RUNLIST_INTR_0_EN_SET_TREE_PBDMA1_INTR_TREE_0 17:17 /* RWIVF */ +#define NV_RUNLIST_INTR_0_EN_SET_TREE_PBDMA1_INTR_TREE_0_DISABLED 0x00000000 /* RWI-V */ +#define NV_RUNLIST_INTR_0_EN_SET_TREE_PBDMA1_INTR_TREE_0_ENABLED 0x00000001 /* RW--V */ +#define NV_RUNLIST_INTR_0_EN_SET_TREE_PBDMA0_INTR_TREE_1 18:18 /* RWIVF */ +#define NV_RUNLIST_INTR_0_EN_SET_TREE_PBDMA0_INTR_TREE_1_DISABLED 0x00000000 /* RWI-V */ +#define NV_RUNLIST_INTR_0_EN_SET_TREE_PBDMA0_INTR_TREE_1_ENABLED 0x00000001 /* RW--V */ +#define NV_RUNLIST_INTR_0_EN_SET_TREE_PBDMA1_INTR_TREE_1 19:19 /* RWIVF */ +#define NV_RUNLIST_INTR_0_EN_SET_TREE_PBDMA1_INTR_TREE_1_DISABLED 0x00000000 /* RWI-V */ +#define NV_RUNLIST_INTR_0_EN_SET_TREE_PBDMA1_INTR_TREE_1_ENABLED 0x00000001 /* RW--V */ +#define NV_RUNLIST_INTR_0_EN_SET_TREE_PBDMAi_INTR_TREE_j(i,j) (16+(i)+(j)*2):(16+(i)+(j)*2) /* */ +#define NV_RUNLIST_INTR_0_EN_SET_TREE_PBDMAi_INTR_TREE_j__SIZE_1 2 /* */ +#define NV_RUNLIST_INTR_0_EN_SET_TREE_PBDMAi_INTR_TREE_j__SIZE_2 2 /* */ +#define NV_RUNLIST_INTR_0_EN_SET_TREE_PBDMAi_INTR_TREE_j_DISABLED 0x00000000 /* */ +#define NV_RUNLIST_INTR_0_EN_SET_TREE_PBDMAi_INTR_TREE_j_ENABLED 0x00000001 /* */ +#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE(i) (0x140+(i)*8) /* RW-4A */ +#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE__SIZE_1 2 /* */ +#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE__PRIV_LEVEL_MASK "NV_RUNLIST_INTR_PRIV_LEVEL_MASK" /* */ +#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_CTXSW_TIMEOUT_ENG0 0:0 /* RWIVF */ +#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_CTXSW_TIMEOUT_ENG0_DISABLED 0x00000000 /* RWI-V */ +#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_CTXSW_TIMEOUT_ENG0_ENABLED 0x00000001 /* RW--V */ +#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_CTXSW_TIMEOUT_ENG1 1:1 /* RWIVF */ +#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_CTXSW_TIMEOUT_ENG1_DISABLED 0x00000000 /* RWI-V */ +#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_CTXSW_TIMEOUT_ENG1_ENABLED 0x00000001 /* RW--V */ +#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_CTXSW_TIMEOUT_ENG2 2:2 /* RWIVF */ +#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_CTXSW_TIMEOUT_ENG2_DISABLED 0x00000000 /* RWI-V */ +#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_CTXSW_TIMEOUT_ENG2_ENABLED 0x00000001 /* RW--V */ +#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_CTXSW_TIMEOUT_ENG(i) (i):(i) /* */ +#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_CTXSW_TIMEOUT_ENG__SIZE_1 3 /* */ +#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_CTXSW_TIMEOUT_ENG_DISABLED 0x00000000 /* */ +#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_CTXSW_TIMEOUT_ENG_ENABLED 0x00000001 /* */ +#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_CTXSW_TIMEOUT_GRCE(i) ((i)+1):((i)+1) /* */ +#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_CTXSW_TIMEOUT_GRCE__SIZE_1 2 /* */ +#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_CTXSW_TIMEOUT_GRCE_DISABLED 0x00000000 /* */ +#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_CTXSW_TIMEOUT_GRCE_ENABLED 0x00000001 /* */ +#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_RUNLIST_IDLE 4:4 /* RWIVF */ +#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_RUNLIST_IDLE_DISABLED 0x00000000 /* RWI-V */ +#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_RUNLIST_IDLE_ENABLED 0x00000001 /* RW--V */ +#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_RUNLIST_AND_ENG_IDLE 5:5 /* RWIVF */ +#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_RUNLIST_AND_ENG_IDLE_DISABLED 0x00000000 /* RWI-V */ +#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_RUNLIST_AND_ENG_IDLE_ENABLED 0x00000001 /* RW--V */ +#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_RUNLIST_ACQUIRE 6:6 /* RWIVF */ +#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_RUNLIST_ACQUIRE_DISABLED 0x00000000 /* RWI-V */ +#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_RUNLIST_ACQUIRE_ENABLED 0x00000001 /* RW--V */ +#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_RUNLIST_ACQUIRE_AND_ENG_IDLE 7:7 /* RWIVF */ +#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_RUNLIST_ACQUIRE_AND_ENG_IDLE_DISABLED 0x00000000 /* RWI-V */ +#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_RUNLIST_ACQUIRE_AND_ENG_IDLE_ENABLED 0x00000001 /* RW--V */ +#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_TSG_PREEMPT_COMPLETE 8:8 /* RWIVF */ +#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_TSG_PREEMPT_COMPLETE_DISABLED 0x00000000 /* RWI-V */ +#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_TSG_PREEMPT_COMPLETE_ENABLED 0x00000001 /* RW--V */ +#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_RUNLIST_PREEMPT_COMPLETE 9:9 /* RWIVF */ +#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_RUNLIST_PREEMPT_COMPLETE_DISABLED 0x00000000 /* RWI-V */ +#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_RUNLIST_PREEMPT_COMPLETE_ENABLED 0x00000001 /* RW--V */ +#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_BAD_TSG 12:12 /* RWIVF */ +#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_BAD_TSG_DISABLED 0x00000000 /* RWI-V */ +#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_BAD_TSG_ENABLED 0x00000001 /* RW--V */ +#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_PBDMA0_INTR_TREE_0 16:16 /* RWIVF */ +#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_PBDMA0_INTR_TREE_0_DISABLED 0x00000000 /* RWI-V */ +#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_PBDMA0_INTR_TREE_0_ENABLED 0x00000001 /* RW--V */ +#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_PBDMA1_INTR_TREE_0 17:17 /* RWIVF */ +#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_PBDMA1_INTR_TREE_0_DISABLED 0x00000000 /* RWI-V */ +#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_PBDMA1_INTR_TREE_0_ENABLED 0x00000001 /* RW--V */ +#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_PBDMA0_INTR_TREE_1 18:18 /* RWIVF */ +#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_PBDMA0_INTR_TREE_1_DISABLED 0x00000000 /* RWI-V */ +#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_PBDMA0_INTR_TREE_1_ENABLED 0x00000001 /* RW--V */ +#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_PBDMA1_INTR_TREE_1 19:19 /* RWIVF */ +#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_PBDMA1_INTR_TREE_1_DISABLED 0x00000000 /* RWI-V */ +#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_PBDMA1_INTR_TREE_1_ENABLED 0x00000001 /* RW--V */ +#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_PBDMAi_INTR_TREE_j(i,j) (16+(i)+(j)*2):(16+(i)+(j)*2) /* */ +#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_PBDMAi_INTR_TREE_j__SIZE_1 2 /* */ +#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_PBDMAi_INTR_TREE_j__SIZE_2 2 /* */ +#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_PBDMAi_INTR_TREE_j_DISABLED 0x00000000 /* */ +#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_PBDMAi_INTR_TREE_j_ENABLED 0x00000001 /* */ +#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_INFO(i) (0x224+(i)*64) /* R--4A */ +#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_INFO__SIZE_1 3 /* */ +#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_INFO_PREV_TSGID 13:0 /* R-IUF */ +#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_INFO_PREV_TSGID_DEFAULT 0x00000000 /* R-I-V */ +#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_INFO_CTXSW_STATE 15:14 /* R-IUF */ +#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_INFO_CTXSW_STATE_LOAD 0x00000001 /* R-I-V */ +#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_INFO_CTXSW_STATE_SAVE 0x00000002 /* R---V */ +#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_INFO_CTXSW_STATE_SWITCH 0x00000003 /* R---V */ +#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_INFO_NEXT_TSGID 29:16 /* R-IUF */ +#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_INFO_NEXT_TSGID_DEFAULT 0x00000000 /* R-I-V */ +#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_INFO_STATUS 31:30 /* R-IUF */ +#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_INFO_STATUS_AWAITING_ACK 0x00000000 /* R-I-V */ +#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_INFO_STATUS_ENG_WAS_RESET 0x00000001 /* R---V */ +#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_INFO_STATUS_ACK_RECEIVED 0x00000002 /* R---V */ +#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_INFO_STATUS_DROPPED_TIMEOUT 0x00000003 /* R---V */ +#define NV_RUNLIST_INFO 0x108 /* R--4R */ +#define NV_RUNLIST_INFO_RUNLIST_IDLE_INTR_ARM 0:0 /* R-IUF */ +#define NV_RUNLIST_INFO_RUNLIST_IDLE_INTR_ARM_UNARMED 0x00000000 /* R-I-V */ +#define NV_RUNLIST_INFO_RUNLIST_IDLE_INTR_ARM_ARMED 0x00000001 /* R---V */ +#define NV_RUNLIST_INFO_RUNLIST_ACQUIRE_INTR_ARM 1:1 /* R-IUF */ +#define NV_RUNLIST_INFO_RUNLIST_ACQUIRE_INTR_ARM_UNARMED 0x00000000 /* R-I-V */ +#define NV_RUNLIST_INFO_RUNLIST_ACQUIRE_INTR_ARM_ARMED 0x00000001 /* R---V */ +#define NV_RUNLIST_INFO_RUNLIST_AND_ENG_IDLE_INTR_ARM 4:4 /* R-IUF */ +#define NV_RUNLIST_INFO_RUNLIST_AND_ENG_IDLE_INTR_ARM_UNARMED 0x00000000 /* R-I-V */ +#define NV_RUNLIST_INFO_RUNLIST_AND_ENG_IDLE_INTR_ARM_ARMED 0x00000001 /* R---V */ +#define NV_RUNLIST_INFO_RUNLIST_ACQUIRE_AND_ENG_IDLE_INTR_ARM 5:5 /* R-IUF */ +#define NV_RUNLIST_INFO_RUNLIST_ACQUIRE_AND_ENG_IDLE_INTR_ARM_UNARMED 0x00000000 /* R-I-V */ +#define NV_RUNLIST_INFO_RUNLIST_ACQUIRE_AND_ENG_IDLE_INTR_ARM_ARMED 0x00000001 /* R---V */ +#define NV_RUNLIST_INFO_ENG_IDLE 8:8 /* R-IUF */ +#define NV_RUNLIST_INFO_ENG_IDLE_FALSE 0x00000000 /* R---V */ +#define NV_RUNLIST_INFO_ENG_IDLE_TRUE 0x00000001 /* R-I-V */ +#define NV_RUNLIST_INFO_RUNLIST_IDLE 9:9 /* R-IUF */ +#define NV_RUNLIST_INFO_RUNLIST_IDLE_FALSE 0x00000000 /* R---V */ +#define NV_RUNLIST_INFO_RUNLIST_IDLE_TRUE 0x00000001 /* R-I-V */ +#define NV_RUNLIST_INFO_RUNLIST_FETCH_STATUS 10:10 /* R-IVF */ +#define NV_RUNLIST_INFO_RUNLIST_FETCH_STATUS_IDLE 0x00000000 /* R-I-V */ +#define NV_RUNLIST_INFO_RUNLIST_FETCH_STATUS_BUSY 0x00000001 /* R---V */ +#define NV_RUNLIST_INFO_ACQUIRE_STILL_PENDING 12:12 /* R-IUF */ +#define NV_RUNLIST_INFO_ACQUIRE_STILL_PENDING_FALSE 0x00000000 /* R-I-V */ +#define NV_RUNLIST_INFO_ACQUIRE_STILL_PENDING_TRUE 0x00000001 /* R---V */ +#define NV_RUNLIST_INFO_RUNLIST_FETCH_NACKED 13:13 /* R-IUF */ +#define NV_RUNLIST_INFO_RUNLIST_FETCH_NACKED_FALSE 0x00000000 /* R-I-V */ +#define NV_RUNLIST_INFO_RUNLIST_FETCH_NACKED_TRUE 0x00000001 /* R---V */ +#define NV_RUNLIST_INTR_BAD_TSG 0x174 /* R--4R */ +#define NV_RUNLIST_INTR_BAD_TSG_CODE 3:0 /* R-IVF */ +#define NV_RUNLIST_INTR_BAD_TSG_CODE_NO_ERROR 0x00000000 /* R-I-V */ +#define NV_RUNLIST_INTR_BAD_TSG_CODE_ZERO_LENGTH_TSG 0x00000001 /* R---V */ +#define NV_RUNLIST_INTR_BAD_TSG_CODE_MAX_LENGTH_EXCEEDED 0x00000002 /* R---V */ +#define NV_RUNLIST_INTR_BAD_TSG_CODE_RUNLIST_OVERFLOW 0x00000003 /* R---V */ +#define NV_RUNLIST_INTR_BAD_TSG_CODE_EXPECTED_A_CHID_ENTRY 0x00000004 /* R---V */ +#define NV_RUNLIST_INTR_BAD_TSG_CODE_EXPECTED_A_TSG_HEADER 0x00000005 /* R---V */ +#define NV_RUNLIST_INTR_BAD_TSG_CODE_INVALID_RUNQUEUE 0x00000006 /* R---V */ +#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_CONFIG(i) (0x220+(i)*64) /* RW-4A */ +#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_CONFIG__SIZE_1 3 /* */ +#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_CONFIG_PERIOD 30:0 /* RWIVF */ +#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_CONFIG_PERIOD_INIT 0x003fffff /* RWI-V */ +#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_CONFIG_PERIOD_MAX 0x7fffffff /* RW--V */ +#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_CONFIG_DETECTION 31:31 /* RWIVF */ +#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_CONFIG_DETECTION_DISABLED 0x00000000 /* RW--V */ +#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_CONFIG_DETECTION_ENABLED 0x00000001 /* RWI-V */ +#define NV_RUNLIST_BLKCG 0x050 /* RW-4R */ +#define NV_RUNLIST_BLKCG_IDLE_CG_DLY_CNT 5:0 /* RWIVF */ +#define NV_RUNLIST_BLKCG_IDLE_CG_DLY_CNT_INIT 0x00000000 /* RWI-V */ +#define NV_RUNLIST_BLKCG_IDLE_CG_DLY_CNT__PROD 0x00000002 /* RW--V */ +#define NV_RUNLIST_BLKCG_IDLE_CG_EN 6:6 /* RWIVF */ +#define NV_RUNLIST_BLKCG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */ +#define NV_RUNLIST_BLKCG_IDLE_CG_EN_DISABLED 0x00000000 /* RWI-V */ +#define NV_RUNLIST_BLKCG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */ +#define NV_RUNLIST_BLKCG_STATE_CG_EN 7:7 /* */ +#define NV_RUNLIST_BLKCG_STATE_CG_EN_ENABLED 0x00000001 /* */ +#define NV_RUNLIST_BLKCG_STATE_CG_EN_DISABLED 0x00000000 /* */ +#define NV_RUNLIST_BLKCG_STATE_CG_EN__PROD 0x00000000 /* */ +#define NV_RUNLIST_BLKCG_STALL_CG_DLY_CNT 13:8 /* */ +#define NV_RUNLIST_BLKCG_STALL_CG_DLY_CNT_INIT 0x00000000 /* */ +#define NV_RUNLIST_BLKCG_STALL_CG_DLY_CNT__PROD 0x00000002 /* */ +#define NV_RUNLIST_BLKCG_STALL_CG_EN 14:14 /* RWIVF */ +#define NV_RUNLIST_BLKCG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */ +#define NV_RUNLIST_BLKCG_STALL_CG_EN_DISABLED 0x00000000 /* RWI-V */ +#define NV_RUNLIST_BLKCG_STALL_CG_EN__PROD 0x00000001 /* RW--V */ +#define NV_RUNLIST_BLKCG_QUIESCENT_CG_EN 15:15 /* */ +#define NV_RUNLIST_BLKCG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */ +#define NV_RUNLIST_BLKCG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */ +#define NV_RUNLIST_BLKCG_QUIESCENT_CG_EN__PROD 0x00000001 /* */ +#define NV_RUNLIST_BLKCG_WAKEUP_DLY_CNT 19:16 /* RWIVF */ +#define NV_RUNLIST_BLKCG_WAKEUP_DLY_CNT_INIT 0x00000000 /* RWI-V */ +#define NV_RUNLIST_BLKCG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */ +#define NV_RUNLIST_BLKCG_THROT_CLK_CNT 23:20 /* */ +#define NV_RUNLIST_BLKCG_THROT_CLK_CNT_INIT 0x0000000f /* */ +#define NV_RUNLIST_BLKCG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */ +#define NV_RUNLIST_BLKCG_THROT_CLK_CNT__PROD 0x00000000 /* */ +#define NV_RUNLIST_BLKCG_DI_DT_SKEW_VAL 27:24 /* */ +#define NV_RUNLIST_BLKCG_DI_DT_SKEW_VAL_INIT 0x00000000 /* */ +#define NV_RUNLIST_BLKCG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */ +#define NV_RUNLIST_BLKCG_THROT_CLK_EN 28:28 /* */ +#define NV_RUNLIST_BLKCG_THROT_CLK_EN_ENABLED 0x00000001 /* */ +#define NV_RUNLIST_BLKCG_THROT_CLK_EN_DISABLED 0x00000000 /* */ +#define NV_RUNLIST_BLKCG_THROT_CLK_EN__PROD 0x00000000 /* */ +#define NV_RUNLIST_BLKCG_THROT_CLK_SW_OVER 29:29 /* */ +#define NV_RUNLIST_BLKCG_THROT_CLK_SW_OVER_EN 0x00000001 /* */ +#define NV_RUNLIST_BLKCG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */ +#define NV_RUNLIST_BLKCG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */ +#define NV_RUNLIST_BLKCG_PAUSE_CG_EN 30:30 /* */ +#define NV_RUNLIST_BLKCG_PAUSE_CG_EN_ENABLED 0x00000001 /* */ +#define NV_RUNLIST_BLKCG_PAUSE_CG_EN_DISABLED 0x00000000 /* */ +#define NV_RUNLIST_BLKCG_PAUSE_CG_EN__PROD 0x00000000 /* */ +#define NV_RUNLIST_BLKCG_HALT_CG_EN 31:31 /* */ +#define NV_RUNLIST_BLKCG_HALT_CG_EN_ENABLED 0x00000001 /* */ +#define NV_RUNLIST_BLKCG_HALT_CG_EN_DISABLED 0x00000000 /* */ +#define NV_RUNLIST_BLKCG_HALT_CG_EN__PROD 0x00000000 /* */ +#define NV_RUNLIST_BLKCG1 0x054 /* RW-4R */ +#define NV_RUNLIST_BLKCG1_MONITOR_CG_EN 0:0 /* RWIVF */ +#define NV_RUNLIST_BLKCG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */ +#define NV_RUNLIST_BLKCG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWI-V */ +#define NV_RUNLIST_BLKCG1_SLCG 16:1 /* */ +#define NV_RUNLIST_BLKCG1_SLCG_ENABLED 0x00000000 /* */ +#define NV_RUNLIST_BLKCG1_SLCG_DISABLED 0x0000FFFF /* */ +#define NV_RUNLIST_BLKCG1_SLCG__PROD 0x00000001 /* */ +#define NV_RUNLIST_BLKCG1_SLCG_RLP 1:1 /* RWIVF */ +#define NV_RUNLIST_BLKCG1_SLCG_RLP_ENABLED 0x00000000 /* RW--V */ +#define NV_RUNLIST_BLKCG1_SLCG_RLP_DISABLED 0x00000001 /* RWI-V */ +#define NV_RUNLIST_BLKCG1_SLCG_RLP__PROD 0x00000001 /* RW--V */ +#define NV_RUNLIST_BLKCG1_SLCG_EVH 3:3 /* RWIVF */ +#define NV_RUNLIST_BLKCG1_SLCG_EVH_ENABLED 0x00000000 /* RW--V */ +#define NV_RUNLIST_BLKCG1_SLCG_EVH_DISABLED 0x00000001 /* RWI-V */ +#define NV_RUNLIST_BLKCG1_SLCG_EVH__PROD 0x00000000 /* RW--V */ +#define NV_RUNLIST_BLKCG1_SLCG_EISM 7:7 /* RWIVF */ +#define NV_RUNLIST_BLKCG1_SLCG_EISM_ENABLED 0x00000000 /* RW--V */ +#define NV_RUNLIST_BLKCG1_SLCG_EISM_DISABLED 0x00000001 /* RWI-V */ +#define NV_RUNLIST_BLKCG1_SLCG_EISM__PROD 0x00000000 /* RW--V */ +#define NV_RUNLIST_BLKCG1_SLCG_LB 8:8 /* RWIVF */ +#define NV_RUNLIST_BLKCG1_SLCG_LB_ENABLED 0x00000000 /* RW--V */ +#define NV_RUNLIST_BLKCG1_SLCG_LB_DISABLED 0x00000001 /* RWI-V */ +#define NV_RUNLIST_BLKCG1_SLCG_LB__PROD 0x00000000 /* RW--V */ +#define NV_RUNLIST_BLKCG1_SLCG_PBDMA_CTL 9:9 /* RWIVF */ +#define NV_RUNLIST_BLKCG1_SLCG_PBDMA_CTL_ENABLED 0x00000000 /* RW--V */ +#define NV_RUNLIST_BLKCG1_SLCG_PBDMA_CTL_DISABLED 0x00000001 /* RWI-V */ +#define NV_RUNLIST_BLKCG1_SLCG_PBDMA_CTL__PROD 0x00000000 /* RW--V */ +#define NV_RUNLIST_BLKCG1_SLCG_PBDMA_GP 10:10 /* RWIVF */ +#define NV_RUNLIST_BLKCG1_SLCG_PBDMA_GP_ENABLED 0x00000000 /* RW--V */ +#define NV_RUNLIST_BLKCG1_SLCG_PBDMA_GP_DISABLED 0x00000001 /* RWI-V */ +#define NV_RUNLIST_BLKCG1_SLCG_PBDMA_GP__PROD 0x00000000 /* RW--V */ +#define NV_RUNLIST_BLKCG1_SLCG_PBDMA_PB 11:11 /* RWIVF */ +#define NV_RUNLIST_BLKCG1_SLCG_PBDMA_PB_ENABLED 0x00000000 /* RW--V */ +#define NV_RUNLIST_BLKCG1_SLCG_PBDMA_PB_DISABLED 0x00000001 /* RWI-V */ +#define NV_RUNLIST_BLKCG1_SLCG_PBDMA_PB__PROD 0x00000000 /* RW--V */ +#define NV_RUNLIST_BLKCG1_SLCG_PRI 13:13 /* RWIVF */ +#define NV_RUNLIST_BLKCG1_SLCG_PRI_ENABLED 0x00000000 /* RW--V */ +#define NV_RUNLIST_BLKCG1_SLCG_PRI_DISABLED 0x00000001 /* RWI-V */ +#define NV_RUNLIST_BLKCG1_SLCG_PRI__PROD 0x00000000 /* RW--V */ +#define NV_RUNLIST_BLKCG1_SLCG_CHSW 14:14 /* RWIVF */ +#define NV_RUNLIST_BLKCG1_SLCG_CHSW_ENABLED 0x00000000 /* RW--V */ +#define NV_RUNLIST_BLKCG1_SLCG_CHSW_DISABLED 0x00000001 /* RWI-V */ +#define NV_RUNLIST_BLKCG1_SLCG_CHSW__PROD 0x00000000 /* RW--V */ +#define NV_RUNLIST_BLKCG1_SLCG_XBAR 15:15 /* RWIVF */ +#define NV_RUNLIST_BLKCG1_SLCG_XBAR_ENABLED 0x00000000 /* RW--V */ +#define NV_RUNLIST_BLKCG1_SLCG_XBAR_DISABLED 0x00000001 /* RWI-V */ +#define NV_RUNLIST_BLKCG1_SLCG_XBAR__PROD 0x00000000 /* RW--V */ +#define NV_RUNLIST_SLCG_MISC 0x05C /* RW-4R */ +#define NV_RUNLIST_SLCG_MISC_EXTRA_BUSY_CLKS 3:0 /* RWIVF */ +#define NV_RUNLIST_SLCG_MISC_EXTRA_BUSY_CLKS_ZERO 0x00000000 /* RWI-V */ +#define NV_RUNLIST_INTERNAL_DOORBELL 0x090 /* -W-4R */ +#define NV_RUNLIST_INTERNAL_DOORBELL_CHID 11:0 /* */ +#define NV_RUNLIST_INTERNAL_DOORBELL_CHID_HW 10:0 /* -WXUF */ +#define NV_RUNLIST_INTERNAL_DOORBELL_GFID 21:16 /* -WXUF */ +#define NV_RUNLIST_SCHED_DISABLE 0x094 /* RW-4R */ +#define NV_RUNLIST_SCHED_DISABLE_RUNLIST 0:0 /* RWIVF */ +#define NV_RUNLIST_SCHED_DISABLE_RUNLIST_ENABLED 0x00000000 /* RWI-V */ +#define NV_RUNLIST_SCHED_DISABLE_RUNLIST_DISABLED 0x00000001 /* RW--V */ +#define NV_RUNLIST_SCHED_DISABLE_RUNLIST_FALSE 0x00000000 /* */ +#define NV_RUNLIST_SCHED_DISABLE_RUNLIST_TRUE 0x00000001 /* */ +#define NV_RUNLIST_PREEMPT 0x098 /* RW-4R */ +#define NV_RUNLIST_PREEMPT_ID 11:0 /* */ +#define NV_RUNLIST_PREEMPT_ID_HW 10:0 /* RWIUF */ +#define NV_RUNLIST_PREEMPT_ID_HW_NULL 0x00000000 /* RWI-V */ +#define NV_RUNLIST_PREEMPT_TSG_PREEMPT_PENDING 20:20 /* R-IVF */ +#define NV_RUNLIST_PREEMPT_TSG_PREEMPT_PENDING_FALSE 0x00000000 /* R-I-V */ +#define NV_RUNLIST_PREEMPT_TSG_PREEMPT_PENDING_TRUE 0x00000001 /* R---V */ +#define NV_RUNLIST_PREEMPT_RUNLIST_PREEMPT_PENDING 21:21 /* R-IVF */ +#define NV_RUNLIST_PREEMPT_RUNLIST_PREEMPT_PENDING_FALSE 0x00000000 /* R-I-V */ +#define NV_RUNLIST_PREEMPT_RUNLIST_PREEMPT_PENDING_TRUE 0x00000001 /* R---V */ +#define NV_RUNLIST_PREEMPT_TYPE 25:24 /* RWIVF */ +#define NV_RUNLIST_PREEMPT_TYPE_RUNLIST 0x00000000 /* RWI-V */ +#define NV_RUNLIST_PREEMPT_TYPE_TSG 0x00000001 /* RW--V */ +#define NV_RUNLIST_ENGINE_STATUS0(i) (0x200+(i)*64) /* R--4A */ +#define NV_RUNLIST_ENGINE_STATUS0__SIZE_1 3 /* */ +#define NV_RUNLIST_ENGINE_STATUS0_TSGID 11:0 /* */ +#define NV_RUNLIST_ENGINE_STATUS0_TSGID_HW 10:0 /* R-XUF */ +#define NV_RUNLIST_ENGINE_STATUS0_CTX_STATUS 15:13 /* R-IVF */ +#define NV_RUNLIST_ENGINE_STATUS0_CTX_STATUS_INVALID 0x00000000 /* R-I-V */ +#define NV_RUNLIST_ENGINE_STATUS0_CTX_STATUS_VALID 0x00000001 /* R---V */ +#define NV_RUNLIST_ENGINE_STATUS0_CTX_STATUS_CTXSW_SAVE 0x00000005 /* R---V */ +#define NV_RUNLIST_ENGINE_STATUS0_CTX_STATUS_CTXSW_LOAD 0x00000006 /* R---V */ +#define NV_RUNLIST_ENGINE_STATUS0_CTX_STATUS_CTXSW_SWITCH 0x00000007 /* R---V */ +#define NV_RUNLIST_ENGINE_STATUS0_CTX 13:13 /* */ +#define NV_RUNLIST_ENGINE_STATUS0_CTX_INVALID 0x00000000 /* */ +#define NV_RUNLIST_ENGINE_STATUS0_CTX_VALID 0x00000001 /* */ +#define NV_RUNLIST_ENGINE_STATUS0_CTXLOAD 14:14 /* */ +#define NV_RUNLIST_ENGINE_STATUS0_CTXLOAD_NOT_IN_PROGRESS 0x00000000 /* */ +#define NV_RUNLIST_ENGINE_STATUS0_CTXLOAD_IN_PROGRESS 0x00000001 /* */ +#define NV_RUNLIST_ENGINE_STATUS0_CTXSW 15:15 /* */ +#define NV_RUNLIST_ENGINE_STATUS0_CTXSW_NOT_IN_PROGRESS 0x00000000 /* */ +#define NV_RUNLIST_ENGINE_STATUS0_CTXSW_IN_PROGRESS 0x00000001 /* */ +#define NV_RUNLIST_ENGINE_STATUS0_NEXT_TSGID 27:16 /* */ +#define NV_RUNLIST_ENGINE_STATUS0_NEXT_TSGID_HW 26:16 /* R-XUF */ +#define NV_RUNLIST_ENGINE_STATUS0_ENG_RELOAD 29:29 /* R-IVF */ +#define NV_RUNLIST_ENGINE_STATUS0_ENG_RELOAD_FALSE 0x00000000 /* R-I-V */ +#define NV_RUNLIST_ENGINE_STATUS0_ENG_RELOAD_TRUE 0x00000001 /* R---V */ +#define NV_RUNLIST_ENGINE_STATUS0_FAULTED 30:30 /* R-IVF */ +#define NV_RUNLIST_ENGINE_STATUS0_FAULTED_FALSE 0x00000000 /* R-I-V */ +#define NV_RUNLIST_ENGINE_STATUS0_FAULTED_TRUE 0x00000001 /* R---V */ +#define NV_RUNLIST_ENGINE_STATUS0_ENGINE 31:31 /* R-IVF */ +#define NV_RUNLIST_ENGINE_STATUS0_ENGINE_IDLE 0x00000000 /* R-I-V */ +#define NV_RUNLIST_ENGINE_STATUS0_ENGINE_BUSY 0x00000001 /* R---V */ +#define NV_RUNLIST_ENGINE_STATUS1(i) (0x204+(i)*64) /* R--4A */ +#define NV_RUNLIST_ENGINE_STATUS1__SIZE_1 3 /* */ +#define NV_RUNLIST_ENGINE_STATUS1_GFID 5:0 /* R-XVF */ +#define NV_RUNLIST_ENGINE_STATUS1_NEXT_GFID 13:8 /* R-XVF */ +#define NV_RUNLIST_ENGINE_STATUS1_INTR_ID 20:16 /* R-XVF */ +#define NV_RUNLIST_ENGINE_STATUS1_GFID_VALID 30:30 /* R-IVF */ +#define NV_RUNLIST_ENGINE_STATUS1_GFID_VALID_FALSE 0x00000000 /* R-I-V */ +#define NV_RUNLIST_ENGINE_STATUS1_GFID_VALID_TRUE 0x00000001 /* R---V */ +#define NV_RUNLIST_ENGINE_STATUS1_NEXT_GFID_VALID 31:31 /* R-IVF */ +#define NV_RUNLIST_ENGINE_STATUS1_NEXT_GFID_VALID_FALSE 0x00000000 /* R-I-V */ +#define NV_RUNLIST_ENGINE_STATUS1_NEXT_GFID_VALID_TRUE 0x00000001 /* R---V */ +#define NV_RUNLIST_ENGINE_STATUS_CHANNEL(i,j) (0x208+(i)*64+(j)*4) /* R--4A */ +#define NV_RUNLIST_ENGINE_STATUS_CHANNEL__SIZE_1 3 /* */ +#define NV_RUNLIST_ENGINE_STATUS_CHANNEL__SIZE_2 2 /* */ +#define NV_RUNLIST_ENGINE_STATUS_CHANNEL_CHID 11:0 /* */ +#define NV_RUNLIST_ENGINE_STATUS_CHANNEL_CHID_HW 10:0 /* R-XUF */ +#define NV_RUNLIST_ENGINE_STATUS_CHANNEL_VALID 15:15 /* R-IVF */ +#define NV_RUNLIST_ENGINE_STATUS_CHANNEL_VALID_FALSE 0x00000000 /* R-I-V */ +#define NV_RUNLIST_ENGINE_STATUS_CHANNEL_VALID_TRUE 0x00000001 /* R---V */ +#define NV_RUNLIST_ENGINE_STATUS_CHANNEL_NEXT_CHID 27:16 /* */ +#define NV_RUNLIST_ENGINE_STATUS_CHANNEL_NEXT_CHID_HW 26:16 /* R-XUF */ +#define NV_RUNLIST_ENGINE_STATUS_CHANNEL_NEXT_VALID 31:31 /* R-IVF */ +#define NV_RUNLIST_ENGINE_STATUS_CHANNEL_NEXT_VALID_FALSE 0x00000000 /* R-I-V */ +#define NV_RUNLIST_ENGINE_STATUS_CHANNEL_NEXT_VALID_TRUE 0x00000001 /* R---V */ +#define NV_RUNLIST_ENGINE_STATUS_DEBUG(i) (0x228+(i)*64) /* R--4A */ +#define NV_RUNLIST_ENGINE_STATUS_DEBUG__SIZE_1 3 /* */ +#define NV_RUNLIST_ENGINE_STATUS_DEBUG_IF_EN 0:0 /* R-IVF */ +#define NV_RUNLIST_ENGINE_STATUS_DEBUG_IF_EN_DISABLED 0x00000000 /* R---V */ +#define NV_RUNLIST_ENGINE_STATUS_DEBUG_IF_EN_ENABLED 0x00000001 /* R-I-V */ +#define NV_RUNLIST_ENGINE_STATUS_DEBUG_PIPE0_NO_CREDITS 8:8 /* R-IVF */ +#define NV_RUNLIST_ENGINE_STATUS_DEBUG_PIPE0_NO_CREDITS_FALSE 0x00000000 /* R-I-V */ +#define NV_RUNLIST_ENGINE_STATUS_DEBUG_PIPE0_NO_CREDITS_TRUE 0x00000001 /* R---V */ +#define NV_RUNLIST_ENGINE_STATUS_DEBUG_PIPE0_WFI 12:12 /* R-IVF */ +#define NV_RUNLIST_ENGINE_STATUS_DEBUG_PIPE0_WFI_FALSE 0x00000000 /* R-I-V */ +#define NV_RUNLIST_ENGINE_STATUS_DEBUG_PIPE0_WFI_TRUE 0x00000001 /* R---V */ +#define NV_RUNLIST_ENGINE_STATUS_DEBUG_PIPE1_NO_CREDITS 16:16 /* R-IVF */ +#define NV_RUNLIST_ENGINE_STATUS_DEBUG_PIPE1_NO_CREDITS_FALSE 0x00000000 /* R-I-V */ +#define NV_RUNLIST_ENGINE_STATUS_DEBUG_PIPE1_NO_CREDITS_TRUE 0x00000001 /* R---V */ +#define NV_RUNLIST_ENGINE_STATUS_DEBUG_PIPE1_WFI 20:20 /* R-IVF */ +#define NV_RUNLIST_ENGINE_STATUS_DEBUG_PIPE1_WFI_FALSE 0x00000000 /* R-I-V */ +#define NV_RUNLIST_ENGINE_STATUS_DEBUG_PIPE1_WFI_TRUE 0x00000001 /* R---V */ +#define NV_RUNLIST_ENGINE_STATUS_DEBUG_ENGINE_ID 29:24 /* R-XUF */ +#define NV_RUNLIST_ENGINE_STATUS_INST(i) (0x210+(i)*64) /* R--4A */ +#define NV_RUNLIST_ENGINE_STATUS_INST__SIZE_1 3 /* */ +#define NV_RUNLIST_ENGINE_STATUS_INST_TARGET 1:0 /* R-XUF */ +#define NV_RUNLIST_ENGINE_STATUS_INST_TARGET_VID_MEM 0x00000000 /* R---V */ +#define NV_RUNLIST_ENGINE_STATUS_INST_TARGET_SYS_MEM_COHERENT 0x00000002 /* R---V */ +#define NV_RUNLIST_ENGINE_STATUS_INST_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* R---V */ +#define NV_RUNLIST_ENGINE_STATUS_INST_VALID 11:11 /* R-IVF */ +#define NV_RUNLIST_ENGINE_STATUS_INST_VALID_FALSE 0x00000000 /* R-I-V */ +#define NV_RUNLIST_ENGINE_STATUS_INST_VALID_TRUE 0x00000001 /* R---V */ +#define NV_RUNLIST_ENGINE_STATUS_INST_PTR_LO 31:12 /* R-XUF */ +#define NV_RUNLIST_ENGINE_STATUS_INST_HI(i) (0x214+(i)*64) /* R--4A */ +#define NV_RUNLIST_ENGINE_STATUS_INST_HI__SIZE_1 3 /* */ +#define NV_RUNLIST_ENGINE_STATUS_INST_HI_PTR_HI 31:0 /* R-XUF */ +#define NV_RUNLIST_ENGINE_STATUS_INST_HI_PTR_HI_ZERO 0x00000000 /* R---V */ +#define NV_RUNLIST_ENGINE_STATUS_NEXT_INST(i) (0x218+(i)*64) /* R--4A */ +#define NV_RUNLIST_ENGINE_STATUS_NEXT_INST__SIZE_1 3 /* */ +#define NV_RUNLIST_ENGINE_STATUS_NEXT_INST_TARGET 1:0 /* R-XUF */ +#define NV_RUNLIST_ENGINE_STATUS_NEXT_INST_TARGET_VID_MEM 0x00000000 /* R---V */ +#define NV_RUNLIST_ENGINE_STATUS_NEXT_INST_TARGET_SYS_MEM_COHERENT 0x00000002 /* R---V */ +#define NV_RUNLIST_ENGINE_STATUS_NEXT_INST_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* R---V */ +#define NV_RUNLIST_ENGINE_STATUS_NEXT_INST_VALID 11:11 /* R-IVF */ +#define NV_RUNLIST_ENGINE_STATUS_NEXT_INST_VALID_FALSE 0x00000000 /* R-I-V */ +#define NV_RUNLIST_ENGINE_STATUS_NEXT_INST_VALID_TRUE 0x00000001 /* R---V */ +#define NV_RUNLIST_ENGINE_STATUS_NEXT_INST_PTR_LO 31:12 /* R-XUF */ +#define NV_RUNLIST_ENGINE_STATUS_NEXT_INST_HI(i) (0x21C+(i)*64) /* R--4A */ +#define NV_RUNLIST_ENGINE_STATUS_NEXT_INST_HI__SIZE_1 3 /* */ +#define NV_RUNLIST_ENGINE_STATUS_NEXT_INST_HI_PTR_HI 31:0 /* R-XUF */ +#define NV_RUNLIST_ENGINE_STATUS_NEXT_INST_HI_PTR_HI_ZERO 0x00000000 /* R---V */ +#endif // __ga100_dev_runlist_h__ diff --git a/src/nouveau/headers/nvidia/hwref/hopper/gh100/dev_fault.h b/src/nouveau/headers/nvidia/hwref/hopper/gh100/dev_fault.h new file mode 100644 index 00000000000..83f79cb6d11 --- /dev/null +++ b/src/nouveau/headers/nvidia/hwref/hopper/gh100/dev_fault.h @@ -0,0 +1,508 @@ +/******************************************************************************* + Copyright (c) 2003-2016 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + + +#ifndef __gh100_dev_fault_h__ +#define __gh100_dev_fault_h__ +/* This file is autogenerated. Do not edit */ +#define NV_PFAULT /* ----G */ +#define NV_PFAULT_MMU_ENG_ID_GRAPHICS 384 /* */ +#define NV_PFAULT_MMU_ENG_ID_DISPLAY 1 /* */ +#define NV_PFAULT_MMU_ENG_ID_GSP 2 /* */ +#define NV_PFAULT_MMU_ENG_ID_IFB 55 /* */ +#define NV_PFAULT_MMU_ENG_ID_FLA 4 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1 256 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2 320 /* */ +#define NV_PFAULT_MMU_ENG_ID_SEC 6 /* */ +#define NV_PFAULT_MMU_ENG_ID_FSP 7 /* */ +#define NV_PFAULT_MMU_ENG_ID_PERF 10 /* */ +#define NV_PFAULT_MMU_ENG_ID_PERF0 10 /* */ +#define NV_PFAULT_MMU_ENG_ID_PERF1 11 /* */ +#define NV_PFAULT_MMU_ENG_ID_PERF2 12 /* */ +#define NV_PFAULT_MMU_ENG_ID_PERF3 13 /* */ +#define NV_PFAULT_MMU_ENG_ID_PERF4 14 /* */ +#define NV_PFAULT_MMU_ENG_ID_PERF5 15 /* */ +#define NV_PFAULT_MMU_ENG_ID_PERF6 16 /* */ +#define NV_PFAULT_MMU_ENG_ID_PERF7 17 /* */ +#define NV_PFAULT_MMU_ENG_ID_PERF8 18 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVDEC 19 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVDEC0 19 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVDEC1 20 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVDEC2 21 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVDEC3 22 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVDEC4 23 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVDEC5 24 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVDEC6 25 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVDEC7 26 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVJPG0 27 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVJPG1 28 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVJPG2 29 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVJPG3 30 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVJPG4 31 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVJPG5 32 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVJPG6 33 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVJPG7 34 /* */ +#define NV_PFAULT_MMU_ENG_ID_GRCOPY 43 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE0 43 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE1 44 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE2 45 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE3 46 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE4 47 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE5 48 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE6 49 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE7 50 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE8 51 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE9 52 /* */ +#define NV_PFAULT_MMU_ENG_ID_PWR_PMU 5 /* */ +#define NV_PFAULT_MMU_ENG_ID_PTP 3 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVENC0 35 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVENC1 36 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVENC2 37 /* */ +#define NV_PFAULT_MMU_ENG_ID_OFA0 53 /* */ +#define NV_PFAULT_MMU_ENG_ID_PHYSICAL 56 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST0 64 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST1 65 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST2 66 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST3 67 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST4 68 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST5 69 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST6 70 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST7 71 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST8 72 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST9 73 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST10 74 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST11 75 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST12 76 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST13 77 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST14 78 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST15 79 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST16 80 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST17 81 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST18 82 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST19 83 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST20 84 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST21 85 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST22 86 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST23 87 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST24 88 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST25 89 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST26 90 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST27 91 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST28 92 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST29 93 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST30 94 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST31 95 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST32 96 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST33 97 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST34 98 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST35 99 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST36 100 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST37 101 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST38 102 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST39 103 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST40 104 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST41 105 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST42 106 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST43 107 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST44 108 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN0 256 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN1 257 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN2 258 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN3 259 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN4 260 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN5 261 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN6 262 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN7 263 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN8 264 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN9 265 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN10 266 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN11 267 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN12 268 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN13 269 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN14 270 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN15 271 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN16 272 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN17 273 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN18 274 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN19 275 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN20 276 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN21 277 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN22 278 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN23 279 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN24 280 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN25 281 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN26 282 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN27 283 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN28 284 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN29 285 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN30 286 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN31 287 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN32 288 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN33 289 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN34 290 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN35 291 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN36 292 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN37 293 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN38 294 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN39 295 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN40 296 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN41 297 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN42 298 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN43 299 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN44 300 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN45 301 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN46 302 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN47 303 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN48 304 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN49 305 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN50 306 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN51 307 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN52 308 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN53 309 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN54 310 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN55 311 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN56 312 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN57 313 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN58 314 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN59 315 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN60 316 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN61 317 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN62 318 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN63 319 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN0 320 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN1 321 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN2 322 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN3 323 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN4 324 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN5 325 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN6 326 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN7 327 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN8 328 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN9 329 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN10 330 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN11 331 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN12 332 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN13 333 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN14 334 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN15 335 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN16 336 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN17 337 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN18 338 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN19 339 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN20 340 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN21 341 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN22 342 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN23 343 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN24 344 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN25 345 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN26 346 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN27 347 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN28 348 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN29 349 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN30 350 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN31 351 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN32 352 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN33 353 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN34 354 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN35 355 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN36 356 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN37 357 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN38 358 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN39 359 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN40 360 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN41 361 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN42 362 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN43 363 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN44 364 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN45 365 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN46 366 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN47 367 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN48 368 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN49 369 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN50 370 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN51 371 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN52 372 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN53 373 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN54 374 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN55 375 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN56 376 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN57 377 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN58 378 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN59 379 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN60 380 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN61 381 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN62 382 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN63 383 /* */ +#define NV_PFAULT_FAULT_TYPE 4:0 /* */ +#define NV_PFAULT_FAULT_TYPE_PDE 0x00000000 /* */ +#define NV_PFAULT_FAULT_TYPE_PDE_SIZE 0x00000001 /* */ +#define NV_PFAULT_FAULT_TYPE_PTE 0x00000002 /* */ +#define NV_PFAULT_FAULT_TYPE_VA_LIMIT_VIOLATION 0x00000003 /* */ +#define NV_PFAULT_FAULT_TYPE_UNBOUND_INST_BLOCK 0x00000004 /* */ +#define NV_PFAULT_FAULT_TYPE_PRIV_VIOLATION 0x00000005 /* */ +#define NV_PFAULT_FAULT_TYPE_RO_VIOLATION 0x00000006 /* */ +#define NV_PFAULT_FAULT_TYPE_WO_VIOLATION 0x00000007 /* */ +#define NV_PFAULT_FAULT_TYPE_PITCH_MASK_VIOLATION 0x00000008 /* */ +#define NV_PFAULT_FAULT_TYPE_WORK_CREATION 0x00000009 /* */ +#define NV_PFAULT_FAULT_TYPE_UNSUPPORTED_APERTURE 0x0000000a /* */ +#define NV_PFAULT_FAULT_TYPE_COMPRESSION_FAILURE 0x0000000b /* */ +#define NV_PFAULT_FAULT_TYPE_UNSUPPORTED_KIND 0x0000000c /* */ +#define NV_PFAULT_FAULT_TYPE_REGION_VIOLATION 0x0000000d /* */ +#define NV_PFAULT_FAULT_TYPE_POISONED 0x0000000e /* */ +#define NV_PFAULT_FAULT_TYPE_ATOMIC_VIOLATION 0x0000000f /* */ +#define NV_PFAULT_CLIENT 14:8 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_0 0x00000000 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_1 0x00000001 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_2 0x00000002 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_3 0x00000003 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_4 0x00000004 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_5 0x00000005 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_6 0x00000006 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_7 0x00000007 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_0 0x00000008 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_1 0x00000009 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_2 0x0000000A /* */ +#define NV_PFAULT_CLIENT_GPC_PE_3 0x0000000B /* */ +#define NV_PFAULT_CLIENT_GPC_PE_4 0x0000000C /* */ +#define NV_PFAULT_CLIENT_GPC_PE_5 0x0000000D /* */ +#define NV_PFAULT_CLIENT_GPC_PE_6 0x0000000E /* */ +#define NV_PFAULT_CLIENT_GPC_PE_7 0x0000000F /* */ +#define NV_PFAULT_CLIENT_GPC_RAST 0x00000010 /* */ +#define NV_PFAULT_CLIENT_GPC_GCC 0x00000011 /* */ +#define NV_PFAULT_CLIENT_GPC_GPCCS 0x00000012 /* */ +#define NV_PFAULT_CLIENT_GPC_PROP_0 0x00000013 /* */ +#define NV_PFAULT_CLIENT_GPC_PROP_1 0x00000014 /* */ +#define NV_PFAULT_CLIENT_GPC_PROP_2 0x00000015 /* */ +#define NV_PFAULT_CLIENT_GPC_PROP_3 0x00000016 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_8 0x00000021 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_9 0x00000022 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_10 0x00000023 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_11 0x00000024 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_12 0x00000025 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_13 0x00000026 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_14 0x00000027 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_15 0x00000028 /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_0 0x00000029 /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_1 0x0000002A /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_2 0x0000002B /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_3 0x0000002C /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_4 0x0000002D /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_5 0x0000002E /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_6 0x0000002F /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_7 0x00000030 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_8 0x00000031 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_9 0x00000032 /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_8 0x00000033 /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_9 0x00000034 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_16 0x00000035 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_17 0x00000036 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_18 0x00000037 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_19 0x00000038 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_10 0x00000039 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_11 0x0000003A /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_10 0x0000003B /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_11 0x0000003C /* */ +#define NV_PFAULT_CLIENT_GPC_T1_20 0x0000003D /* */ +#define NV_PFAULT_CLIENT_GPC_T1_21 0x0000003E /* */ +#define NV_PFAULT_CLIENT_GPC_T1_22 0x0000003F /* */ +#define NV_PFAULT_CLIENT_GPC_T1_23 0x00000040 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_12 0x00000041 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_13 0x00000042 /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_12 0x00000043 /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_13 0x00000044 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_24 0x00000045 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_25 0x00000046 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_26 0x00000047 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_27 0x00000048 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_14 0x00000049 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_15 0x0000004A /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_14 0x0000004B /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_15 0x0000004C /* */ +#define NV_PFAULT_CLIENT_GPC_T1_28 0x0000004D /* */ +#define NV_PFAULT_CLIENT_GPC_T1_29 0x0000004E /* */ +#define NV_PFAULT_CLIENT_GPC_T1_30 0x0000004F /* */ +#define NV_PFAULT_CLIENT_GPC_T1_31 0x00000050 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_16 0x00000051 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_17 0x00000052 /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_16 0x00000053 /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_17 0x00000054 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_32 0x00000055 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_33 0x00000056 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_34 0x00000057 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_35 0x00000058 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_18 0x00000059 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_19 0x0000005A /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_18 0x0000005B /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_19 0x0000005C /* */ +#define NV_PFAULT_CLIENT_GPC_T1_36 0x0000005D /* */ +#define NV_PFAULT_CLIENT_GPC_T1_37 0x0000005E /* */ +#define NV_PFAULT_CLIENT_GPC_T1_38 0x0000005F /* */ +#define NV_PFAULT_CLIENT_GPC_T1_39 0x00000060 /* */ +#define NV_PFAULT_CLIENT_GPC_ROP_0 0x00000070 /* */ +#define NV_PFAULT_CLIENT_GPC_ROP_1 0x00000071 /* */ +#define NV_PFAULT_CLIENT_GPC_ROP_2 0x00000072 /* */ +#define NV_PFAULT_CLIENT_GPC_ROP_3 0x00000073 /* */ +#define NV_PFAULT_CLIENT_GPC_GPM 0x00000017 /* */ +#define NV_PFAULT_CLIENT_HUB_VIP 0x00000000 /* */ +#define NV_PFAULT_CLIENT_HUB_CE0 0x00000001 /* */ +#define NV_PFAULT_CLIENT_HUB_CE1 0x00000002 /* */ +#define NV_PFAULT_CLIENT_HUB_DNISO 0x00000003 /* */ +#define NV_PFAULT_CLIENT_HUB_DISPNISO 0x00000003 /* */ +#define NV_PFAULT_CLIENT_HUB_FE0 0x00000004 /* */ +#define NV_PFAULT_CLIENT_HUB_FE 0x00000004 /* */ +#define NV_PFAULT_CLIENT_HUB_FECS0 0x00000005 /* */ +#define NV_PFAULT_CLIENT_HUB_FECS 0x00000005 /* */ +#define NV_PFAULT_CLIENT_HUB_HOST 0x00000006 /* */ +#define NV_PFAULT_CLIENT_HUB_HOST_CPU 0x00000007 /* */ +#define NV_PFAULT_CLIENT_HUB_HOST_CPU_NB 0x00000008 /* */ +#define NV_PFAULT_CLIENT_HUB_ISO 0x00000009 /* */ +#define NV_PFAULT_CLIENT_HUB_MMU 0x0000000A /* */ +#define NV_PFAULT_CLIENT_HUB_NVDEC0 0x0000000B /* */ +#define NV_PFAULT_CLIENT_HUB_NVDEC 0x0000000B /* */ +#define NV_PFAULT_CLIENT_HUB_CE3 0x0000000C /* */ +#define NV_PFAULT_CLIENT_HUB_NVENC1 0x0000000D /* */ +#define NV_PFAULT_CLIENT_HUB_NISO 0x0000000E /* */ +#define NV_PFAULT_CLIENT_HUB_ACTRS 0x0000000E /* */ +#define NV_PFAULT_CLIENT_HUB_P2P 0x0000000F /* */ +#define NV_PFAULT_CLIENT_HUB_PD 0x00000010 /* */ +#define NV_PFAULT_CLIENT_HUB_PERF0 0x00000011 /* */ +#define NV_PFAULT_CLIENT_HUB_PERF 0x00000011 /* */ +#define NV_PFAULT_CLIENT_HUB_PMU 0x00000012 /* */ +#define NV_PFAULT_CLIENT_HUB_RASTERTWOD 0x00000013 /* */ +#define NV_PFAULT_CLIENT_HUB_SCC 0x00000014 /* */ +#define NV_PFAULT_CLIENT_HUB_SCC_NB 0x00000015 /* */ +#define NV_PFAULT_CLIENT_HUB_SEC 0x00000016 /* */ +#define NV_PFAULT_CLIENT_HUB_SSYNC 0x00000017 /* */ +#define NV_PFAULT_CLIENT_HUB_GRCOPY 0x00000018 /* */ +#define NV_PFAULT_CLIENT_HUB_CE2 0x00000018 /* */ +#define NV_PFAULT_CLIENT_HUB_XV 0x00000019 /* */ +#define NV_PFAULT_CLIENT_HUB_MMU_NB 0x0000001A /* */ +#define NV_PFAULT_CLIENT_HUB_NVENC0 0x0000001B /* */ +#define NV_PFAULT_CLIENT_HUB_NVENC 0x0000001B /* */ +#define NV_PFAULT_CLIENT_HUB_DFALCON 0x0000001C /* */ +#define NV_PFAULT_CLIENT_HUB_SKED0 0x0000001D /* */ +#define NV_PFAULT_CLIENT_HUB_SKED 0x0000001D /* */ +#define NV_PFAULT_CLIENT_HUB_AFALCON 0x0000001E /* */ +#define NV_PFAULT_CLIENT_HUB_DONT_CARE 0x0000001F /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE0 0x00000020 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE1 0x00000021 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE2 0x00000022 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE3 0x00000023 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE4 0x00000024 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE5 0x00000025 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE6 0x00000026 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE7 0x00000027 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE8 0x00000028 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE9 0x00000029 /* */ +#define NV_PFAULT_CLIENT_HUB_HSHUB 0x0000002A /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X0 0x0000002B /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X1 0x0000002C /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X2 0x0000002D /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X3 0x0000002E /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X4 0x0000002F /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X5 0x00000030 /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X6 0x00000031 /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X7 0x00000032 /* */ +#define NV_PFAULT_CLIENT_HUB_NVENC2 0x00000033 /* */ +#define NV_PFAULT_CLIENT_HUB_VPR_SCRUBBER0 0x00000034 /* */ +#define NV_PFAULT_CLIENT_HUB_VPR_SCRUBBER1 0x00000035 /* */ +#define NV_PFAULT_CLIENT_HUB_DWBIF 0x00000036 /* */ +#define NV_PFAULT_CLIENT_HUB_FBFALCON 0x00000037 /* */ +#define NV_PFAULT_CLIENT_HUB_CE_SHIM 0x00000038 /* */ +#define NV_PFAULT_CLIENT_HUB_GSP 0x00000039 /* */ +#define NV_PFAULT_CLIENT_HUB_NVDEC1 0x0000003A /* */ +#define NV_PFAULT_CLIENT_HUB_NVDEC2 0x0000003B /* */ +#define NV_PFAULT_CLIENT_HUB_NVJPG0 0x0000003C /* */ +#define NV_PFAULT_CLIENT_HUB_NVDEC3 0x0000003D /* */ +#define NV_PFAULT_CLIENT_HUB_NVDEC4 0x0000003E /* */ +#define NV_PFAULT_CLIENT_HUB_OFA0 0x0000003F /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE10 0x00000040 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE11 0x00000041 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE12 0x00000042 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE13 0x00000043 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE14 0x00000044 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE15 0x00000045 /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X8 0x00000046 /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X9 0x00000047 /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X10 0x00000048 /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X11 0x00000049 /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X12 0x0000004A /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X13 0x0000004B /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X14 0x0000004C /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X15 0x0000004D /* */ +#define NV_PFAULT_CLIENT_HUB_FE1 0x0000004E /* */ +#define NV_PFAULT_CLIENT_HUB_FE2 0x0000004F /* */ +#define NV_PFAULT_CLIENT_HUB_FE3 0x00000050 /* */ +#define NV_PFAULT_CLIENT_HUB_FE4 0x00000051 /* */ +#define NV_PFAULT_CLIENT_HUB_FE5 0x00000052 /* */ +#define NV_PFAULT_CLIENT_HUB_FE6 0x00000053 /* */ +#define NV_PFAULT_CLIENT_HUB_FE7 0x00000054 /* */ +#define NV_PFAULT_CLIENT_HUB_FECS1 0x00000055 /* */ +#define NV_PFAULT_CLIENT_HUB_FECS2 0x00000056 /* */ +#define NV_PFAULT_CLIENT_HUB_FECS3 0x00000057 /* */ +#define NV_PFAULT_CLIENT_HUB_FECS4 0x00000058 /* */ +#define NV_PFAULT_CLIENT_HUB_FECS5 0x00000059 /* */ +#define NV_PFAULT_CLIENT_HUB_FECS6 0x0000005A /* */ +#define NV_PFAULT_CLIENT_HUB_FECS7 0x0000005B /* */ +#define NV_PFAULT_CLIENT_HUB_SKED1 0x0000005C /* */ +#define NV_PFAULT_CLIENT_HUB_SKED2 0x0000005D /* */ +#define NV_PFAULT_CLIENT_HUB_SKED3 0x0000005E /* */ +#define NV_PFAULT_CLIENT_HUB_SKED4 0x0000005F /* */ +#define NV_PFAULT_CLIENT_HUB_SKED5 0x00000060 /* */ +#define NV_PFAULT_CLIENT_HUB_SKED6 0x00000061 /* */ +#define NV_PFAULT_CLIENT_HUB_SKED7 0x00000062 /* */ +#define NV_PFAULT_CLIENT_HUB_ESC 0x00000063 /* */ +#define NV_PFAULT_CLIENT_HUB_NVDEC5 0x0000006F /* */ +#define NV_PFAULT_CLIENT_HUB_NVDEC6 0x00000070 /* */ +#define NV_PFAULT_CLIENT_HUB_NVDEC7 0x00000071 /* */ +#define NV_PFAULT_CLIENT_HUB_NVJPG1 0x00000072 /* */ +#define NV_PFAULT_CLIENT_HUB_NVJPG2 0x00000073 /* */ +#define NV_PFAULT_CLIENT_HUB_NVJPG3 0x00000074 /* */ +#define NV_PFAULT_CLIENT_HUB_NVJPG4 0x00000075 /* */ +#define NV_PFAULT_CLIENT_HUB_NVJPG5 0x00000076 /* */ +#define NV_PFAULT_CLIENT_HUB_NVJPG6 0x00000077 /* */ +#define NV_PFAULT_CLIENT_HUB_NVJPG7 0x00000078 /* */ +#define NV_PFAULT_CLIENT_HUB_FSP 0x00000079 /* */ +#define NV_PFAULT_ACCESS_TYPE 19:16 /* */ +#define NV_PFAULT_ACCESS_TYPE_READ 0x00000000 /* */ +#define NV_PFAULT_ACCESS_TYPE_WRITE 0x00000001 /* */ +#define NV_PFAULT_ACCESS_TYPE_ATOMIC 0x00000002 /* */ +#define NV_PFAULT_ACCESS_TYPE_PREFETCH 0x00000003 /* */ +#define NV_PFAULT_ACCESS_TYPE_VIRT_READ 0x00000000 /* */ +#define NV_PFAULT_ACCESS_TYPE_VIRT_WRITE 0x00000001 /* */ +#define NV_PFAULT_ACCESS_TYPE_VIRT_ATOMIC 0x00000002 /* */ +#define NV_PFAULT_ACCESS_TYPE_VIRT_ATOMIC_STRONG 0x00000002 /* */ +#define NV_PFAULT_ACCESS_TYPE_VIRT_PREFETCH 0x00000003 /* */ +#define NV_PFAULT_ACCESS_TYPE_VIRT_ATOMIC_WEAK 0x00000004 /* */ +#define NV_PFAULT_ACCESS_TYPE_PHYS_READ 0x00000008 /* */ +#define NV_PFAULT_ACCESS_TYPE_PHYS_WRITE 0x00000009 /* */ +#define NV_PFAULT_ACCESS_TYPE_PHYS_ATOMIC 0x0000000a /* */ +#define NV_PFAULT_ACCESS_TYPE_PHYS_PREFETCH 0x0000000b /* */ +#define NV_PFAULT_MMU_CLIENT_TYPE 20:20 /* */ +#define NV_PFAULT_MMU_CLIENT_TYPE_GPC 0x00000000 /* */ +#define NV_PFAULT_MMU_CLIENT_TYPE_HUB 0x00000001 /* */ +#define NV_PFAULT_GPC_ID 28:24 /* */ +#define NV_PFAULT_PROTECTED_MODE 29:29 /* */ +#define NV_PFAULT_REPLAYABLE_FAULT_EN 30:30 /* */ +#define NV_PFAULT_VALID 31:31 /* */ +#endif // __gh100_dev_fault_h__ diff --git a/src/nouveau/headers/nvidia/hwref/hopper/gh100/dev_mmu.h b/src/nouveau/headers/nvidia/hwref/hopper/gh100/dev_mmu.h new file mode 100644 index 00000000000..42b11fead0e --- /dev/null +++ b/src/nouveau/headers/nvidia/hwref/hopper/gh100/dev_mmu.h @@ -0,0 +1,560 @@ +/******************************************************************************* + Copyright (c) 2003-2016 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + + +#ifndef __gh100_dev_mmu_h__ +#define __gh100_dev_mmu_h__ +/* This file is autogenerated. Do not edit */ +#define NV_MMU_PDE /* ----G */ +#define NV_MMU_PDE_APERTURE_BIG (0*32+1):(0*32+0) /* RWXVF */ +#define NV_MMU_PDE_APERTURE_BIG_INVALID 0x00000000 /* RW--V */ +#define NV_MMU_PDE_APERTURE_BIG_VIDEO_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_PDE_APERTURE_BIG_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_PDE_APERTURE_BIG_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_PDE_SIZE (0*32+3):(0*32+2) /* RWXVF */ +#define NV_MMU_PDE_SIZE_FULL 0x00000000 /* RW--V */ +#define NV_MMU_PDE_SIZE_HALF 0x00000001 /* RW--V */ +#define NV_MMU_PDE_SIZE_QUARTER 0x00000002 /* RW--V */ +#define NV_MMU_PDE_SIZE_EIGHTH 0x00000003 /* RW--V */ +#define NV_MMU_PDE_ADDRESS_BIG_SYS (0*32+31):(0*32+4) /* RWXVF */ +#define NV_MMU_PDE_ADDRESS_BIG_VID (0*32+31-3):(0*32+4) /* RWXVF */ +#define NV_MMU_PDE_ADDRESS_BIG_VID_PEER (0*32+31):(0*32+32-3) /* RWXVF */ +#define NV_MMU_PDE_ADDRESS_BIG_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_PDE_APERTURE_SMALL (1*32+1):(1*32+0) /* RWXVF */ +#define NV_MMU_PDE_APERTURE_SMALL_INVALID 0x00000000 /* RW--V */ +#define NV_MMU_PDE_APERTURE_SMALL_VIDEO_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_PDE_APERTURE_SMALL_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_PDE_APERTURE_SMALL_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_PDE_VOL_SMALL (1*32+2):(1*32+2) /* RWXVF */ +#define NV_MMU_PDE_VOL_SMALL_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_PDE_VOL_SMALL_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_PDE_VOL_BIG (1*32+3):(1*32+3) /* RWXVF */ +#define NV_MMU_PDE_VOL_BIG_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_PDE_VOL_BIG_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_PDE_ADDRESS_SMALL_SYS (1*32+31):(1*32+4) /* RWXVF */ +#define NV_MMU_PDE_ADDRESS_SMALL_VID (1*32+31-3):(1*32+4) /* RWXVF */ +#define NV_MMU_PDE_ADDRESS_SMALL_VID_PEER (1*32+31):(1*32+32-3) /* RWXVF */ +#define NV_MMU_PDE_ADDRESS_SMALL_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_PDE_ADDRESS_SHIFT 0x0000000c /* */ +#define NV_MMU_PDE__SIZE 8 +#define NV_MMU_PTE /* ----G */ +#define NV_MMU_PTE_VALID (0*32+0):(0*32+0) /* RWXVF */ +#define NV_MMU_PTE_VALID_TRUE 0x1 /* RW--V */ +#define NV_MMU_PTE_VALID_FALSE 0x0 /* RW--V */ +#define NV_MMU_PTE_PRIVILEGE (0*32+1):(0*32+1) /* RWXVF */ +#define NV_MMU_PTE_PRIVILEGE_TRUE 0x1 /* RW--V */ +#define NV_MMU_PTE_PRIVILEGE_FALSE 0x0 /* RW--V */ +#define NV_MMU_PTE_READ_ONLY (0*32+2):(0*32+2) /* RWXVF */ +#define NV_MMU_PTE_READ_ONLY_TRUE 0x1 /* RW--V */ +#define NV_MMU_PTE_READ_ONLY_FALSE 0x0 /* RW--V */ +#define NV_MMU_PTE_ENCRYPTED (0*32+3):(0*32+3) /* RWXVF */ +#define NV_MMU_PTE_ENCRYPTED_TRUE 0x00000001 /* R---V */ +#define NV_MMU_PTE_ENCRYPTED_FALSE 0x00000000 /* R---V */ +#define NV_MMU_PTE_ADDRESS_SYS (0*32+31):(0*32+4) /* RWXVF */ +#define NV_MMU_PTE_ADDRESS_VID (0*32+31-3):(0*32+4) /* RWXVF */ +#define NV_MMU_PTE_ADDRESS_VID_PEER (0*32+31):(0*32+32-3) /* RWXVF */ +#define NV_MMU_PTE_ADDRESS_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_PTE_ADDRESS_VID_PEER_1 0x00000001 /* RW--V */ +#define NV_MMU_PTE_ADDRESS_VID_PEER_2 0x00000002 /* RW--V */ +#define NV_MMU_PTE_ADDRESS_VID_PEER_3 0x00000003 /* RW--V */ +#define NV_MMU_PTE_ADDRESS_VID_PEER_4 0x00000004 /* RW--V */ +#define NV_MMU_PTE_ADDRESS_VID_PEER_5 0x00000005 /* RW--V */ +#define NV_MMU_PTE_ADDRESS_VID_PEER_6 0x00000006 /* RW--V */ +#define NV_MMU_PTE_ADDRESS_VID_PEER_7 0x00000007 /* RW--V */ +#define NV_MMU_PTE_VOL (1*32+0):(1*32+0) /* RWXVF */ +#define NV_MMU_PTE_VOL_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_PTE_VOL_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_PTE_APERTURE (1*32+2):(1*32+1) /* RWXVF */ +#define NV_MMU_PTE_APERTURE_VIDEO_MEMORY 0x00000000 /* RW--V */ +#define NV_MMU_PTE_APERTURE_PEER_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_PTE_APERTURE_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_PTE_LOCK (1*32+3):(1*32+3) /* RWXVF */ +#define NV_MMU_PTE_LOCK_TRUE 0x1 /* RW--V */ +#define NV_MMU_PTE_LOCK_FALSE 0x0 /* RW--V */ +#define NV_MMU_PTE_ATOMIC_DISABLE (1*32+3):(1*32+3) /* RWXVF */ +#define NV_MMU_PTE_ATOMIC_DISABLE_TRUE 0x1 /* RW--V */ +#define NV_MMU_PTE_ATOMIC_DISABLE_FALSE 0x0 /* RW--V */ +#define NV_MMU_PTE_COMPTAGLINE (1*32+20+11):(1*32+12) /* RWXVF */ +#define NV_MMU_PTE_READ_DISABLE (1*32+30):(1*32+30) /* RWXVF */ +#define NV_MMU_PTE_READ_DISABLE_TRUE 0x1 /* RW--V */ +#define NV_MMU_PTE_READ_DISABLE_FALSE 0x0 /* RW--V */ +#define NV_MMU_PTE_WRITE_DISABLE (1*32+31):(1*32+31) /* RWXVF */ +#define NV_MMU_PTE_WRITE_DISABLE_TRUE 0x1 /* RW--V */ +#define NV_MMU_PTE_WRITE_DISABLE_FALSE 0x0 /* RW--V */ +#define NV_MMU_PTE_ADDRESS_SHIFT 0x0000000c /* */ +#define NV_MMU_PTE__SIZE 8 +#define NV_MMU_PTE_COMPTAGS_NONE 0x0 /* */ +#define NV_MMU_PTE_COMPTAGS_1 0x1 /* */ +#define NV_MMU_PTE_COMPTAGS_2 0x2 /* */ +#define NV_MMU_PTE_KIND (1*32+7):(1*32+4) /* RWXVF */ +#define NV_MMU_PTE_KIND_INVALID 0x07 /* R---V */ +#define NV_MMU_PTE_KIND_PITCH 0x00 /* R---V */ +#define NV_MMU_PTE_KIND_GENERIC_MEMORY 0x6 /* R---V */ +#define NV_MMU_PTE_KIND_Z16 0x1 /* R---V */ +#define NV_MMU_PTE_KIND_S8 0x2 /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24 0x3 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8 0x4 /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8 0x5 /* R---V */ +#define NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE 0x8 /* R---V */ +#define NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE_DISABLE_PLC 0x9 /* R---V */ +#define NV_MMU_PTE_KIND_S8_COMPRESSIBLE_DISABLE_PLC 0xA /* R---V */ +#define NV_MMU_PTE_KIND_Z16_COMPRESSIBLE_DISABLE_PLC 0xB /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_COMPRESSIBLE_DISABLE_PLC 0xC /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8_COMPRESSIBLE_DISABLE_PLC 0xD /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_COMPRESSIBLE_DISABLE_PLC 0xE /* R---V */ +#define NV_MMU_PTE_KIND_SMSKED_MESSAGE 0xF /* R---V */ +#define NV_MMU_VER1_PDE /* ----G */ +#define NV_MMU_VER1_PDE_APERTURE_BIG (0*32+1):(0*32+0) /* RWXVF */ +#define NV_MMU_VER1_PDE_APERTURE_BIG_INVALID 0x00000000 /* RW--V */ +#define NV_MMU_VER1_PDE_APERTURE_BIG_VIDEO_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_VER1_PDE_APERTURE_BIG_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_VER1_PDE_APERTURE_BIG_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_VER1_PDE_SIZE (0*32+3):(0*32+2) /* RWXVF */ +#define NV_MMU_VER1_PDE_SIZE_FULL 0x00000000 /* RW--V */ +#define NV_MMU_VER1_PDE_SIZE_HALF 0x00000001 /* RW--V */ +#define NV_MMU_VER1_PDE_SIZE_QUARTER 0x00000002 /* RW--V */ +#define NV_MMU_VER1_PDE_SIZE_EIGHTH 0x00000003 /* RW--V */ +#define NV_MMU_VER1_PDE_ADDRESS_BIG_SYS (0*32+31):(0*32+4) /* RWXVF */ +#define NV_MMU_VER1_PDE_ADDRESS_BIG_VID (0*32+31-3):(0*32+4) /* RWXVF */ +#define NV_MMU_VER1_PDE_ADDRESS_BIG_VID_PEER (0*32+31):(0*32+32-3) /* RWXVF */ +#define NV_MMU_VER1_PDE_ADDRESS_BIG_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_VER1_PDE_APERTURE_SMALL (1*32+1):(1*32+0) /* RWXVF */ +#define NV_MMU_VER1_PDE_APERTURE_SMALL_INVALID 0x00000000 /* RW--V */ +#define NV_MMU_VER1_PDE_APERTURE_SMALL_VIDEO_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_VER1_PDE_APERTURE_SMALL_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_VER1_PDE_APERTURE_SMALL_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_VER1_PDE_VOL_SMALL (1*32+2):(1*32+2) /* RWXVF */ +#define NV_MMU_VER1_PDE_VOL_SMALL_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_VER1_PDE_VOL_SMALL_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_VER1_PDE_VOL_BIG (1*32+3):(1*32+3) /* RWXVF */ +#define NV_MMU_VER1_PDE_VOL_BIG_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_VER1_PDE_VOL_BIG_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_VER1_PDE_ADDRESS_SMALL_SYS (1*32+31):(1*32+4) /* RWXVF */ +#define NV_MMU_VER1_PDE_ADDRESS_SMALL_VID (1*32+31-3):(1*32+4) /* RWXVF */ +#define NV_MMU_VER1_PDE_ADDRESS_SMALL_VID_PEER (1*32+31):(1*32+32-3) /* RWXVF */ +#define NV_MMU_VER1_PDE_ADDRESS_SMALL_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_VER1_PDE_ADDRESS_SHIFT 0x0000000c /* */ +#define NV_MMU_VER1_PDE__SIZE 8 +#define NV_MMU_VER1_PTE /* ----G */ +#define NV_MMU_VER1_PTE_VALID (0*32+0):(0*32+0) /* RWXVF */ +#define NV_MMU_VER1_PTE_VALID_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER1_PTE_VALID_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER1_PTE_PRIVILEGE (0*32+1):(0*32+1) /* RWXVF */ +#define NV_MMU_VER1_PTE_PRIVILEGE_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER1_PTE_PRIVILEGE_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER1_PTE_READ_ONLY (0*32+2):(0*32+2) /* RWXVF */ +#define NV_MMU_VER1_PTE_READ_ONLY_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER1_PTE_READ_ONLY_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER1_PTE_ENCRYPTED (0*32+3):(0*32+3) /* RWXVF */ +#define NV_MMU_VER1_PTE_ENCRYPTED_TRUE 0x00000001 /* R---V */ +#define NV_MMU_VER1_PTE_ENCRYPTED_FALSE 0x00000000 /* R---V */ +#define NV_MMU_VER1_PTE_ADDRESS_SYS (0*32+31):(0*32+4) /* RWXVF */ +#define NV_MMU_VER1_PTE_ADDRESS_VID (0*32+31-3):(0*32+4) /* RWXVF */ +#define NV_MMU_VER1_PTE_ADDRESS_VID_PEER (0*32+31):(0*32+32-3) /* RWXVF */ +#define NV_MMU_VER1_PTE_ADDRESS_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_VER1_PTE_ADDRESS_VID_PEER_1 0x00000001 /* RW--V */ +#define NV_MMU_VER1_PTE_ADDRESS_VID_PEER_2 0x00000002 /* RW--V */ +#define NV_MMU_VER1_PTE_ADDRESS_VID_PEER_3 0x00000003 /* RW--V */ +#define NV_MMU_VER1_PTE_ADDRESS_VID_PEER_4 0x00000004 /* RW--V */ +#define NV_MMU_VER1_PTE_ADDRESS_VID_PEER_5 0x00000005 /* RW--V */ +#define NV_MMU_VER1_PTE_ADDRESS_VID_PEER_6 0x00000006 /* RW--V */ +#define NV_MMU_VER1_PTE_ADDRESS_VID_PEER_7 0x00000007 /* RW--V */ +#define NV_MMU_VER1_PTE_VOL (1*32+0):(1*32+0) /* RWXVF */ +#define NV_MMU_VER1_PTE_VOL_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_VER1_PTE_VOL_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_VER1_PTE_APERTURE (1*32+2):(1*32+1) /* RWXVF */ +#define NV_MMU_VER1_PTE_APERTURE_VIDEO_MEMORY 0x00000000 /* RW--V */ +#define NV_MMU_VER1_PTE_APERTURE_PEER_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_VER1_PTE_APERTURE_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_VER1_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_VER1_PTE_ATOMIC_DISABLE (1*32+3):(1*32+3) /* RWXVF */ +#define NV_MMU_VER1_PTE_ATOMIC_DISABLE_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER1_PTE_ATOMIC_DISABLE_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER1_PTE_COMPTAGLINE (1*32+20+11):(1*32+12) /* RWXVF */ +#define NV_MMU_VER1_PTE_KIND (1*32+11):(1*32+4) /* RWXVF */ +#define NV_MMU_VER1_PTE_ADDRESS_SHIFT 0x0000000c /* */ +#define NV_MMU_VER1_PTE__SIZE 8 +#define NV_MMU_VER1_PTE_COMPTAGS_NONE 0x0 /* */ +#define NV_MMU_VER1_PTE_COMPTAGS_1 0x1 /* */ +#define NV_MMU_VER1_PTE_COMPTAGS_2 0x2 /* */ +#define NV_MMU_NEW_PDE /* ----G */ +#define NV_MMU_NEW_PDE_IS_PTE 0:0 /* RWXVF */ +#define NV_MMU_NEW_PDE_IS_PTE_TRUE 0x1 /* RW--V */ +#define NV_MMU_NEW_PDE_IS_PTE_FALSE 0x0 /* RW--V */ +#define NV_MMU_NEW_PDE_IS_PDE 0:0 /* RWXVF */ +#define NV_MMU_NEW_PDE_IS_PDE_TRUE 0x0 /* RW--V */ +#define NV_MMU_NEW_PDE_IS_PDE_FALSE 0x1 /* RW--V */ +#define NV_MMU_NEW_PDE_VALID 0:0 /* RWXVF */ +#define NV_MMU_NEW_PDE_VALID_TRUE 0x1 /* RW--V */ +#define NV_MMU_NEW_PDE_VALID_FALSE 0x0 /* RW--V */ +#define NV_MMU_NEW_PDE_APERTURE 2:1 /* RWXVF */ +#define NV_MMU_NEW_PDE_APERTURE_INVALID 0x00000000 /* RW--V */ +#define NV_MMU_NEW_PDE_APERTURE_VIDEO_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_NEW_PDE_APERTURE_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_NEW_PDE_APERTURE_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_NEW_PDE_VOL 3:3 /* RWXVF */ +#define NV_MMU_NEW_PDE_VOL_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_NEW_PDE_VOL_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_NEW_PDE_NO_ATS 5:5 /* RWXVF */ +#define NV_MMU_NEW_PDE_NO_ATS_TRUE 0x1 /* RW--V */ +#define NV_MMU_NEW_PDE_NO_ATS_FALSE 0x0 /* RW--V */ +#define NV_MMU_NEW_PDE_ADDRESS_SYS 53:8 /* RWXVF */ +#define NV_MMU_NEW_PDE_ADDRESS_VID (35-3):8 /* RWXVF */ +#define NV_MMU_NEW_PDE_ADDRESS_VID_PEER 35:(36-3) /* RWXVF */ +#define NV_MMU_NEW_PDE_ADDRESS_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_NEW_PDE_ADDRESS_SHIFT 0x0000000c /* */ +#define NV_MMU_NEW_PDE__SIZE 8 +#define NV_MMU_NEW_DUAL_PDE /* ----G */ +#define NV_MMU_NEW_DUAL_PDE_IS_PTE 0:0 /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_IS_PTE_TRUE 0x1 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_IS_PTE_FALSE 0x0 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_IS_PDE 0:0 /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_IS_PDE_TRUE 0x0 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_IS_PDE_FALSE 0x1 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_VALID 0:0 /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_VALID_TRUE 0x1 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_VALID_FALSE 0x0 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_APERTURE_BIG 2:1 /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_APERTURE_BIG_INVALID 0x00000000 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_APERTURE_BIG_VIDEO_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_APERTURE_BIG_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_APERTURE_BIG_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_VOL_BIG 3:3 /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_VOL_BIG_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_VOL_BIG_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_NO_ATS 5:5 /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_NO_ATS_TRUE 0x1 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_NO_ATS_FALSE 0x0 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_ADDRESS_BIG_SYS 53:(8-4) /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_ADDRESS_BIG_VID (35-3):(8-4) /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_ADDRESS_BIG_VID_PEER 35:(36-3) /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_ADDRESS_BIG_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_APERTURE_SMALL 66:65 /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_APERTURE_SMALL_INVALID 0x00000000 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_APERTURE_SMALL_VIDEO_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_APERTURE_SMALL_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_APERTURE_SMALL_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_VOL_SMALL 67:67 /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_VOL_SMALL_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_VOL_SMALL_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_ADDRESS_SMALL_SYS 117:72 /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_ADDRESS_SMALL_VID (99-3):72 /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_ADDRESS_SMALL_VID_PEER 99:(100-3) /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_ADDRESS_SMALL_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_ADDRESS_SHIFT 0x0000000c /* */ +#define NV_MMU_NEW_DUAL_PDE_ADDRESS_BIG_SHIFT 8 /* */ +#define NV_MMU_NEW_DUAL_PDE__SIZE 16 +#define NV_MMU_NEW_PTE /* ----G */ +#define NV_MMU_NEW_PTE_VALID 0:0 /* RWXVF */ +#define NV_MMU_NEW_PTE_VALID_TRUE 0x1 /* RW--V */ +#define NV_MMU_NEW_PTE_VALID_FALSE 0x0 /* RW--V */ +#define NV_MMU_NEW_PTE_APERTURE 2:1 /* RWXVF */ +#define NV_MMU_NEW_PTE_APERTURE_VIDEO_MEMORY 0x00000000 /* RW--V */ +#define NV_MMU_NEW_PTE_APERTURE_PEER_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_NEW_PTE_APERTURE_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_NEW_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_NEW_PTE_VOL 3:3 /* RWXVF */ +#define NV_MMU_NEW_PTE_VOL_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_NEW_PTE_VOL_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_NEW_PTE_ENCRYPTED 4:4 /* RWXVF */ +#define NV_MMU_NEW_PTE_ENCRYPTED_TRUE 0x00000001 /* R---V */ +#define NV_MMU_NEW_PTE_ENCRYPTED_FALSE 0x00000000 /* R---V */ +#define NV_MMU_NEW_PTE_PRIVILEGE 5:5 /* RWXVF */ +#define NV_MMU_NEW_PTE_PRIVILEGE_TRUE 0x1 /* RW--V */ +#define NV_MMU_NEW_PTE_PRIVILEGE_FALSE 0x0 /* RW--V */ +#define NV_MMU_NEW_PTE_READ_ONLY 6:6 /* RWXVF */ +#define NV_MMU_NEW_PTE_READ_ONLY_TRUE 0x1 /* RW--V */ +#define NV_MMU_NEW_PTE_READ_ONLY_FALSE 0x0 /* RW--V */ +#define NV_MMU_NEW_PTE_ATOMIC_DISABLE 7:7 /* RWXVF */ +#define NV_MMU_NEW_PTE_ATOMIC_DISABLE_TRUE 0x1 /* RW--V */ +#define NV_MMU_NEW_PTE_ATOMIC_DISABLE_FALSE 0x0 /* RW--V */ +#define NV_MMU_NEW_PTE_ADDRESS_SYS 53:8 /* RWXVF */ +#define NV_MMU_NEW_PTE_ADDRESS_VID (35-3):8 /* RWXVF */ +#define NV_MMU_NEW_PTE_ADDRESS_VID_PEER 35:(36-3) /* RWXVF */ +#define NV_MMU_NEW_PTE_ADDRESS_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_NEW_PTE_ADDRESS_VID_PEER_1 0x00000001 /* RW--V */ +#define NV_MMU_NEW_PTE_ADDRESS_VID_PEER_2 0x00000002 /* RW--V */ +#define NV_MMU_NEW_PTE_ADDRESS_VID_PEER_3 0x00000003 /* RW--V */ +#define NV_MMU_NEW_PTE_ADDRESS_VID_PEER_4 0x00000004 /* RW--V */ +#define NV_MMU_NEW_PTE_ADDRESS_VID_PEER_5 0x00000005 /* RW--V */ +#define NV_MMU_NEW_PTE_ADDRESS_VID_PEER_6 0x00000006 /* RW--V */ +#define NV_MMU_NEW_PTE_ADDRESS_VID_PEER_7 0x00000007 /* RW--V */ +#define NV_MMU_NEW_PTE_COMPTAGLINE (20+35):36 /* RWXVF */ +#define NV_MMU_NEW_PTE_KIND 63:56 /* RWXVF */ +#define NV_MMU_NEW_PTE_ADDRESS_SHIFT 0x0000000c /* */ +#define NV_MMU_NEW_PTE__SIZE 8 +#define NV_MMU_VER2_PDE /* ----G */ +#define NV_MMU_VER2_PDE_IS_PTE 0:0 /* RWXVF */ +#define NV_MMU_VER2_PDE_IS_PTE_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER2_PDE_IS_PTE_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER2_PDE_IS_PDE 0:0 /* RWXVF */ +#define NV_MMU_VER2_PDE_IS_PDE_TRUE 0x0 /* RW--V */ +#define NV_MMU_VER2_PDE_IS_PDE_FALSE 0x1 /* RW--V */ +#define NV_MMU_VER2_PDE_VALID 0:0 /* RWXVF */ +#define NV_MMU_VER2_PDE_VALID_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER2_PDE_VALID_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER2_PDE_APERTURE 2:1 /* RWXVF */ +#define NV_MMU_VER2_PDE_APERTURE_INVALID 0x00000000 /* RW--V */ +#define NV_MMU_VER2_PDE_APERTURE_VIDEO_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_VER2_PDE_APERTURE_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_VER2_PDE_APERTURE_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_VER2_PDE_VOL 3:3 /* RWXVF */ +#define NV_MMU_VER2_PDE_VOL_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_VER2_PDE_VOL_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_VER2_PDE_NO_ATS 5:5 /* RWXVF */ +#define NV_MMU_VER2_PDE_NO_ATS_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER2_PDE_NO_ATS_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER2_PDE_ADDRESS_SYS 53:8 /* RWXVF */ +#define NV_MMU_VER2_PDE_ADDRESS_VID (35-3):8 /* RWXVF */ +#define NV_MMU_VER2_PDE_ADDRESS_VID_PEER 35:(36-3) /* RWXVF */ +#define NV_MMU_VER2_PDE_ADDRESS_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_VER2_PDE_ADDRESS_SHIFT 0x0000000c /* */ +#define NV_MMU_VER2_PDE__SIZE 8 +#define NV_MMU_VER2_DUAL_PDE /* ----G */ +#define NV_MMU_VER2_DUAL_PDE_IS_PTE 0:0 /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_IS_PTE_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_IS_PTE_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_IS_PDE 0:0 /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_IS_PDE_TRUE 0x0 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_IS_PDE_FALSE 0x1 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_VALID 0:0 /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_VALID_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_VALID_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_APERTURE_BIG 2:1 /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_APERTURE_BIG_INVALID 0x00000000 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_APERTURE_BIG_VIDEO_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_APERTURE_BIG_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_APERTURE_BIG_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_VOL_BIG 3:3 /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_VOL_BIG_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_VOL_BIG_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_NO_ATS 5:5 /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_NO_ATS_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_NO_ATS_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_ADDRESS_BIG_SYS 53:(8-4) /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_ADDRESS_BIG_VID (35-3):(8-4) /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_ADDRESS_BIG_VID_PEER 35:(36-3) /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_ADDRESS_BIG_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_APERTURE_SMALL 66:65 /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_APERTURE_SMALL_INVALID 0x00000000 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_APERTURE_SMALL_VIDEO_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_APERTURE_SMALL_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_APERTURE_SMALL_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_VOL_SMALL 67:67 /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_VOL_SMALL_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_VOL_SMALL_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_ADDRESS_SMALL_SYS 117:72 /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_ADDRESS_SMALL_VID (99-3):72 /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_ADDRESS_SMALL_VID_PEER 99:(100-3) /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_ADDRESS_SMALL_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_ADDRESS_SHIFT 0x0000000c /* */ +#define NV_MMU_VER2_DUAL_PDE_ADDRESS_BIG_SHIFT 8 /* */ +#define NV_MMU_VER2_DUAL_PDE__SIZE 16 +#define NV_MMU_VER2_PTE /* ----G */ +#define NV_MMU_VER2_PTE_VALID 0:0 /* RWXVF */ +#define NV_MMU_VER2_PTE_VALID_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER2_PTE_VALID_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER2_PTE_APERTURE 2:1 /* RWXVF */ +#define NV_MMU_VER2_PTE_APERTURE_VIDEO_MEMORY 0x00000000 /* RW--V */ +#define NV_MMU_VER2_PTE_APERTURE_PEER_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_VER2_PTE_APERTURE_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_VER2_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_VER2_PTE_VOL 3:3 /* RWXVF */ +#define NV_MMU_VER2_PTE_VOL_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_VER2_PTE_VOL_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_VER2_PTE_ENCRYPTED 4:4 /* RWXVF */ +#define NV_MMU_VER2_PTE_ENCRYPTED_TRUE 0x00000001 /* R---V */ +#define NV_MMU_VER2_PTE_ENCRYPTED_FALSE 0x00000000 /* R---V */ +#define NV_MMU_VER2_PTE_PRIVILEGE 5:5 /* RWXVF */ +#define NV_MMU_VER2_PTE_PRIVILEGE_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER2_PTE_PRIVILEGE_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER2_PTE_READ_ONLY 6:6 /* RWXVF */ +#define NV_MMU_VER2_PTE_READ_ONLY_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER2_PTE_READ_ONLY_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER2_PTE_ATOMIC_DISABLE 7:7 /* RWXVF */ +#define NV_MMU_VER2_PTE_ATOMIC_DISABLE_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER2_PTE_ATOMIC_DISABLE_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER2_PTE_ADDRESS_SYS 53:8 /* RWXVF */ +#define NV_MMU_VER2_PTE_ADDRESS_VID (35-3):8 /* RWXVF */ +#define NV_MMU_VER2_PTE_ADDRESS_VID_PEER 35:(36-3) /* RWXVF */ +#define NV_MMU_VER2_PTE_ADDRESS_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_VER2_PTE_ADDRESS_VID_PEER_1 0x00000001 /* RW--V */ +#define NV_MMU_VER2_PTE_ADDRESS_VID_PEER_2 0x00000002 /* RW--V */ +#define NV_MMU_VER2_PTE_ADDRESS_VID_PEER_3 0x00000003 /* RW--V */ +#define NV_MMU_VER2_PTE_ADDRESS_VID_PEER_4 0x00000004 /* RW--V */ +#define NV_MMU_VER2_PTE_ADDRESS_VID_PEER_5 0x00000005 /* RW--V */ +#define NV_MMU_VER2_PTE_ADDRESS_VID_PEER_6 0x00000006 /* RW--V */ +#define NV_MMU_VER2_PTE_ADDRESS_VID_PEER_7 0x00000007 /* RW--V */ +#define NV_MMU_VER2_PTE_COMPTAGLINE (20+35):36 /* RWXVF */ +#define NV_MMU_VER2_PTE_KIND 63:56 /* RWXVF */ +#define NV_MMU_VER2_PTE_ADDRESS_SHIFT 0x0000000c /* */ +#define NV_MMU_VER2_PTE__SIZE 8 +#define NV_MMU_VER3_PDE /* ----G */ +#define NV_MMU_VER3_PDE_IS_PTE 0:0 /* RWXVF */ +#define NV_MMU_VER3_PDE_IS_PTE_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER3_PDE_IS_PTE_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER3_PDE_VALID 0:0 /* RWXVF */ +#define NV_MMU_VER3_PDE_VALID_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER3_PDE_VALID_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER3_PDE_APERTURE 2:1 /* RWXVF */ +#define NV_MMU_VER3_PDE_APERTURE_INVALID 0x00000000 /* RW--V */ +#define NV_MMU_VER3_PDE_APERTURE_VIDEO_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_VER3_PDE_APERTURE_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_VER3_PDE_APERTURE_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_VER3_PDE_PCF 5:3 /* RWXVF */ +#define NV_MMU_VER3_PDE_PCF_VALID_CACHED_ATS_ALLOWED__OR__INVALID_ATS_ALLOWED 0x00000000 /* RW--V */ +#define NV_MMU_VER3_PDE_PCF_VALID_CACHED_ATS_ALLOWED 0x00000000 /* RW--V */ +#define NV_MMU_VER3_PDE_PCF_INVALID_ATS_ALLOWED 0x00000000 /* RW--V */ +#define NV_MMU_VER3_PDE_PCF_VALID_UNCACHED_ATS_ALLOWED__OR__SPARSE_ATS_ALLOWED 0x00000001 /* RW--V */ +#define NV_MMU_VER3_PDE_PCF_VALID_UNCACHED_ATS_ALLOWED 0x00000001 /* RW--V */ +#define NV_MMU_VER3_PDE_PCF_SPARSE_ATS_ALLOWED 0x00000001 /* RW--V */ +#define NV_MMU_VER3_PDE_PCF_VALID_CACHED_ATS_NOT_ALLOWED__OR__INVALID_ATS_NOT_ALLOWED 0x00000002 /* RW--V */ +#define NV_MMU_VER3_PDE_PCF_VALID_CACHED_ATS_NOT_ALLOWED 0x00000002 /* RW--V */ +#define NV_MMU_VER3_PDE_PCF_INVALID_ATS_NOT_ALLOWED 0x00000002 /* RW--V */ +#define NV_MMU_VER3_PDE_PCF_VALID_UNCACHED_ATS_NOT_ALLOWED__OR__SPARSE_ATS_NOT_ALLOWED 0x00000003 /* RW--V */ +#define NV_MMU_VER3_PDE_PCF_VALID_UNCACHED_ATS_NOT_ALLOWED 0x00000003 /* RW--V */ +#define NV_MMU_VER3_PDE_PCF_SPARSE_ATS_NOT_ALLOWED 0x00000003 /* RW--V */ +#define NV_MMU_VER3_PDE_ADDRESS 51:12 /* RWXVF */ +#define NV_MMU_VER3_PDE_ADDRESS_SHIFT 0x0000000c /* */ +#define NV_MMU_VER3_PDE__SIZE 8 +#define NV_MMU_VER3_DUAL_PDE /* ----G */ +#define NV_MMU_VER3_DUAL_PDE_IS_PTE 0:0 /* RWXVF */ +#define NV_MMU_VER3_DUAL_PDE_IS_PTE_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_IS_PTE_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_VALID 0:0 /* RWXVF */ +#define NV_MMU_VER3_DUAL_PDE_VALID_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_VALID_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_APERTURE_BIG 2:1 /* RWXVF */ +#define NV_MMU_VER3_DUAL_PDE_APERTURE_BIG_INVALID 0x00000000 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_APERTURE_BIG_VIDEO_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_APERTURE_BIG_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_APERTURE_BIG_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_BIG 5:3 /* RWXVF */ +#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_CACHED_ATS_ALLOWED__OR__INVALID_ATS_ALLOWED 0x00000000 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_CACHED_ATS_ALLOWED 0x00000000 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_INVALID_ATS_ALLOWED 0x00000000 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_UNCACHED_ATS_ALLOWED__OR__SPARSE_ATS_ALLOWED 0x00000001 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_UNCACHED_ATS_ALLOWED 0x00000001 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_SPARSE_ATS_ALLOWED 0x00000001 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_CACHED_ATS_NOT_ALLOWED__OR__INVALID_ATS_NOT_ALLOWED 0x00000002 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_CACHED_ATS_NOT_ALLOWED 0x00000002 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_INVALID_ATS_NOT_ALLOWED 0x00000002 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_UNCACHED_ATS_NOT_ALLOWED__OR__SPARSE_ATS_NOT_ALLOWED 0x00000003 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_UNCACHED_ATS_NOT_ALLOWED 0x00000003 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_SPARSE_ATS_NOT_ALLOWED 0x00000003 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_ADDRESS_BIG 51:8 /* RWXVF */ +#define NV_MMU_VER3_DUAL_PDE_APERTURE_SMALL 66:65 /* RWXVF */ +#define NV_MMU_VER3_DUAL_PDE_APERTURE_SMALL_INVALID 0x00000000 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_APERTURE_SMALL_VIDEO_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_APERTURE_SMALL_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_APERTURE_SMALL_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL 69:67 /* RWXVF */ +#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_CACHED_ATS_ALLOWED__OR__INVALID_ATS_ALLOWED 0x00000000 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_CACHED_ATS_ALLOWED 0x00000000 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_INVALID_ATS_ALLOWED 0x00000000 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_UNCACHED_ATS_ALLOWED__OR__SPARSE_ATS_ALLOWED 0x00000001 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_UNCACHED_ATS_ALLOWED 0x00000001 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_SPARSE_ATS_ALLOWED 0x00000001 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_CACHED_ATS_NOT_ALLOWED__OR__INVALID_ATS_NOT_ALLOWED 0x00000002 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_CACHED_ATS_NOT_ALLOWED 0x00000002 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_INVALID_ATS_NOT_ALLOWED 0x00000002 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_UNCACHED_ATS_NOT_ALLOWED__OR__SPARSE_ATS_NOT_ALLOWED 0x00000003 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_UNCACHED_ATS_NOT_ALLOWED 0x00000003 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_SPARSE_ATS_NOT_ALLOWED 0x00000003 /* RW--V */ +#define NV_MMU_VER3_DUAL_PDE_ADDRESS_SMALL 115:76 /* RWXVF */ +#define NV_MMU_VER3_DUAL_PDE_ADDRESS_SHIFT 0x0000000c /* */ +#define NV_MMU_VER3_DUAL_PDE_ADDRESS_BIG_SHIFT 8 /* */ +#define NV_MMU_VER3_DUAL_PDE__SIZE 16 +#define NV_MMU_VER3_PTE /* ----G */ +#define NV_MMU_VER3_PTE_VALID 0:0 /* RWXVF */ +#define NV_MMU_VER3_PTE_VALID_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER3_PTE_VALID_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER3_PTE_APERTURE 2:1 /* RWXVF */ +#define NV_MMU_VER3_PTE_APERTURE_VIDEO_MEMORY 0x00000000 /* RW--V */ +#define NV_MMU_VER3_PTE_APERTURE_PEER_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_VER3_PTE_APERTURE_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_VER3_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF 7:3 /* RWXVF */ +#define NV_MMU_VER3_PTE_PCF_INVALID 0x00000000 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_SPARSE 0x00000001 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_MAPPING_NOWHERE 0x00000002 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_NO_VALID_4KB_PAGE 0x00000003 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_REGULAR_RW_ATOMIC_CACHED_ACE 0x00000000 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_REGULAR_RW_ATOMIC_UNCACHED_ACE 0x00000001 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RW_ATOMIC_CACHED_ACE 0x00000002 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RW_ATOMIC_UNCACHED_ACE 0x00000003 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_REGULAR_RO_ATOMIC_CACHED_ACE 0x00000004 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_REGULAR_RO_ATOMIC_UNCACHED_ACE 0x00000005 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_ATOMIC_CACHED_ACE 0x00000006 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_ATOMIC_UNCACHED_ACE 0x00000007 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_REGULAR_RW_NO_ATOMIC_CACHED_ACE 0x00000008 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_REGULAR_RW_NO_ATOMIC_UNCACHED_ACE 0x00000009 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RW_NO_ATOMIC_CACHED_ACE 0x0000000A /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RW_NO_ATOMIC_UNCACHED_ACE 0x0000000B /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_REGULAR_RO_NO_ATOMIC_CACHED_ACE 0x0000000C /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_REGULAR_RO_NO_ATOMIC_UNCACHED_ACE 0x0000000D /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_NO_ATOMIC_CACHED_ACE 0x0000000E /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_NO_ATOMIC_UNCACHED_ACE 0x0000000F /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_REGULAR_RW_ATOMIC_CACHED_ACD 0x00000010 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_REGULAR_RW_ATOMIC_UNCACHED_ACD 0x00000011 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RW_ATOMIC_CACHED_ACD 0x00000012 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RW_ATOMIC_UNCACHED_ACD 0x00000013 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_REGULAR_RO_ATOMIC_CACHED_ACD 0x00000014 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_REGULAR_RO_ATOMIC_UNCACHED_ACD 0x00000015 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_ATOMIC_CACHED_ACD 0x00000016 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_ATOMIC_UNCACHED_ACD 0x00000017 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_REGULAR_RW_NO_ATOMIC_CACHED_ACD 0x00000018 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_REGULAR_RW_NO_ATOMIC_UNCACHED_ACD 0x00000019 /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RW_NO_ATOMIC_CACHED_ACD 0x0000001A /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RW_NO_ATOMIC_UNCACHED_ACD 0x0000001B /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_REGULAR_RO_NO_ATOMIC_CACHED_ACD 0x0000001C /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_REGULAR_RO_NO_ATOMIC_UNCACHED_ACD 0x0000001D /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_NO_ATOMIC_CACHED_ACD 0x0000001E /* RW--V */ +#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RO_NO_ATOMIC_UNCACHED_ACD 0x0000001F /* RW--V */ +#define NV_MMU_VER3_PTE_KIND 11:8 /* RWXVF */ +#define NV_MMU_VER3_PTE_ADDRESS 51:12 /* RWXVF */ +#define NV_MMU_VER3_PTE_ADDRESS_SYS 51:12 /* RWXVF */ +#define NV_MMU_VER3_PTE_ADDRESS_PEER 51:12 /* RWXVF */ +#define NV_MMU_VER3_PTE_ADDRESS_VID 39:12 /* RWXVF */ +#define NV_MMU_VER3_PTE_PEER_ID 63:(64-3) /* RWXVF */ +#define NV_MMU_VER3_PTE_PEER_ID_0 0x00000000 /* RW--V */ +#define NV_MMU_VER3_PTE_PEER_ID_1 0x00000001 /* RW--V */ +#define NV_MMU_VER3_PTE_PEER_ID_2 0x00000002 /* RW--V */ +#define NV_MMU_VER3_PTE_PEER_ID_3 0x00000003 /* RW--V */ +#define NV_MMU_VER3_PTE_PEER_ID_4 0x00000004 /* RW--V */ +#define NV_MMU_VER3_PTE_PEER_ID_5 0x00000005 /* RW--V */ +#define NV_MMU_VER3_PTE_PEER_ID_6 0x00000006 /* RW--V */ +#define NV_MMU_VER3_PTE_PEER_ID_7 0x00000007 /* RW--V */ +#define NV_MMU_VER3_PTE_ADDRESS_SHIFT 0x0000000c /* */ +#define NV_MMU_VER3_PTE__SIZE 8 +#define NV_MMU_CLIENT /* ----G */ +#define NV_MMU_CLIENT_KIND 2:0 /* RWXVF */ +#define NV_MMU_CLIENT_KIND_Z16 0x1 /* R---V */ +#define NV_MMU_CLIENT_KIND_S8 0x2 /* R---V */ +#define NV_MMU_CLIENT_KIND_S8Z24 0x3 /* R---V */ +#define NV_MMU_CLIENT_KIND_ZF32_X24S8 0x4 /* R---V */ +#define NV_MMU_CLIENT_KIND_Z24S8 0x5 /* R---V */ +#define NV_MMU_CLIENT_KIND_GENERIC_MEMORY 0x6 /* R---V */ +#define NV_MMU_CLIENT_KIND_INVALID 0x7 /* R---V */ +#endif // __gh100_dev_mmu_h__ diff --git a/src/nouveau/headers/nvidia/hwref/maxwell/gm107/dev_mmu.h b/src/nouveau/headers/nvidia/hwref/maxwell/gm107/dev_mmu.h new file mode 100644 index 00000000000..28c47cfb977 --- /dev/null +++ b/src/nouveau/headers/nvidia/hwref/maxwell/gm107/dev_mmu.h @@ -0,0 +1,339 @@ +/******************************************************************************* + Copyright (c) 2003-2016 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + + +#ifndef __gm107_dev_mmu_h__ +#define __gm107_dev_mmu_h__ +/* This file is autogenerated. Do not edit */ +#define NV_MMU_PDE /* ----G */ +#define NV_MMU_PDE_APERTURE_BIG (0*32+1):(0*32+0) /* RWXVF */ +#define NV_MMU_PDE_APERTURE_BIG_INVALID 0x00000000 /* RW--V */ +#define NV_MMU_PDE_APERTURE_BIG_VIDEO_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_PDE_APERTURE_BIG_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_PDE_APERTURE_BIG_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_PDE_SIZE (0*32+3):(0*32+2) /* RWXVF */ +#define NV_MMU_PDE_SIZE_FULL 0x00000000 /* RW--V */ +#define NV_MMU_PDE_SIZE_HALF 0x00000001 /* RW--V */ +#define NV_MMU_PDE_SIZE_QUARTER 0x00000002 /* RW--V */ +#define NV_MMU_PDE_SIZE_EIGHTH 0x00000003 /* RW--V */ +#define NV_MMU_PDE_ADDRESS_BIG_SYS (0*32+31):(0*32+4) /* RWXVF */ +#define NV_MMU_PDE_ADDRESS_BIG_VID (0*32+31-3):(0*32+4) /* RWXVF */ +#define NV_MMU_PDE_ADDRESS_BIG_VID_PEER (0*32+31):(0*32+32-3) /* RWXVF */ +#define NV_MMU_PDE_ADDRESS_BIG_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_PDE_APERTURE_SMALL (1*32+1):(1*32+0) /* RWXVF */ +#define NV_MMU_PDE_APERTURE_SMALL_INVALID 0x00000000 /* RW--V */ +#define NV_MMU_PDE_APERTURE_SMALL_VIDEO_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_PDE_APERTURE_SMALL_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_PDE_APERTURE_SMALL_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_PDE_VOL_SMALL (1*32+2):(1*32+2) /* RWXVF */ +#define NV_MMU_PDE_VOL_SMALL_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_PDE_VOL_SMALL_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_PDE_VOL_BIG (1*32+3):(1*32+3) /* RWXVF */ +#define NV_MMU_PDE_VOL_BIG_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_PDE_VOL_BIG_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_PDE_ADDRESS_SMALL_SYS (1*32+31):(1*32+4) /* RWXVF */ +#define NV_MMU_PDE_ADDRESS_SMALL_VID (1*32+31-3):(1*32+4) /* RWXVF */ +#define NV_MMU_PDE_ADDRESS_SMALL_VID_PEER (1*32+31):(1*32+32-3) /* RWXVF */ +#define NV_MMU_PDE_ADDRESS_SMALL_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_PDE_ADDRESS_SHIFT 0x0000000c /* */ +#define NV_MMU_PDE__SIZE 8 +#define NV_MMU_PTE /* ----G */ +#define NV_MMU_PTE_VALID (0*32+0):(0*32+0) /* RWXVF */ +#define NV_MMU_PTE_VALID_TRUE 0x1 /* RW--V */ +#define NV_MMU_PTE_VALID_FALSE 0x0 /* RW--V */ +#define NV_MMU_PTE_PRIVILEGE (0*32+1):(0*32+1) /* RWXVF */ +#define NV_MMU_PTE_PRIVILEGE_TRUE 0x1 /* RW--V */ +#define NV_MMU_PTE_PRIVILEGE_FALSE 0x0 /* RW--V */ +#define NV_MMU_PTE_READ_ONLY (0*32+2):(0*32+2) /* RWXVF */ +#define NV_MMU_PTE_READ_ONLY_TRUE 0x1 /* RW--V */ +#define NV_MMU_PTE_READ_ONLY_FALSE 0x0 /* RW--V */ +#define NV_MMU_PTE_ENCRYPTED (0*32+3):(0*32+3) /* RWXVF */ +#define NV_MMU_PTE_ENCRYPTED_TRUE 0x00000001 /* R---V */ +#define NV_MMU_PTE_ENCRYPTED_FALSE 0x00000000 /* R---V */ +#define NV_MMU_PTE_ADDRESS_SYS (0*32+31):(0*32+4) /* RWXVF */ +#define NV_MMU_PTE_ADDRESS_VID (0*32+31-3):(0*32+4) /* RWXVF */ +#define NV_MMU_PTE_ADDRESS_VID_PEER (0*32+31):(0*32+32-3) /* RWXVF */ +#define NV_MMU_PTE_ADDRESS_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_PTE_ADDRESS_VID_PEER_1 0x00000001 /* RW--V */ +#define NV_MMU_PTE_ADDRESS_VID_PEER_2 0x00000002 /* RW--V */ +#define NV_MMU_PTE_ADDRESS_VID_PEER_3 0x00000003 /* RW--V */ +#define NV_MMU_PTE_ADDRESS_VID_PEER_4 0x00000004 /* RW--V */ +#define NV_MMU_PTE_ADDRESS_VID_PEER_5 0x00000005 /* RW--V */ +#define NV_MMU_PTE_ADDRESS_VID_PEER_6 0x00000006 /* RW--V */ +#define NV_MMU_PTE_ADDRESS_VID_PEER_7 0x00000007 /* RW--V */ +#define NV_MMU_PTE_VOL (1*32+0):(1*32+0) /* RWXVF */ +#define NV_MMU_PTE_VOL_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_PTE_VOL_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_PTE_APERTURE (1*32+2):(1*32+1) /* RWXVF */ +#define NV_MMU_PTE_APERTURE_VIDEO_MEMORY 0x00000000 /* RW--V */ +#define NV_MMU_PTE_APERTURE_PEER_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_PTE_APERTURE_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_PTE_LOCK (1*32+3):(1*32+3) /* RWXVF */ +#define NV_MMU_PTE_LOCK_TRUE 0x1 /* RW--V */ +#define NV_MMU_PTE_LOCK_FALSE 0x0 /* RW--V */ +#define NV_MMU_PTE_COMPTAGLINE (1*32+28):(1*32+12) /* RWXVF */ +#define NV_MMU_PTE_READ_DISABLE (1*32+30):(1*32+30) /* RWXVF */ +#define NV_MMU_PTE_READ_DISABLE_TRUE 0x1 /* RW--V */ +#define NV_MMU_PTE_READ_DISABLE_FALSE 0x0 /* RW--V */ +#define NV_MMU_PTE_WRITE_DISABLE (1*32+31):(1*32+31) /* RWXVF */ +#define NV_MMU_PTE_WRITE_DISABLE_TRUE 0x1 /* RW--V */ +#define NV_MMU_PTE_WRITE_DISABLE_FALSE 0x0 /* RW--V */ +#define NV_MMU_PTE_ADDRESS_SHIFT 0x0000000c /* */ +#define NV_MMU_PTE__SIZE 8 +#define NV_MMU_PTE_COMPTAGS_NONE 0x0 /* */ +#define NV_MMU_PTE_COMPTAGS_1 0x1 /* */ +#define NV_MMU_PTE_COMPTAGS_2 0x2 /* */ +#define NV_MMU_PTE_KIND (1*32+11):(1*32+4) /* RWXVF */ +#define NV_MMU_PTE_KIND_INVALID 0xff /* R---V */ +#define NV_MMU_PTE_KIND_PITCH 0x00 /* R---V */ +#define NV_MMU_PTE_KIND_Z16 0x01 /* R---V */ +#define NV_MMU_PTE_KIND_Z16_2C 0x02 /* R---V */ +#define NV_MMU_PTE_KIND_Z16_MS2_2C 0x03 /* R---V */ +#define NV_MMU_PTE_KIND_Z16_MS4_2C 0x04 /* R---V */ +#define NV_MMU_PTE_KIND_Z16_MS8_2C 0x05 /* R---V */ +#define NV_MMU_PTE_KIND_Z16_MS16_2C 0x06 /* R---V */ +#define NV_MMU_PTE_KIND_Z16_2Z 0x07 /* R---V */ +#define NV_MMU_PTE_KIND_Z16_MS2_2Z 0x08 /* R---V */ +#define NV_MMU_PTE_KIND_Z16_MS4_2Z 0x09 /* R---V */ +#define NV_MMU_PTE_KIND_Z16_MS8_2Z 0x0a /* R---V */ +#define NV_MMU_PTE_KIND_Z16_MS16_2Z 0x0b /* R---V */ +#define NV_MMU_PTE_KIND_Z16_4CZ 0x0c /* R---V */ +#define NV_MMU_PTE_KIND_Z16_MS2_4CZ 0x0d /* R---V */ +#define NV_MMU_PTE_KIND_Z16_MS4_4CZ 0x0e /* R---V */ +#define NV_MMU_PTE_KIND_Z16_MS8_4CZ 0x0f /* R---V */ +#define NV_MMU_PTE_KIND_Z16_MS16_4CZ 0x10 /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24 0x11 /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_1Z 0x12 /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_MS2_1Z 0x13 /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_MS4_1Z 0x14 /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_MS8_1Z 0x15 /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_MS16_1Z 0x16 /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_2CZ 0x17 /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_MS2_2CZ 0x18 /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_MS4_2CZ 0x19 /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_MS8_2CZ 0x1a /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_MS16_2CZ 0x1b /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_2CS 0x1c /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_MS2_2CS 0x1d /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_MS4_2CS 0x1e /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_MS8_2CS 0x1f /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_MS16_2CS 0x20 /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_4CSZV 0x21 /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_MS2_4CSZV 0x22 /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_MS4_4CSZV 0x23 /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_MS8_4CSZV 0x24 /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_MS16_4CSZV 0x25 /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12 0x26 /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4 0x27 /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8 0x28 /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24 0x29 /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_1ZV 0x2e /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_1ZV 0x2f /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_1ZV 0x30 /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_1ZV 0x31 /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2CS 0x32 /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2CS 0x33 /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2CS 0x34 /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2CS 0x35 /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2CZV 0x3a /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2CZV 0x3b /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2CZV 0x3c /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2CZV 0x3d /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2ZV 0x3e /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2ZV 0x3f /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2ZV 0x40 /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2ZV 0x41 /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_4CSZV 0x42 /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_4CSZV 0x43 /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_4CSZV 0x44 /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_4CSZV 0x45 /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8 0x46 /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_1Z 0x47 /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_MS2_1Z 0x48 /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_MS4_1Z 0x49 /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_MS8_1Z 0x4a /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_MS16_1Z 0x4b /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_2CS 0x4c /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_MS2_2CS 0x4d /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_MS4_2CS 0x4e /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_MS8_2CS 0x4f /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_MS16_2CS 0x50 /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_2CZ 0x51 /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_MS2_2CZ 0x52 /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_MS4_2CZ 0x53 /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_MS8_2CZ 0x54 /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_MS16_2CZ 0x55 /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_4CSZV 0x56 /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_MS2_4CSZV 0x57 /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_MS4_4CSZV 0x58 /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_MS8_4CSZV 0x59 /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_MS16_4CSZV 0x5a /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12 0x5b /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4 0x5c /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8 0x5d /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24 0x5e /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_1ZV 0x63 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_1ZV 0x64 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_1ZV 0x65 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_1ZV 0x66 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2CS 0x67 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2CS 0x68 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2CS 0x69 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2CS 0x6a /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2CZV 0x6f /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2CZV 0x70 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2CZV 0x71 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2CZV 0x72 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2ZV 0x73 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2ZV 0x74 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2ZV 0x75 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2ZV 0x76 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_4CSZV 0x77 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_4CSZV 0x78 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_4CSZV 0x79 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_4CSZV 0x7a /* R---V */ +#define NV_MMU_PTE_KIND_ZF32 0x7b /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_1Z 0x7c /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_MS2_1Z 0x7d /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_MS4_1Z 0x7e /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_MS8_1Z 0x7f /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_MS16_1Z 0x80 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_2CS 0x81 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_MS2_2CS 0x82 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_MS4_2CS 0x83 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_MS8_2CS 0x84 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_MS16_2CS 0x85 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_2CZ 0x86 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_MS2_2CZ 0x87 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_MS4_2CZ 0x88 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_MS8_2CZ 0x89 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_MS16_2CZ 0x8a /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12 0x8b /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4 0x8c /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8 0x8d /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24 0x8e /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1CS 0x8f /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1CS 0x90 /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1CS 0x91 /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1CS 0x92 /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1ZV 0x97 /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1ZV 0x98 /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1ZV 0x99 /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1ZV 0x9a /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1CZV 0x9b /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1CZV 0x9c /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1CZV 0x9d /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1CZV 0x9e /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_2CS 0x9f /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_2CS 0xa0 /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_2CS 0xa1 /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_2CS 0xa2 /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_2CSZV 0xa3 /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_2CSZV 0xa4 /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_2CSZV 0xa5 /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_2CSZV 0xa6 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12 0xa7 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4 0xa8 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8 0xa9 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24 0xaa /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1CS 0xab /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1CS 0xac /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1CS 0xad /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1CS 0xae /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1ZV 0xb3 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1ZV 0xb4 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1ZV 0xb5 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1ZV 0xb6 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1CZV 0xb7 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1CZV 0xb8 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1CZV 0xb9 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1CZV 0xba /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_2CS 0xbb /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_2CS 0xbc /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_2CS 0xbd /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_2CS 0xbe /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_2CSZV 0xbf /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_2CSZV 0xc0 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_2CSZV 0xc1 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_2CSZV 0xc2 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8 0xc3 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8_1CS 0xc4 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_1CS 0xc5 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_1CS 0xc6 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_1CS 0xc7 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_1CS 0xc8 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8_2CSZV 0xce /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_2CSZV 0xcf /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_2CSZV 0xd0 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_2CSZV 0xd1 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_2CSZV 0xd2 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8_2CS 0xd3 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_2CS 0xd4 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_2CS 0xd5 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_2CS 0xd6 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_2CS 0xd7 /* R---V */ +#define NV_MMU_PTE_KIND_GENERIC_16BX2 0xfe /* R---V */ +#define NV_MMU_PTE_KIND_C32_2C 0xd8 /* R---V */ +#define NV_MMU_PTE_KIND_C32_2CBR 0xd9 /* R---V */ +#define NV_MMU_PTE_KIND_C32_2CBA 0xda /* R---V */ +#define NV_MMU_PTE_KIND_C32_2CRA 0xdb /* R---V */ +#define NV_MMU_PTE_KIND_C32_2BRA 0xdc /* R---V */ +#define NV_MMU_PTE_KIND_C32_MS2_2C 0xdd /* R---V */ +#define NV_MMU_PTE_KIND_C32_MS2_2CBR 0xde /* R---V */ +#define NV_MMU_PTE_KIND_C32_MS2_2CRA 0xcc /* R---V */ +#define NV_MMU_PTE_KIND_C32_MS4_2C 0xdf /* R---V */ +#define NV_MMU_PTE_KIND_C32_MS4_2CBR 0xe0 /* R---V */ +#define NV_MMU_PTE_KIND_C32_MS4_2CBA 0xe1 /* R---V */ +#define NV_MMU_PTE_KIND_C32_MS4_2CRA 0xe2 /* R---V */ +#define NV_MMU_PTE_KIND_C32_MS4_2BRA 0xe3 /* R---V */ +#define NV_MMU_PTE_KIND_C32_MS8_MS16_2C 0xe4 /* R---V */ +#define NV_MMU_PTE_KIND_C32_MS8_MS16_2CRA 0xe5 /* R---V */ +#define NV_MMU_PTE_KIND_C64_2C 0xe6 /* R---V */ +#define NV_MMU_PTE_KIND_C64_2CBR 0xe7 /* R---V */ +#define NV_MMU_PTE_KIND_C64_2CBA 0xe8 /* R---V */ +#define NV_MMU_PTE_KIND_C64_2CRA 0xe9 /* R---V */ +#define NV_MMU_PTE_KIND_C64_2BRA 0xea /* R---V */ +#define NV_MMU_PTE_KIND_C64_MS2_2C 0xeb /* R---V */ +#define NV_MMU_PTE_KIND_C64_MS2_2CBR 0xec /* R---V */ +#define NV_MMU_PTE_KIND_C64_MS2_2CRA 0xcd /* R---V */ +#define NV_MMU_PTE_KIND_C64_MS4_2C 0xed /* R---V */ +#define NV_MMU_PTE_KIND_C64_MS4_2CBR 0xee /* R---V */ +#define NV_MMU_PTE_KIND_C64_MS4_2CBA 0xef /* R---V */ +#define NV_MMU_PTE_KIND_C64_MS4_2CRA 0xf0 /* R---V */ +#define NV_MMU_PTE_KIND_C64_MS4_2BRA 0xf1 /* R---V */ +#define NV_MMU_PTE_KIND_C64_MS8_MS16_2C 0xf2 /* R---V */ +#define NV_MMU_PTE_KIND_C64_MS8_MS16_2CRA 0xf3 /* R---V */ +#define NV_MMU_PTE_KIND_C128_2C 0xf4 /* R---V */ +#define NV_MMU_PTE_KIND_C128_2CR 0xf5 /* R---V */ +#define NV_MMU_PTE_KIND_C128_MS2_2C 0xf6 /* R---V */ +#define NV_MMU_PTE_KIND_C128_MS2_2CR 0xf7 /* R---V */ +#define NV_MMU_PTE_KIND_C128_MS4_2C 0xf8 /* R---V */ +#define NV_MMU_PTE_KIND_C128_MS4_2CR 0xf9 /* R---V */ +#define NV_MMU_PTE_KIND_C128_MS8_MS16_2C 0xfa /* R---V */ +#define NV_MMU_PTE_KIND_C128_MS8_MS16_2CR 0xfb /* R---V */ +#define NV_MMU_PTE_KIND_X8C24 0xfc /* R---V */ +#define NV_MMU_PTE_KIND_PITCH_NO_SWIZZLE 0xfd /* R---V */ +#define NV_MMU_PTE_KIND_SMSKED_MESSAGE 0xca /* R---V */ +#define NV_MMU_PTE_KIND_SMHOST_MESSAGE 0xcb /* R---V */ +#endif // __gm107_dev_mmu_h__ diff --git a/src/nouveau/headers/nvidia/hwref/pascal/gp100/dev_fault.h b/src/nouveau/headers/nvidia/hwref/pascal/gp100/dev_fault.h new file mode 100644 index 00000000000..72ff29eead2 --- /dev/null +++ b/src/nouveau/headers/nvidia/hwref/pascal/gp100/dev_fault.h @@ -0,0 +1,203 @@ +/******************************************************************************* + Copyright (c) 2003-2016 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + + +#ifndef __gp100_dev_fault_h__ +#define __gp100_dev_fault_h__ +/* This file is autogenerated. Do not edit */ +#define NV_PFAULT_MMU_ENG_ID_GRAPHICS 0 /* */ +#define NV_PFAULT_MMU_ENG_ID_DISPLAY 1 /* */ +#define NV_PFAULT_MMU_ENG_ID_IFB 3 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1 4 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2 5 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST0 6 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST1 7 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST2 8 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST3 9 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST4 10 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST5 11 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST6 12 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST7 13 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST8 14 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST9 15 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST10 16 /* */ +#define NV_PFAULT_MMU_ENG_ID_SEC 18 /* */ +#define NV_PFAULT_MMU_ENG_ID_PERF 19 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVDEC 2 /* */ +#define NV_PFAULT_MMU_ENG_ID_GRCOPY 27 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE0 21 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE1 22 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE2 27 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE3 28 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE4 29 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE5 30 /* */ +#define NV_PFAULT_MMU_ENG_ID_PWR_PMU 23 /* */ +#define NV_PFAULT_MMU_ENG_ID_PTP 24 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVENC 25 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVENC0 25 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVENC1 17 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVENC2 20 /* */ +#define NV_PFAULT_MMU_ENG_ID_PHYSICAL 31 /* */ +#define NV_PFAULT_FAULT_TYPE 4:0 /* */ +#define NV_PFAULT_FAULT_TYPE_PDE 0x00000000 /* */ +#define NV_PFAULT_FAULT_TYPE_PDE_SIZE 0x00000001 /* */ +#define NV_PFAULT_FAULT_TYPE_PTE 0x00000002 /* */ +#define NV_PFAULT_FAULT_TYPE_VA_LIMIT_VIOLATION 0x00000003 /* */ +#define NV_PFAULT_FAULT_TYPE_UNBOUND_INST_BLOCK 0x00000004 /* */ +#define NV_PFAULT_FAULT_TYPE_PRIV_VIOLATION 0x00000005 /* */ +#define NV_PFAULT_FAULT_TYPE_RO_VIOLATION 0x00000006 /* */ +#define NV_PFAULT_FAULT_TYPE_PITCH_MASK_VIOLATION 0x00000008 /* */ +#define NV_PFAULT_FAULT_TYPE_WORK_CREATION 0x00000009 /* */ +#define NV_PFAULT_FAULT_TYPE_UNSUPPORTED_APERTURE 0x0000000a /* */ +#define NV_PFAULT_FAULT_TYPE_COMPRESSION_FAILURE 0x0000000b /* */ +#define NV_PFAULT_FAULT_TYPE_UNSUPPORTED_KIND 0x0000000c /* */ +#define NV_PFAULT_FAULT_TYPE_REGION_VIOLATION 0x0000000d /* */ +#define NV_PFAULT_FAULT_TYPE_POISONED 0x0000000e /* */ +#define NV_PFAULT_FAULT_TYPE_ATOMIC_VIOLATION 0x0000000f /* */ +#define NV_PFAULT_CLIENT 14:8 /* */ +#define NV_PFAULT_CLIENT_GPC_L1_0 0x00000000 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_0 0x00000001 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_0 0x00000002 /* */ +#define NV_PFAULT_CLIENT_GPC_L1_1 0x00000003 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_1 0x00000004 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_1 0x00000005 /* */ +#define NV_PFAULT_CLIENT_GPC_L1_2 0x00000006 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_2 0x00000007 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_2 0x00000008 /* */ +#define NV_PFAULT_CLIENT_GPC_L1_3 0x00000009 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_3 0x0000000A /* */ +#define NV_PFAULT_CLIENT_GPC_PE_3 0x0000000B /* */ +#define NV_PFAULT_CLIENT_GPC_RAST 0x0000000C /* */ +#define NV_PFAULT_CLIENT_GPC_GCC 0x0000000D /* */ +#define NV_PFAULT_CLIENT_GPC_GPCCS 0x0000000E /* */ +#define NV_PFAULT_CLIENT_GPC_PROP_0 0x0000000F /* */ +#define NV_PFAULT_CLIENT_GPC_PROP_1 0x00000010 /* */ +#define NV_PFAULT_CLIENT_GPC_PROP_2 0x00000011 /* */ +#define NV_PFAULT_CLIENT_GPC_PROP_3 0x00000012 /* */ +#define NV_PFAULT_CLIENT_GPC_L1_4 0x00000014 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_4 0x00000015 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_4 0x00000016 /* */ +#define NV_PFAULT_CLIENT_GPC_L1_5 0x00000017 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_5 0x00000018 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_5 0x00000019 /* */ +#define NV_PFAULT_CLIENT_GPC_L1_6 0x0000001A /* */ +#define NV_PFAULT_CLIENT_GPC_T1_6 0x0000001B /* */ +#define NV_PFAULT_CLIENT_GPC_PE_6 0x0000001C /* */ +#define NV_PFAULT_CLIENT_GPC_L1_7 0x0000001D /* */ +#define NV_PFAULT_CLIENT_GPC_T1_7 0x0000001E /* */ +#define NV_PFAULT_CLIENT_GPC_PE_7 0x0000001F /* */ +#define NV_PFAULT_CLIENT_GPC_L1_8 0x00000020 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_8 0x00000021 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_8 0x00000022 /* */ +#define NV_PFAULT_CLIENT_GPC_L1_9 0x00000023 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_9 0x00000024 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_9 0x00000025 /* */ +#define NV_PFAULT_CLIENT_GPC_L1_10 0x00000026 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_10 0x00000027 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_10 0x00000028 /* */ +#define NV_PFAULT_CLIENT_GPC_L1_11 0x00000029 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_11 0x0000002A /* */ +#define NV_PFAULT_CLIENT_GPC_PE_11 0x0000002B /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_0 0x00000030 /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_1 0x00000031 /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_2 0x00000032 /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_3 0x00000033 /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_4 0x00000034 /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_5 0x00000035 /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_6 0x00000036 /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_7 0x00000037 /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_8 0x00000038 /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_9 0x00000039 /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_10 0x0000003A /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_11 0x0000003B /* */ +#define NV_PFAULT_CLIENT_GPC_GPM 0x00000013 /* */ +#define NV_PFAULT_CLIENT_GPC_LTP_UTLB_0 0x00000014 /* */ +#define NV_PFAULT_CLIENT_GPC_LTP_UTLB_1 0x00000015 /* */ +#define NV_PFAULT_CLIENT_GPC_LTP_UTLB_2 0x00000016 /* */ +#define NV_PFAULT_CLIENT_GPC_LTP_UTLB_3 0x00000017 /* */ +#define NV_PFAULT_CLIENT_GPC_RGG_UTLB 0x00000018 /* */ +#define NV_PFAULT_CLIENT_HUB_CE0 0x00000001 /* */ +#define NV_PFAULT_CLIENT_HUB_CE1 0x00000002 /* */ +#define NV_PFAULT_CLIENT_HUB_DNISO 0x00000003 /* */ +#define NV_PFAULT_CLIENT_HUB_FE 0x00000004 /* */ +#define NV_PFAULT_CLIENT_HUB_FECS 0x00000005 /* */ +#define NV_PFAULT_CLIENT_HUB_HOST 0x00000006 /* */ +#define NV_PFAULT_CLIENT_HUB_HOST_CPU 0x00000007 /* */ +#define NV_PFAULT_CLIENT_HUB_HOST_CPU_NB 0x00000008 /* */ +#define NV_PFAULT_CLIENT_HUB_ISO 0x00000009 /* */ +#define NV_PFAULT_CLIENT_HUB_MMU 0x0000000A /* */ +#define NV_PFAULT_CLIENT_HUB_NVDEC 0x0000000B /* */ +#define NV_PFAULT_CLIENT_HUB_NVENC1 0x0000000D /* */ +#define NV_PFAULT_CLIENT_HUB_NVENC2 0x00000033 /* */ +#define NV_PFAULT_CLIENT_HUB_NISO 0x0000000E /* */ +#define NV_PFAULT_CLIENT_HUB_P2P 0x0000000F /* */ +#define NV_PFAULT_CLIENT_HUB_PD 0x00000010 /* */ +#define NV_PFAULT_CLIENT_HUB_PERF 0x00000011 /* */ +#define NV_PFAULT_CLIENT_HUB_PMU 0x00000012 /* */ +#define NV_PFAULT_CLIENT_HUB_RASTERTWOD 0x00000013 /* */ +#define NV_PFAULT_CLIENT_HUB_SCC 0x00000014 /* */ +#define NV_PFAULT_CLIENT_HUB_SCC_NB 0x00000015 /* */ +#define NV_PFAULT_CLIENT_HUB_SEC 0x00000016 /* */ +#define NV_PFAULT_CLIENT_HUB_SSYNC 0x00000017 /* */ +#define NV_PFAULT_CLIENT_HUB_VIP 0x00000000 /* */ +#define NV_PFAULT_CLIENT_HUB_GRCOPY 0x00000018 /* */ +#define NV_PFAULT_CLIENT_HUB_CE2 0x00000018 /* */ +#define NV_PFAULT_CLIENT_HUB_XV 0x00000019 /* */ +#define NV_PFAULT_CLIENT_HUB_MMU_NB 0x0000001A /* */ +#define NV_PFAULT_CLIENT_HUB_NVENC 0x0000001B /* */ +#define NV_PFAULT_CLIENT_HUB_NVENC0 0x0000001B /* */ +#define NV_PFAULT_CLIENT_HUB_DFALCON 0x0000001C /* */ +#define NV_PFAULT_CLIENT_HUB_SKED 0x0000001D /* */ +#define NV_PFAULT_CLIENT_HUB_AFALCON 0x0000001E /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE0 0x00000020 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE1 0x00000021 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE2 0x00000022 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE3 0x00000023 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE4 0x00000024 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE5 0x00000025 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE6 0x00000026 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE7 0x00000027 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE8 0x00000028 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE9 0x00000029 /* */ +#define NV_PFAULT_CLIENT_HUB_HSHUB 0x0000002A /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X0 0x0000002B /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X1 0x0000002C /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X2 0x0000002D /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X3 0x0000002E /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X4 0x0000002F /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X5 0x00000030 /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X6 0x00000031 /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X7 0x00000032 /* */ +#define NV_PFAULT_CLIENT_HUB_VPR_SCRUBBER0 0x00000034 /* */ +#define NV_PFAULT_CLIENT_HUB_VPR_SCRUBBER1 0x00000035 /* */ +#define NV_PFAULT_CLIENT_HUB_DONT_CARE 0x0000001F /* */ +#define NV_PFAULT_ACCESS_TYPE 18:16 /* */ +#define NV_PFAULT_ACCESS_TYPE_READ 0x00000000 /* */ +#define NV_PFAULT_ACCESS_TYPE_WRITE 0x00000001 /* */ +#define NV_PFAULT_ACCESS_TYPE_ATOMIC 0x00000002 /* */ +#define NV_PFAULT_ACCESS_TYPE_PREFETCH 0x00000003 /* */ +#define NV_PFAULT_MMU_CLIENT_TYPE 20:20 /* */ +#define NV_PFAULT_MMU_CLIENT_TYPE_GPC 0x00000000 /* */ +#define NV_PFAULT_MMU_CLIENT_TYPE_HUB 0x00000001 /* */ +#define NV_PFAULT_GPC_ID 28:24 /* */ +#endif // __gp100_dev_fault_h__ diff --git a/src/nouveau/headers/nvidia/hwref/pascal/gp100/dev_fb.h b/src/nouveau/headers/nvidia/hwref/pascal/gp100/dev_fb.h new file mode 100644 index 00000000000..faced40e296 --- /dev/null +++ b/src/nouveau/headers/nvidia/hwref/pascal/gp100/dev_fb.h @@ -0,0 +1,71 @@ +/******************************************************************************* + Copyright (c) 2016 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +// Excerpt of gp100/dev_fb.h + +#ifndef __dev_fb_h__ +#define __dev_fb_h__ + +#define NV_PFB_PRI_MMU_INVALIDATE_ALL_VA 0:0 /* RWXVF */ +#define NV_PFB_PRI_MMU_INVALIDATE_ALL_VA_FALSE 0x00000000 /* RW--V */ +#define NV_PFB_PRI_MMU_INVALIDATE_ALL_VA_TRUE 0x00000001 /* RW--V */ +#define NV_PFB_PRI_MMU_INVALIDATE_ALL_PDB 1:1 /* RWXVF */ +#define NV_PFB_PRI_MMU_INVALIDATE_ALL_PDB_FALSE 0x00000000 /* RW--V */ +#define NV_PFB_PRI_MMU_INVALIDATE_ALL_PDB_TRUE 0x00000001 /* RW--V */ +#define NV_PFB_PRI_MMU_INVALIDATE_REPLAY 5:3 /* RWXVF */ +#define NV_PFB_PRI_MMU_INVALIDATE_REPLAY_NONE 0x00000000 /* RW--V */ +#define NV_PFB_PRI_MMU_INVALIDATE_REPLAY_START 0x00000001 /* RW--V */ +#define NV_PFB_PRI_MMU_INVALIDATE_REPLAY_START_ACK_ALL 0x00000002 /* RW--V */ +#define NV_PFB_PRI_MMU_INVALIDATE_REPLAY_CANCEL_TARGETED 0x00000003 /* RW--V */ +#define NV_PFB_PRI_MMU_INVALIDATE_REPLAY_CANCEL_GLOBAL 0x00000004 /* RW--V */ +#define NV_PFB_PRI_MMU_INVALIDATE_REPLAY_CANCEL 0x00000004 /* */ +#define NV_PFB_PRI_MMU_INVALIDATE_SYS_MEMBAR 6:6 /* RWXVF */ +#define NV_PFB_PRI_MMU_INVALIDATE_SYS_MEMBAR_FALSE 0x00000000 /* RW--V */ +#define NV_PFB_PRI_MMU_INVALIDATE_SYS_MEMBAR_TRUE 0x00000001 /* RW--V */ +#define NV_PFB_PRI_MMU_INVALIDATE_ACK 8:7 /* RWXVF */ +#define NV_PFB_PRI_MMU_INVALIDATE_ACK_NONE_REQUIRED 0x00000000 /* RW--V */ +#define NV_PFB_PRI_MMU_INVALIDATE_ACK_INTRANODE 0x00000002 /* RW--V */ +#define NV_PFB_PRI_MMU_INVALIDATE_ACK_GLOBALLY 0x00000001 /* RW--V */ +#define NV_PFB_PRI_MMU_INVALIDATE_CANCEL_CLIENT_ID 14:9 /* RWXVF */ +#define NV_PFB_PRI_MMU_INVALIDATE_CANCEL_GPC_ID 19:15 /* RWXVF */ +#define NV_PFB_PRI_MMU_INVALIDATE_CANCEL_CLIENT_TYPE 20:20 /* RWXVF */ +#define NV_PFB_PRI_MMU_INVALIDATE_CANCEL_CLIENT_TYPE_GPC 0x00000000 /* RW--V */ +#define NV_PFB_PRI_MMU_INVALIDATE_CANCEL_CLIENT_TYPE_HUB 0x00000001 /* RW--V */ +#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL 26:24 /* RWXVF */ +#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_ALL 0x00000000 /* RW--V */ +#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_PTE_ONLY 0x00000001 /* RW--V */ +#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE0 0x00000002 /* RW--V */ +#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE1 0x00000003 /* RW--V */ +#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE2 0x00000004 /* RW--V */ +#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE3 0x00000005 /* RW--V */ +#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE4 0x00000006 /* RW--V */ +#define NV_PFB_PRI_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE5 0x00000007 /* RW--V */ +#define NV_PFB_PRI_MMU_INVALIDATE_TRIGGER 31:31 /* -WEVF */ +#define NV_PFB_PRI_MMU_INVALIDATE_TRIGGER_FALSE 0x00000000 /* -WE-V */ +#define NV_PFB_PRI_MMU_INVALIDATE_TRIGGER_TRUE 0x00000001 /* -W--T */ + +#define NV_PFB_PRI_MMU_PAGE_FAULT_CTRL_PRF_FILTER 1:0 /* RWEVF */ +#define NV_PFB_PRI_MMU_PAGE_FAULT_CTRL_PRF_FILTER_SEND_ALL 0x00000000 /* RWE-V */ +#define NV_PFB_PRI_MMU_PAGE_FAULT_CTRL_PRF_FILTER_SEND_NONE 0x00000003 /* RW--V */ + +#endif // __dev_fb_h__ diff --git a/src/nouveau/headers/nvidia/hwref/pascal/gp100/dev_mmu.h b/src/nouveau/headers/nvidia/hwref/pascal/gp100/dev_mmu.h new file mode 100644 index 00000000000..cb1131e8df9 --- /dev/null +++ b/src/nouveau/headers/nvidia/hwref/pascal/gp100/dev_mmu.h @@ -0,0 +1,625 @@ +/******************************************************************************* + Copyright (c) 2003-2016 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + + +#ifndef __gp100_dev_mmu_h__ +#define __gp100_dev_mmu_h__ +/* This file is autogenerated. Do not edit */ +#define NV_MMU_PDE /* ----G */ +#define NV_MMU_PDE_APERTURE_BIG (0*32+1):(0*32+0) /* RWXVF */ +#define NV_MMU_PDE_APERTURE_BIG_INVALID 0x00000000 /* RW--V */ +#define NV_MMU_PDE_APERTURE_BIG_VIDEO_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_PDE_APERTURE_BIG_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_PDE_APERTURE_BIG_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_PDE_SIZE (0*32+3):(0*32+2) /* RWXVF */ +#define NV_MMU_PDE_SIZE_FULL 0x00000000 /* RW--V */ +#define NV_MMU_PDE_SIZE_HALF 0x00000001 /* RW--V */ +#define NV_MMU_PDE_SIZE_QUARTER 0x00000002 /* RW--V */ +#define NV_MMU_PDE_SIZE_EIGHTH 0x00000003 /* RW--V */ +#define NV_MMU_PDE_ADDRESS_BIG_SYS (0*32+31):(0*32+4) /* RWXVF */ +#define NV_MMU_PDE_ADDRESS_BIG_VID (0*32+31-3):(0*32+4) /* RWXVF */ +#define NV_MMU_PDE_ADDRESS_BIG_VID_PEER (0*32+31):(0*32+32-3) /* RWXVF */ +#define NV_MMU_PDE_ADDRESS_BIG_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_PDE_APERTURE_SMALL (1*32+1):(1*32+0) /* RWXVF */ +#define NV_MMU_PDE_APERTURE_SMALL_INVALID 0x00000000 /* RW--V */ +#define NV_MMU_PDE_APERTURE_SMALL_VIDEO_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_PDE_APERTURE_SMALL_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_PDE_APERTURE_SMALL_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_PDE_VOL_SMALL (1*32+2):(1*32+2) /* RWXVF */ +#define NV_MMU_PDE_VOL_SMALL_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_PDE_VOL_SMALL_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_PDE_VOL_BIG (1*32+3):(1*32+3) /* RWXVF */ +#define NV_MMU_PDE_VOL_BIG_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_PDE_VOL_BIG_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_PDE_ADDRESS_SMALL_SYS (1*32+31):(1*32+4) /* RWXVF */ +#define NV_MMU_PDE_ADDRESS_SMALL_VID (1*32+31-3):(1*32+4) /* RWXVF */ +#define NV_MMU_PDE_ADDRESS_SMALL_VID_PEER (1*32+31):(1*32+32-3) /* RWXVF */ +#define NV_MMU_PDE_ADDRESS_SMALL_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_PDE_ADDRESS_SHIFT 0x0000000c /* */ +#define NV_MMU_PDE__SIZE 8 +#define NV_MMU_PTE /* ----G */ +#define NV_MMU_PTE_VALID (0*32+0):(0*32+0) /* RWXVF */ +#define NV_MMU_PTE_VALID_TRUE 0x1 /* RW--V */ +#define NV_MMU_PTE_VALID_FALSE 0x0 /* RW--V */ +#define NV_MMU_PTE_PRIVILEGE (0*32+1):(0*32+1) /* RWXVF */ +#define NV_MMU_PTE_PRIVILEGE_TRUE 0x1 /* RW--V */ +#define NV_MMU_PTE_PRIVILEGE_FALSE 0x0 /* RW--V */ +#define NV_MMU_PTE_READ_ONLY (0*32+2):(0*32+2) /* RWXVF */ +#define NV_MMU_PTE_READ_ONLY_TRUE 0x1 /* RW--V */ +#define NV_MMU_PTE_READ_ONLY_FALSE 0x0 /* RW--V */ +#define NV_MMU_PTE_ENCRYPTED (0*32+3):(0*32+3) /* RWXVF */ +#define NV_MMU_PTE_ENCRYPTED_TRUE 0x00000001 /* R---V */ +#define NV_MMU_PTE_ENCRYPTED_FALSE 0x00000000 /* R---V */ +#define NV_MMU_PTE_ADDRESS_SYS (0*32+31):(0*32+4) /* RWXVF */ +#define NV_MMU_PTE_ADDRESS_VID (0*32+31-3):(0*32+4) /* RWXVF */ +#define NV_MMU_PTE_ADDRESS_VID_PEER (0*32+31):(0*32+32-3) /* RWXVF */ +#define NV_MMU_PTE_ADDRESS_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_PTE_ADDRESS_VID_PEER_1 0x00000001 /* RW--V */ +#define NV_MMU_PTE_ADDRESS_VID_PEER_2 0x00000002 /* RW--V */ +#define NV_MMU_PTE_ADDRESS_VID_PEER_3 0x00000003 /* RW--V */ +#define NV_MMU_PTE_ADDRESS_VID_PEER_4 0x00000004 /* RW--V */ +#define NV_MMU_PTE_ADDRESS_VID_PEER_5 0x00000005 /* RW--V */ +#define NV_MMU_PTE_ADDRESS_VID_PEER_6 0x00000006 /* RW--V */ +#define NV_MMU_PTE_ADDRESS_VID_PEER_7 0x00000007 /* RW--V */ +#define NV_MMU_PTE_VOL (1*32+0):(1*32+0) /* RWXVF */ +#define NV_MMU_PTE_VOL_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_PTE_VOL_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_PTE_APERTURE (1*32+2):(1*32+1) /* RWXVF */ +#define NV_MMU_PTE_APERTURE_VIDEO_MEMORY 0x00000000 /* RW--V */ +#define NV_MMU_PTE_APERTURE_PEER_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_PTE_APERTURE_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_PTE_LOCK (1*32+3):(1*32+3) /* RWXVF */ +#define NV_MMU_PTE_LOCK_TRUE 0x1 /* RW--V */ +#define NV_MMU_PTE_LOCK_FALSE 0x0 /* RW--V */ +#define NV_MMU_PTE_ATOMIC_DISABLE (1*32+3):(1*32+3) /* RWXVF */ +#define NV_MMU_PTE_ATOMIC_DISABLE_TRUE 0x1 /* RW--V */ +#define NV_MMU_PTE_ATOMIC_DISABLE_FALSE 0x0 /* RW--V */ +#define NV_MMU_PTE_COMPTAGLINE (1*32+18+11):(1*32+12) /* RWXVF */ +#define NV_MMU_PTE_READ_DISABLE (1*32+30):(1*32+30) /* RWXVF */ +#define NV_MMU_PTE_READ_DISABLE_TRUE 0x1 /* RW--V */ +#define NV_MMU_PTE_READ_DISABLE_FALSE 0x0 /* RW--V */ +#define NV_MMU_PTE_WRITE_DISABLE (1*32+31):(1*32+31) /* RWXVF */ +#define NV_MMU_PTE_WRITE_DISABLE_TRUE 0x1 /* RW--V */ +#define NV_MMU_PTE_WRITE_DISABLE_FALSE 0x0 /* RW--V */ +#define NV_MMU_PTE_ADDRESS_SHIFT 0x0000000c /* */ +#define NV_MMU_PTE__SIZE 8 +#define NV_MMU_PTE_COMPTAGS_NONE 0x0 /* */ +#define NV_MMU_PTE_COMPTAGS_1 0x1 /* */ +#define NV_MMU_PTE_COMPTAGS_2 0x2 /* */ +#define NV_MMU_PTE_KIND (1*32+11):(1*32+4) /* RWXVF */ +#define NV_MMU_PTE_KIND_INVALID 0xff /* R---V */ +#define NV_MMU_PTE_KIND_PITCH 0x00 /* R---V */ +#define NV_MMU_PTE_KIND_Z16 0x01 /* R---V */ +#define NV_MMU_PTE_KIND_Z16_2C 0x02 /* R---V */ +#define NV_MMU_PTE_KIND_Z16_MS2_2C 0x03 /* R---V */ +#define NV_MMU_PTE_KIND_Z16_MS4_2C 0x04 /* R---V */ +#define NV_MMU_PTE_KIND_Z16_MS8_2C 0x05 /* R---V */ +#define NV_MMU_PTE_KIND_Z16_MS16_2C 0x06 /* R---V */ +#define NV_MMU_PTE_KIND_Z16_2Z 0x07 /* R---V */ +#define NV_MMU_PTE_KIND_Z16_MS2_2Z 0x08 /* R---V */ +#define NV_MMU_PTE_KIND_Z16_MS4_2Z 0x09 /* R---V */ +#define NV_MMU_PTE_KIND_Z16_MS8_2Z 0x0a /* R---V */ +#define NV_MMU_PTE_KIND_Z16_MS16_2Z 0x0b /* R---V */ +#define NV_MMU_PTE_KIND_Z16_2CZ 0x36 /* R---V */ +#define NV_MMU_PTE_KIND_Z16_MS2_2CZ 0x37 /* R---V */ +#define NV_MMU_PTE_KIND_Z16_MS4_2CZ 0x38 /* R---V */ +#define NV_MMU_PTE_KIND_Z16_MS8_2CZ 0x39 /* R---V */ +#define NV_MMU_PTE_KIND_Z16_MS16_2CZ 0x5f /* R---V */ +#define NV_MMU_PTE_KIND_Z16_4CZ 0x0c /* R---V */ +#define NV_MMU_PTE_KIND_Z16_MS2_4CZ 0x0d /* R---V */ +#define NV_MMU_PTE_KIND_Z16_MS4_4CZ 0x0e /* R---V */ +#define NV_MMU_PTE_KIND_Z16_MS8_4CZ 0x0f /* R---V */ +#define NV_MMU_PTE_KIND_Z16_MS16_4CZ 0x10 /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24 0x11 /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_1Z 0x12 /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_MS2_1Z 0x13 /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_MS4_1Z 0x14 /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_MS8_1Z 0x15 /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_MS16_1Z 0x16 /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_2CZ 0x17 /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_MS2_2CZ 0x18 /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_MS4_2CZ 0x19 /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_MS8_2CZ 0x1a /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_MS16_2CZ 0x1b /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_2CS 0x1c /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_MS2_2CS 0x1d /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_MS4_2CS 0x1e /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_MS8_2CS 0x1f /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_MS16_2CS 0x20 /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_4CSZV 0x21 /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_MS2_4CSZV 0x22 /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_MS4_4CSZV 0x23 /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_MS8_4CSZV 0x24 /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_MS16_4CSZV 0x25 /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12 0x26 /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4 0x27 /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8 0x28 /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24 0x29 /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_1ZV 0x2e /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_1ZV 0x2f /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_1ZV 0x30 /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_1ZV 0x31 /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2CS 0x32 /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2CS 0x33 /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2CS 0x34 /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2CS 0x35 /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2CZV 0x3a /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2CZV 0x3b /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2CZV 0x3c /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2CZV 0x3d /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2ZV 0x3e /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2ZV 0x3f /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2ZV 0x40 /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2ZV 0x41 /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_4CSZV 0x42 /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_4CSZV 0x43 /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_4CSZV 0x44 /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_4CSZV 0x45 /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8 0x46 /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_1Z 0x47 /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_MS2_1Z 0x48 /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_MS4_1Z 0x49 /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_MS8_1Z 0x4a /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_MS16_1Z 0x4b /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_2CS 0x4c /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_MS2_2CS 0x4d /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_MS4_2CS 0x4e /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_MS8_2CS 0x4f /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_MS16_2CS 0x50 /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_2CZ 0x51 /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_MS2_2CZ 0x52 /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_MS4_2CZ 0x53 /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_MS8_2CZ 0x54 /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_MS16_2CZ 0x55 /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_4CSZV 0x56 /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_MS2_4CSZV 0x57 /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_MS4_4CSZV 0x58 /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_MS8_4CSZV 0x59 /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_MS16_4CSZV 0x5a /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12 0x5b /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4 0x5c /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8 0x5d /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24 0x5e /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_1ZV 0x63 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_1ZV 0x64 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_1ZV 0x65 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_1ZV 0x66 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2CS 0x67 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2CS 0x68 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2CS 0x69 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2CS 0x6a /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2CZV 0x6f /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2CZV 0x70 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2CZV 0x71 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2CZV 0x72 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2ZV 0x73 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2ZV 0x74 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2ZV 0x75 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2ZV 0x76 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_4CSZV 0x77 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_4CSZV 0x78 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_4CSZV 0x79 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_4CSZV 0x7a /* R---V */ +#define NV_MMU_PTE_KIND_ZF32 0x7b /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_1Z 0x7c /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_MS2_1Z 0x7d /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_MS4_1Z 0x7e /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_MS8_1Z 0x7f /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_MS16_1Z 0x80 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_2CS 0x81 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_MS2_2CS 0x82 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_MS4_2CS 0x83 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_MS8_2CS 0x84 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_MS16_2CS 0x85 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_2CZ 0x86 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_MS2_2CZ 0x87 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_MS4_2CZ 0x88 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_MS8_2CZ 0x89 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_MS16_2CZ 0x8a /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12 0x8b /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4 0x8c /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8 0x8d /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24 0x8e /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1CS 0x8f /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1CS 0x90 /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1CS 0x91 /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1CS 0x92 /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1ZV 0x97 /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1ZV 0x98 /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1ZV 0x99 /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1ZV 0x9a /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1CZV 0x9b /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1CZV 0x9c /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1CZV 0x9d /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1CZV 0x9e /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_2CS 0x9f /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_2CS 0xa0 /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_2CS 0xa1 /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_2CS 0xa2 /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_2CSZV 0xa3 /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_2CSZV 0xa4 /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_2CSZV 0xa5 /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_2CSZV 0xa6 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12 0xa7 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4 0xa8 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8 0xa9 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24 0xaa /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1CS 0xab /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1CS 0xac /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1CS 0xad /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1CS 0xae /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1ZV 0xb3 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1ZV 0xb4 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1ZV 0xb5 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1ZV 0xb6 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1CZV 0xb7 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1CZV 0xb8 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1CZV 0xb9 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1CZV 0xba /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_2CS 0xbb /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_2CS 0xbc /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_2CS 0xbd /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_2CS 0xbe /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_2CSZV 0xbf /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_2CSZV 0xc0 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_2CSZV 0xc1 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_2CSZV 0xc2 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8 0xc3 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8_1CS 0xc4 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_1CS 0xc5 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_1CS 0xc6 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_1CS 0xc7 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_1CS 0xc8 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8_2CSZV 0xce /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_2CSZV 0xcf /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_2CSZV 0xd0 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_2CSZV 0xd1 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_2CSZV 0xd2 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8_2CS 0xd3 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_2CS 0xd4 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_2CS 0xd5 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_2CS 0xd6 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_2CS 0xd7 /* R---V */ +#define NV_MMU_PTE_KIND_S8 0x2a /* R---V */ +#define NV_MMU_PTE_KIND_S8_2S 0x2b /* R---V */ +#define NV_MMU_PTE_KIND_GENERIC_16BX2 0xfe /* R---V */ +#define NV_MMU_PTE_KIND_C32_2C 0xd8 /* R---V */ +#define NV_MMU_PTE_KIND_C32_2CBR 0xd9 /* R---V */ +#define NV_MMU_PTE_KIND_C32_2CBA 0xda /* R---V */ +#define NV_MMU_PTE_KIND_C32_2CRA 0xdb /* R---V */ +#define NV_MMU_PTE_KIND_C32_2BRA 0xdc /* R---V */ +#define NV_MMU_PTE_KIND_C32_MS2_2C 0xdd /* R---V */ +#define NV_MMU_PTE_KIND_C32_MS2_2CBR 0xde /* R---V */ +#define NV_MMU_PTE_KIND_C32_MS2_2CRA 0xcc /* R---V */ +#define NV_MMU_PTE_KIND_C32_MS4_2C 0xdf /* R---V */ +#define NV_MMU_PTE_KIND_C32_MS4_2CBR 0xe0 /* R---V */ +#define NV_MMU_PTE_KIND_C32_MS4_2CBA 0xe1 /* R---V */ +#define NV_MMU_PTE_KIND_C32_MS4_2CRA 0xe2 /* R---V */ +#define NV_MMU_PTE_KIND_C32_MS4_2BRA 0xe3 /* R---V */ +#define NV_MMU_PTE_KIND_C32_MS4_4CBRA 0x2c /* R---V */ +#define NV_MMU_PTE_KIND_C32_MS8_MS16_2C 0xe4 /* R---V */ +#define NV_MMU_PTE_KIND_C32_MS8_MS16_2CRA 0xe5 /* R---V */ +#define NV_MMU_PTE_KIND_C64_2C 0xe6 /* R---V */ +#define NV_MMU_PTE_KIND_C64_2CBR 0xe7 /* R---V */ +#define NV_MMU_PTE_KIND_C64_2CBA 0xe8 /* R---V */ +#define NV_MMU_PTE_KIND_C64_2CRA 0xe9 /* R---V */ +#define NV_MMU_PTE_KIND_C64_2BRA 0xea /* R---V */ +#define NV_MMU_PTE_KIND_C64_MS2_2C 0xeb /* R---V */ +#define NV_MMU_PTE_KIND_C64_MS2_2CBR 0xec /* R---V */ +#define NV_MMU_PTE_KIND_C64_MS2_2CRA 0xcd /* R---V */ +#define NV_MMU_PTE_KIND_C64_MS4_2C 0xed /* R---V */ +#define NV_MMU_PTE_KIND_C64_MS4_2CBR 0xee /* R---V */ +#define NV_MMU_PTE_KIND_C64_MS4_2CBA 0xef /* R---V */ +#define NV_MMU_PTE_KIND_C64_MS4_2CRA 0xf0 /* R---V */ +#define NV_MMU_PTE_KIND_C64_MS4_2BRA 0xf1 /* R---V */ +#define NV_MMU_PTE_KIND_C64_MS4_4CBRA 0x2d /* R---V */ +#define NV_MMU_PTE_KIND_C64_MS8_MS16_2C 0xf2 /* R---V */ +#define NV_MMU_PTE_KIND_C64_MS8_MS16_2CRA 0xf3 /* R---V */ +#define NV_MMU_PTE_KIND_C128_2C 0xf4 /* R---V */ +#define NV_MMU_PTE_KIND_C128_2CR 0xf5 /* R---V */ +#define NV_MMU_PTE_KIND_C128_MS2_2C 0xf6 /* R---V */ +#define NV_MMU_PTE_KIND_C128_MS2_2CR 0xf7 /* R---V */ +#define NV_MMU_PTE_KIND_C128_MS4_2C 0xf8 /* R---V */ +#define NV_MMU_PTE_KIND_C128_MS4_2CR 0xf9 /* R---V */ +#define NV_MMU_PTE_KIND_C128_MS8_MS16_2C 0xfa /* R---V */ +#define NV_MMU_PTE_KIND_C128_MS8_MS16_2CR 0xfb /* R---V */ +#define NV_MMU_PTE_KIND_X8C24 0xfc /* R---V */ +#define NV_MMU_PTE_KIND_PITCH_NO_SWIZZLE 0xfd /* R---V */ +#define NV_MMU_PTE_KIND_SMSKED_MESSAGE 0xca /* R---V */ +#define NV_MMU_PTE_KIND_SMHOST_MESSAGE 0xcb /* R---V */ +#define NV_MMU_VER1_PDE /* ----G */ +#define NV_MMU_VER1_PDE_APERTURE_BIG (0*32+1):(0*32+0) /* RWXVF */ +#define NV_MMU_VER1_PDE_APERTURE_BIG_INVALID 0x00000000 /* RW--V */ +#define NV_MMU_VER1_PDE_APERTURE_BIG_VIDEO_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_VER1_PDE_APERTURE_BIG_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_VER1_PDE_APERTURE_BIG_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_VER1_PDE_SIZE (0*32+3):(0*32+2) /* RWXVF */ +#define NV_MMU_VER1_PDE_SIZE_FULL 0x00000000 /* RW--V */ +#define NV_MMU_VER1_PDE_SIZE_HALF 0x00000001 /* RW--V */ +#define NV_MMU_VER1_PDE_SIZE_QUARTER 0x00000002 /* RW--V */ +#define NV_MMU_VER1_PDE_SIZE_EIGHTH 0x00000003 /* RW--V */ +#define NV_MMU_VER1_PDE_ADDRESS_BIG_SYS (0*32+31):(0*32+4) /* RWXVF */ +#define NV_MMU_VER1_PDE_ADDRESS_BIG_VID (0*32+31-3):(0*32+4) /* RWXVF */ +#define NV_MMU_VER1_PDE_ADDRESS_BIG_VID_PEER (0*32+31):(0*32+32-3) /* RWXVF */ +#define NV_MMU_VER1_PDE_ADDRESS_BIG_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_VER1_PDE_APERTURE_SMALL (1*32+1):(1*32+0) /* RWXVF */ +#define NV_MMU_VER1_PDE_APERTURE_SMALL_INVALID 0x00000000 /* RW--V */ +#define NV_MMU_VER1_PDE_APERTURE_SMALL_VIDEO_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_VER1_PDE_APERTURE_SMALL_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_VER1_PDE_APERTURE_SMALL_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_VER1_PDE_VOL_SMALL (1*32+2):(1*32+2) /* RWXVF */ +#define NV_MMU_VER1_PDE_VOL_SMALL_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_VER1_PDE_VOL_SMALL_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_VER1_PDE_VOL_BIG (1*32+3):(1*32+3) /* RWXVF */ +#define NV_MMU_VER1_PDE_VOL_BIG_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_VER1_PDE_VOL_BIG_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_VER1_PDE_ADDRESS_SMALL_SYS (1*32+31):(1*32+4) /* RWXVF */ +#define NV_MMU_VER1_PDE_ADDRESS_SMALL_VID (1*32+31-3):(1*32+4) /* RWXVF */ +#define NV_MMU_VER1_PDE_ADDRESS_SMALL_VID_PEER (1*32+31):(1*32+32-3) /* RWXVF */ +#define NV_MMU_VER1_PDE_ADDRESS_SMALL_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_VER1_PDE_ADDRESS_SHIFT 0x0000000c /* */ +#define NV_MMU_VER1_PDE__SIZE 8 +#define NV_MMU_VER1_PTE /* ----G */ +#define NV_MMU_VER1_PTE_VALID (0*32+0):(0*32+0) /* RWXVF */ +#define NV_MMU_VER1_PTE_VALID_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER1_PTE_VALID_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER1_PTE_PRIVILEGE (0*32+1):(0*32+1) /* RWXVF */ +#define NV_MMU_VER1_PTE_PRIVILEGE_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER1_PTE_PRIVILEGE_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER1_PTE_READ_ONLY (0*32+2):(0*32+2) /* RWXVF */ +#define NV_MMU_VER1_PTE_READ_ONLY_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER1_PTE_READ_ONLY_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER1_PTE_ENCRYPTED (0*32+3):(0*32+3) /* RWXVF */ +#define NV_MMU_VER1_PTE_ENCRYPTED_TRUE 0x00000001 /* R---V */ +#define NV_MMU_VER1_PTE_ENCRYPTED_FALSE 0x00000000 /* R---V */ +#define NV_MMU_VER1_PTE_ADDRESS_SYS (0*32+31):(0*32+4) /* RWXVF */ +#define NV_MMU_VER1_PTE_ADDRESS_VID (0*32+31-3):(0*32+4) /* RWXVF */ +#define NV_MMU_VER1_PTE_ADDRESS_VID_PEER (0*32+31):(0*32+32-3) /* RWXVF */ +#define NV_MMU_VER1_PTE_ADDRESS_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_VER1_PTE_ADDRESS_VID_PEER_1 0x00000001 /* RW--V */ +#define NV_MMU_VER1_PTE_ADDRESS_VID_PEER_2 0x00000002 /* RW--V */ +#define NV_MMU_VER1_PTE_ADDRESS_VID_PEER_3 0x00000003 /* RW--V */ +#define NV_MMU_VER1_PTE_ADDRESS_VID_PEER_4 0x00000004 /* RW--V */ +#define NV_MMU_VER1_PTE_ADDRESS_VID_PEER_5 0x00000005 /* RW--V */ +#define NV_MMU_VER1_PTE_ADDRESS_VID_PEER_6 0x00000006 /* RW--V */ +#define NV_MMU_VER1_PTE_ADDRESS_VID_PEER_7 0x00000007 /* RW--V */ +#define NV_MMU_VER1_PTE_VOL (1*32+0):(1*32+0) /* RWXVF */ +#define NV_MMU_VER1_PTE_VOL_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_VER1_PTE_VOL_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_VER1_PTE_APERTURE (1*32+2):(1*32+1) /* RWXVF */ +#define NV_MMU_VER1_PTE_APERTURE_VIDEO_MEMORY 0x00000000 /* RW--V */ +#define NV_MMU_VER1_PTE_APERTURE_PEER_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_VER1_PTE_APERTURE_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_VER1_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_VER1_PTE_ATOMIC_DISABLE (1*32+3):(1*32+3) /* RWXVF */ +#define NV_MMU_VER1_PTE_ATOMIC_DISABLE_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER1_PTE_ATOMIC_DISABLE_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER1_PTE_COMPTAGLINE (1*32+18+11):(1*32+12) /* RWXVF */ +#define NV_MMU_VER1_PTE_KIND (1*32+11):(1*32+4) /* RWXVF */ +#define NV_MMU_VER1_PTE_ADDRESS_SHIFT 0x0000000c /* */ +#define NV_MMU_VER1_PTE__SIZE 8 +#define NV_MMU_VER1_PTE_COMPTAGS_NONE 0x0 /* */ +#define NV_MMU_VER1_PTE_COMPTAGS_1 0x1 /* */ +#define NV_MMU_VER1_PTE_COMPTAGS_2 0x2 /* */ +#define NV_MMU_NEW_PDE /* ----G */ +#define NV_MMU_NEW_PDE_IS_PTE 0:0 /* RWXVF */ +#define NV_MMU_NEW_PDE_IS_PTE_TRUE 0x1 /* RW--V */ +#define NV_MMU_NEW_PDE_IS_PTE_FALSE 0x0 /* RW--V */ +#define NV_MMU_NEW_PDE_IS_PDE 0:0 /* RWXVF */ +#define NV_MMU_NEW_PDE_IS_PDE_TRUE 0x0 /* RW--V */ +#define NV_MMU_NEW_PDE_IS_PDE_FALSE 0x1 /* RW--V */ +#define NV_MMU_NEW_PDE_VALID 0:0 /* RWXVF */ +#define NV_MMU_NEW_PDE_VALID_TRUE 0x1 /* RW--V */ +#define NV_MMU_NEW_PDE_VALID_FALSE 0x0 /* RW--V */ +#define NV_MMU_NEW_PDE_APERTURE 2:1 /* RWXVF */ +#define NV_MMU_NEW_PDE_APERTURE_INVALID 0x00000000 /* RW--V */ +#define NV_MMU_NEW_PDE_APERTURE_VIDEO_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_NEW_PDE_APERTURE_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_NEW_PDE_APERTURE_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_NEW_PDE_VOL 3:3 /* RWXVF */ +#define NV_MMU_NEW_PDE_VOL_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_NEW_PDE_VOL_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_NEW_PDE_ADDRESS_SYS 53:8 /* RWXVF */ +#define NV_MMU_NEW_PDE_ADDRESS_VID (35-3):8 /* RWXVF */ +#define NV_MMU_NEW_PDE_ADDRESS_VID_PEER 35:(36-3) /* RWXVF */ +#define NV_MMU_NEW_PDE_ADDRESS_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_NEW_PDE_ADDRESS_SHIFT 0x0000000c /* */ +#define NV_MMU_NEW_PDE__SIZE 8 +#define NV_MMU_NEW_DUAL_PDE /* ----G */ +#define NV_MMU_NEW_DUAL_PDE_IS_PTE 0:0 /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_IS_PTE_TRUE 0x1 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_IS_PTE_FALSE 0x0 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_IS_PDE 0:0 /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_IS_PDE_TRUE 0x0 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_IS_PDE_FALSE 0x1 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_VALID 0:0 /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_VALID_TRUE 0x1 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_VALID_FALSE 0x0 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_APERTURE_BIG 2:1 /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_APERTURE_BIG_INVALID 0x00000000 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_APERTURE_BIG_VIDEO_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_APERTURE_BIG_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_APERTURE_BIG_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_VOL_BIG 3:3 /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_VOL_BIG_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_VOL_BIG_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_ADDRESS_BIG_SYS 53:(8-4) /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_ADDRESS_BIG_VID (35-3):(8-4) /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_ADDRESS_BIG_VID_PEER 35:(36-3) /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_ADDRESS_BIG_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_APERTURE_SMALL 66:65 /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_APERTURE_SMALL_INVALID 0x00000000 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_APERTURE_SMALL_VIDEO_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_APERTURE_SMALL_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_APERTURE_SMALL_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_VOL_SMALL 67:67 /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_VOL_SMALL_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_VOL_SMALL_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_ADDRESS_SMALL_SYS 117:72 /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_ADDRESS_SMALL_VID (99-3):72 /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_ADDRESS_SMALL_VID_PEER 99:(100-3) /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_ADDRESS_SMALL_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_ADDRESS_SHIFT 0x0000000c /* */ +#define NV_MMU_NEW_DUAL_PDE_ADDRESS_BIG_SHIFT 8 /* */ +#define NV_MMU_NEW_DUAL_PDE__SIZE 16 +#define NV_MMU_NEW_PTE /* ----G */ +#define NV_MMU_NEW_PTE_VALID 0:0 /* RWXVF */ +#define NV_MMU_NEW_PTE_VALID_TRUE 0x1 /* RW--V */ +#define NV_MMU_NEW_PTE_VALID_FALSE 0x0 /* RW--V */ +#define NV_MMU_NEW_PTE_APERTURE 2:1 /* RWXVF */ +#define NV_MMU_NEW_PTE_APERTURE_VIDEO_MEMORY 0x00000000 /* RW--V */ +#define NV_MMU_NEW_PTE_APERTURE_PEER_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_NEW_PTE_APERTURE_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_NEW_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_NEW_PTE_VOL 3:3 /* RWXVF */ +#define NV_MMU_NEW_PTE_VOL_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_NEW_PTE_VOL_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_NEW_PTE_ENCRYPTED 4:4 /* RWXVF */ +#define NV_MMU_NEW_PTE_ENCRYPTED_TRUE 0x00000001 /* R---V */ +#define NV_MMU_NEW_PTE_ENCRYPTED_FALSE 0x00000000 /* R---V */ +#define NV_MMU_NEW_PTE_PRIVILEGE 5:5 /* RWXVF */ +#define NV_MMU_NEW_PTE_PRIVILEGE_TRUE 0x1 /* RW--V */ +#define NV_MMU_NEW_PTE_PRIVILEGE_FALSE 0x0 /* RW--V */ +#define NV_MMU_NEW_PTE_READ_ONLY 6:6 /* RWXVF */ +#define NV_MMU_NEW_PTE_READ_ONLY_TRUE 0x1 /* RW--V */ +#define NV_MMU_NEW_PTE_READ_ONLY_FALSE 0x0 /* RW--V */ +#define NV_MMU_NEW_PTE_ATOMIC_DISABLE 7:7 /* RWXVF */ +#define NV_MMU_NEW_PTE_ATOMIC_DISABLE_TRUE 0x1 /* RW--V */ +#define NV_MMU_NEW_PTE_ATOMIC_DISABLE_FALSE 0x0 /* RW--V */ +#define NV_MMU_NEW_PTE_ADDRESS_SYS 53:8 /* RWXVF */ +#define NV_MMU_NEW_PTE_ADDRESS_VID (35-3):8 /* RWXVF */ +#define NV_MMU_NEW_PTE_ADDRESS_VID_PEER 35:(36-3) /* RWXVF */ +#define NV_MMU_NEW_PTE_ADDRESS_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_NEW_PTE_ADDRESS_VID_PEER_1 0x00000001 /* RW--V */ +#define NV_MMU_NEW_PTE_ADDRESS_VID_PEER_2 0x00000002 /* RW--V */ +#define NV_MMU_NEW_PTE_ADDRESS_VID_PEER_3 0x00000003 /* RW--V */ +#define NV_MMU_NEW_PTE_ADDRESS_VID_PEER_4 0x00000004 /* RW--V */ +#define NV_MMU_NEW_PTE_ADDRESS_VID_PEER_5 0x00000005 /* RW--V */ +#define NV_MMU_NEW_PTE_ADDRESS_VID_PEER_6 0x00000006 /* RW--V */ +#define NV_MMU_NEW_PTE_ADDRESS_VID_PEER_7 0x00000007 /* RW--V */ +#define NV_MMU_NEW_PTE_COMPTAGLINE (18+35):36 /* RWXVF */ +#define NV_MMU_NEW_PTE_KIND 63:56 /* RWXVF */ +#define NV_MMU_NEW_PTE_ADDRESS_SHIFT 0x0000000c /* */ +#define NV_MMU_NEW_PTE__SIZE 8 +#define NV_MMU_VER2_PDE /* ----G */ +#define NV_MMU_VER2_PDE_IS_PTE 0:0 /* RWXVF */ +#define NV_MMU_VER2_PDE_IS_PTE_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER2_PDE_IS_PTE_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER2_PDE_IS_PDE 0:0 /* RWXVF */ +#define NV_MMU_VER2_PDE_IS_PDE_TRUE 0x0 /* RW--V */ +#define NV_MMU_VER2_PDE_IS_PDE_FALSE 0x1 /* RW--V */ +#define NV_MMU_VER2_PDE_VALID 0:0 /* RWXVF */ +#define NV_MMU_VER2_PDE_VALID_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER2_PDE_VALID_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER2_PDE_APERTURE 2:1 /* RWXVF */ +#define NV_MMU_VER2_PDE_APERTURE_INVALID 0x00000000 /* RW--V */ +#define NV_MMU_VER2_PDE_APERTURE_VIDEO_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_VER2_PDE_APERTURE_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_VER2_PDE_APERTURE_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_VER2_PDE_VOL 3:3 /* RWXVF */ +#define NV_MMU_VER2_PDE_VOL_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_VER2_PDE_VOL_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_VER2_PDE_ADDRESS_SYS 53:8 /* RWXVF */ +#define NV_MMU_VER2_PDE_ADDRESS_VID (35-3):8 /* RWXVF */ +#define NV_MMU_VER2_PDE_ADDRESS_VID_PEER 35:(36-3) /* RWXVF */ +#define NV_MMU_VER2_PDE_ADDRESS_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_VER2_PDE_ADDRESS_SHIFT 0x0000000c /* */ +#define NV_MMU_VER2_PDE__SIZE 8 +#define NV_MMU_VER2_DUAL_PDE /* ----G */ +#define NV_MMU_VER2_DUAL_PDE_IS_PTE 0:0 /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_IS_PTE_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_IS_PTE_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_IS_PDE 0:0 /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_IS_PDE_TRUE 0x0 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_IS_PDE_FALSE 0x1 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_VALID 0:0 /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_VALID_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_VALID_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_APERTURE_BIG 2:1 /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_APERTURE_BIG_INVALID 0x00000000 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_APERTURE_BIG_VIDEO_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_APERTURE_BIG_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_APERTURE_BIG_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_VOL_BIG 3:3 /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_VOL_BIG_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_VOL_BIG_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_ADDRESS_BIG_SYS 53:(8-4) /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_ADDRESS_BIG_VID (35-3):(8-4) /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_ADDRESS_BIG_VID_PEER 35:(36-3) /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_ADDRESS_BIG_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_APERTURE_SMALL 66:65 /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_APERTURE_SMALL_INVALID 0x00000000 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_APERTURE_SMALL_VIDEO_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_APERTURE_SMALL_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_APERTURE_SMALL_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_VOL_SMALL 67:67 /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_VOL_SMALL_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_VOL_SMALL_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_ADDRESS_SMALL_SYS 117:72 /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_ADDRESS_SMALL_VID (99-3):72 /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_ADDRESS_SMALL_VID_PEER 99:(100-3) /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_ADDRESS_SMALL_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_ADDRESS_SHIFT 0x0000000c /* */ +#define NV_MMU_VER2_DUAL_PDE_ADDRESS_BIG_SHIFT 8 /* */ +#define NV_MMU_VER2_DUAL_PDE__SIZE 16 +#define NV_MMU_VER2_PTE /* ----G */ +#define NV_MMU_VER2_PTE_VALID 0:0 /* RWXVF */ +#define NV_MMU_VER2_PTE_VALID_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER2_PTE_VALID_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER2_PTE_APERTURE 2:1 /* RWXVF */ +#define NV_MMU_VER2_PTE_APERTURE_VIDEO_MEMORY 0x00000000 /* RW--V */ +#define NV_MMU_VER2_PTE_APERTURE_PEER_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_VER2_PTE_APERTURE_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_VER2_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_VER2_PTE_VOL 3:3 /* RWXVF */ +#define NV_MMU_VER2_PTE_VOL_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_VER2_PTE_VOL_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_VER2_PTE_ENCRYPTED 4:4 /* RWXVF */ +#define NV_MMU_VER2_PTE_ENCRYPTED_TRUE 0x00000001 /* R---V */ +#define NV_MMU_VER2_PTE_ENCRYPTED_FALSE 0x00000000 /* R---V */ +#define NV_MMU_VER2_PTE_PRIVILEGE 5:5 /* RWXVF */ +#define NV_MMU_VER2_PTE_PRIVILEGE_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER2_PTE_PRIVILEGE_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER2_PTE_READ_ONLY 6:6 /* RWXVF */ +#define NV_MMU_VER2_PTE_READ_ONLY_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER2_PTE_READ_ONLY_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER2_PTE_ATOMIC_DISABLE 7:7 /* RWXVF */ +#define NV_MMU_VER2_PTE_ATOMIC_DISABLE_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER2_PTE_ATOMIC_DISABLE_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER2_PTE_ADDRESS_SYS 53:8 /* RWXVF */ +#define NV_MMU_VER2_PTE_ADDRESS_VID (35-3):8 /* RWXVF */ +#define NV_MMU_VER2_PTE_ADDRESS_VID_PEER 35:(36-3) /* RWXVF */ +#define NV_MMU_VER2_PTE_ADDRESS_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_VER2_PTE_ADDRESS_VID_PEER_1 0x00000001 /* RW--V */ +#define NV_MMU_VER2_PTE_ADDRESS_VID_PEER_2 0x00000002 /* RW--V */ +#define NV_MMU_VER2_PTE_ADDRESS_VID_PEER_3 0x00000003 /* RW--V */ +#define NV_MMU_VER2_PTE_ADDRESS_VID_PEER_4 0x00000004 /* RW--V */ +#define NV_MMU_VER2_PTE_ADDRESS_VID_PEER_5 0x00000005 /* RW--V */ +#define NV_MMU_VER2_PTE_ADDRESS_VID_PEER_6 0x00000006 /* RW--V */ +#define NV_MMU_VER2_PTE_ADDRESS_VID_PEER_7 0x00000007 /* RW--V */ +#define NV_MMU_VER2_PTE_COMPTAGLINE (18+35):36 /* RWXVF */ +#define NV_MMU_VER2_PTE_KIND 63:56 /* RWXVF */ +#define NV_MMU_VER2_PTE_ADDRESS_SHIFT 0x0000000c /* */ +#define NV_MMU_VER2_PTE__SIZE 8 +#endif // __gp100_dev_mmu_h__ diff --git a/src/nouveau/headers/nvidia/hwref/turing/tu102/dev_fault.h b/src/nouveau/headers/nvidia/hwref/turing/tu102/dev_fault.h new file mode 100644 index 00000000000..b0263e7e207 --- /dev/null +++ b/src/nouveau/headers/nvidia/hwref/turing/tu102/dev_fault.h @@ -0,0 +1,400 @@ +/******************************************************************************* + Copyright (c) 2003-2016 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + + +#ifndef __tu102_dev_fault_h__ +#define __tu102_dev_fault_h__ +/* This file is autogenerated. Do not edit */ +#define NV_PFAULT_MMU_ENG_ID_GRAPHICS 64 /* */ +#define NV_PFAULT_MMU_ENG_ID_DISPLAY 1 /* */ +#define NV_PFAULT_MMU_ENG_ID_GSP 2 /* */ +#define NV_PFAULT_MMU_ENG_ID_IFB 9 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1 128 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2 192 /* */ +#define NV_PFAULT_MMU_ENG_ID_SEC 14 /* */ +#define NV_PFAULT_MMU_ENG_ID_PERF 8 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVDEC 10 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVDEC0 10 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVDEC1 25 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVDEC2 26 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVJPG0 24 /* */ +#define NV_PFAULT_MMU_ENG_ID_GRCOPY 15 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE0 15 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE1 16 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE2 17 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE3 18 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE4 19 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE5 20 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE6 21 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE7 22 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE8 23 /* */ +#define NV_PFAULT_MMU_ENG_ID_PWR_PMU 6 /* */ +#define NV_PFAULT_MMU_ENG_ID_PTP 3 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVENC0 11 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVENC1 12 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVENC2 13 /* */ +#define NV_PFAULT_MMU_ENG_ID_PHYSICAL 31 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST0 32 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST1 33 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST2 34 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST3 35 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST4 36 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST5 37 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST6 38 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST7 39 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST8 40 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST9 41 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST10 42 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST11 43 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST12 44 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST13 45 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST14 46 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN0 128 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN1 129 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN2 130 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN3 131 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN4 132 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN5 133 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN6 134 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN7 135 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN8 136 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN9 137 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN10 138 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN11 139 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN12 140 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN13 141 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN14 142 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN15 143 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN16 144 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN17 145 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN18 146 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN19 147 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN20 148 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN21 149 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN22 150 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN23 151 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN24 152 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN25 153 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN26 154 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN27 155 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN28 156 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN29 157 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN30 158 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN31 159 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN32 160 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN33 161 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN34 162 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN35 163 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN36 164 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN37 165 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN38 166 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN39 167 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN40 168 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN41 169 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN42 170 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN43 171 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN44 172 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN45 173 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN46 174 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN47 175 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN48 176 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN49 177 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN50 178 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN51 179 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN52 180 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN53 181 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN54 182 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN55 183 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN56 184 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN57 185 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN58 186 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN59 187 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN60 188 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN61 189 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN62 190 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1_FN63 191 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN0 192 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN1 193 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN2 194 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN3 195 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN4 196 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN5 197 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN6 198 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN7 199 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN8 200 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN9 201 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN10 202 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN11 203 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN12 204 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN13 205 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN14 206 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN15 207 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN16 208 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN17 209 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN18 210 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN19 211 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN20 212 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN21 213 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN22 214 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN23 215 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN24 216 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN25 217 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN26 218 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN27 219 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN28 220 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN29 221 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN30 222 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN31 223 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN32 224 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN33 225 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN34 226 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN35 227 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN36 228 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN37 229 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN38 230 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN39 231 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN40 232 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN41 233 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN42 234 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN43 235 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN44 236 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN45 237 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN46 238 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN47 239 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN48 240 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN49 241 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN50 242 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN51 243 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN52 244 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN53 245 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN54 246 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN55 247 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN56 248 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN57 249 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN58 250 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN59 251 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN60 252 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN61 253 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN62 254 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2_FN63 255 /* */ +#define NV_PFAULT_FAULT_TYPE 4:0 /* */ +#define NV_PFAULT_FAULT_TYPE_PDE 0x00000000 /* */ +#define NV_PFAULT_FAULT_TYPE_PDE_SIZE 0x00000001 /* */ +#define NV_PFAULT_FAULT_TYPE_PTE 0x00000002 /* */ +#define NV_PFAULT_FAULT_TYPE_VA_LIMIT_VIOLATION 0x00000003 /* */ +#define NV_PFAULT_FAULT_TYPE_UNBOUND_INST_BLOCK 0x00000004 /* */ +#define NV_PFAULT_FAULT_TYPE_PRIV_VIOLATION 0x00000005 /* */ +#define NV_PFAULT_FAULT_TYPE_RO_VIOLATION 0x00000006 /* */ +#define NV_PFAULT_FAULT_TYPE_WO_VIOLATION 0x00000007 /* */ +#define NV_PFAULT_FAULT_TYPE_PITCH_MASK_VIOLATION 0x00000008 /* */ +#define NV_PFAULT_FAULT_TYPE_WORK_CREATION 0x00000009 /* */ +#define NV_PFAULT_FAULT_TYPE_UNSUPPORTED_APERTURE 0x0000000a /* */ +#define NV_PFAULT_FAULT_TYPE_COMPRESSION_FAILURE 0x0000000b /* */ +#define NV_PFAULT_FAULT_TYPE_UNSUPPORTED_KIND 0x0000000c /* */ +#define NV_PFAULT_FAULT_TYPE_REGION_VIOLATION 0x0000000d /* */ +#define NV_PFAULT_FAULT_TYPE_POISONED 0x0000000e /* */ +#define NV_PFAULT_FAULT_TYPE_ATOMIC_VIOLATION 0x0000000f /* */ +#define NV_PFAULT_CLIENT 14:8 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_0 0x00000000 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_1 0x00000001 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_2 0x00000002 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_3 0x00000003 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_4 0x00000004 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_5 0x00000005 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_6 0x00000006 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_7 0x00000007 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_0 0x00000008 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_1 0x00000009 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_2 0x0000000A /* */ +#define NV_PFAULT_CLIENT_GPC_PE_3 0x0000000B /* */ +#define NV_PFAULT_CLIENT_GPC_PE_4 0x0000000C /* */ +#define NV_PFAULT_CLIENT_GPC_PE_5 0x0000000D /* */ +#define NV_PFAULT_CLIENT_GPC_PE_6 0x0000000E /* */ +#define NV_PFAULT_CLIENT_GPC_PE_7 0x0000000F /* */ +#define NV_PFAULT_CLIENT_GPC_RAST 0x00000010 /* */ +#define NV_PFAULT_CLIENT_GPC_GCC 0x00000011 /* */ +#define NV_PFAULT_CLIENT_GPC_GPCCS 0x00000012 /* */ +#define NV_PFAULT_CLIENT_GPC_PROP_0 0x00000013 /* */ +#define NV_PFAULT_CLIENT_GPC_PROP_1 0x00000014 /* */ +#define NV_PFAULT_CLIENT_GPC_PROP_2 0x00000015 /* */ +#define NV_PFAULT_CLIENT_GPC_PROP_3 0x00000016 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_8 0x00000021 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_9 0x00000022 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_10 0x00000023 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_11 0x00000024 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_12 0x00000025 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_13 0x00000026 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_14 0x00000027 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_15 0x00000028 /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_0 0x00000029 /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_1 0x0000002A /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_2 0x0000002B /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_3 0x0000002C /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_4 0x0000002D /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_5 0x0000002E /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_6 0x0000002F /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_7 0x00000030 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_8 0x00000031 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_9 0x00000032 /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_8 0x00000033 /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_9 0x00000034 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_16 0x00000035 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_17 0x00000036 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_18 0x00000037 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_19 0x00000038 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_10 0x00000039 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_11 0x0000003A /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_10 0x0000003B /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_11 0x0000003C /* */ +#define NV_PFAULT_CLIENT_GPC_T1_20 0x0000003D /* */ +#define NV_PFAULT_CLIENT_GPC_T1_21 0x0000003E /* */ +#define NV_PFAULT_CLIENT_GPC_T1_22 0x0000003F /* */ +#define NV_PFAULT_CLIENT_GPC_T1_23 0x00000040 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_12 0x00000041 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_13 0x00000042 /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_12 0x00000043 /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_13 0x00000044 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_24 0x00000045 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_25 0x00000046 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_26 0x00000047 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_27 0x00000048 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_14 0x00000049 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_15 0x0000004A /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_14 0x0000004B /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_15 0x0000004C /* */ +#define NV_PFAULT_CLIENT_GPC_T1_28 0x0000004D /* */ +#define NV_PFAULT_CLIENT_GPC_T1_29 0x0000004E /* */ +#define NV_PFAULT_CLIENT_GPC_T1_30 0x0000004F /* */ +#define NV_PFAULT_CLIENT_GPC_T1_31 0x00000050 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_16 0x00000051 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_17 0x00000052 /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_16 0x00000053 /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_17 0x00000054 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_32 0x00000055 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_33 0x00000056 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_34 0x00000057 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_35 0x00000058 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_18 0x00000059 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_19 0x0000005A /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_18 0x0000005B /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_19 0x0000005C /* */ +#define NV_PFAULT_CLIENT_GPC_T1_36 0x0000005D /* */ +#define NV_PFAULT_CLIENT_GPC_T1_37 0x0000005E /* */ +#define NV_PFAULT_CLIENT_GPC_T1_38 0x0000005F /* */ +#define NV_PFAULT_CLIENT_GPC_T1_39 0x00000060 /* */ +#define NV_PFAULT_CLIENT_GPC_GPM 0x00000017 /* */ +#define NV_PFAULT_CLIENT_GPC_LTP_UTLB_0 0x00000018 /* */ +#define NV_PFAULT_CLIENT_GPC_LTP_UTLB_1 0x00000019 /* */ +#define NV_PFAULT_CLIENT_GPC_LTP_UTLB_2 0x0000001A /* */ +#define NV_PFAULT_CLIENT_GPC_LTP_UTLB_3 0x0000001B /* */ +#define NV_PFAULT_CLIENT_GPC_LTP_UTLB_4 0x0000001C /* */ +#define NV_PFAULT_CLIENT_GPC_LTP_UTLB_5 0x0000001D /* */ +#define NV_PFAULT_CLIENT_GPC_LTP_UTLB_6 0x0000001E /* */ +#define NV_PFAULT_CLIENT_GPC_LTP_UTLB_7 0x0000001F /* */ +#define NV_PFAULT_CLIENT_GPC_RGG_UTLB 0x00000020 /* */ +#define NV_PFAULT_CLIENT_HUB_CE0 0x00000001 /* */ +#define NV_PFAULT_CLIENT_HUB_CE1 0x00000002 /* */ +#define NV_PFAULT_CLIENT_HUB_DNISO 0x00000003 /* */ +#define NV_PFAULT_CLIENT_HUB_FE 0x00000004 /* */ +#define NV_PFAULT_CLIENT_HUB_FECS 0x00000005 /* */ +#define NV_PFAULT_CLIENT_HUB_HOST 0x00000006 /* */ +#define NV_PFAULT_CLIENT_HUB_HOST_CPU 0x00000007 /* */ +#define NV_PFAULT_CLIENT_HUB_HOST_CPU_NB 0x00000008 /* */ +#define NV_PFAULT_CLIENT_HUB_ISO 0x00000009 /* */ +#define NV_PFAULT_CLIENT_HUB_MMU 0x0000000A /* */ +#define NV_PFAULT_CLIENT_HUB_NVDEC 0x0000000B /* */ +#define NV_PFAULT_CLIENT_HUB_NVDEC0 0x0000000B /* */ +#define NV_PFAULT_CLIENT_HUB_NVENC1 0x0000000D /* */ +#define NV_PFAULT_CLIENT_HUB_NVENC2 0x00000033 /* */ +#define NV_PFAULT_CLIENT_HUB_NISO 0x0000000E /* */ +#define NV_PFAULT_CLIENT_HUB_P2P 0x0000000F /* */ +#define NV_PFAULT_CLIENT_HUB_PD 0x00000010 /* */ +#define NV_PFAULT_CLIENT_HUB_PERF 0x00000011 /* */ +#define NV_PFAULT_CLIENT_HUB_PMU 0x00000012 /* */ +#define NV_PFAULT_CLIENT_HUB_RASTERTWOD 0x00000013 /* */ +#define NV_PFAULT_CLIENT_HUB_SCC 0x00000014 /* */ +#define NV_PFAULT_CLIENT_HUB_SCC_NB 0x00000015 /* */ +#define NV_PFAULT_CLIENT_HUB_SEC 0x00000016 /* */ +#define NV_PFAULT_CLIENT_HUB_SSYNC 0x00000017 /* */ +#define NV_PFAULT_CLIENT_HUB_NVDEC1 0x0000003A /* */ +#define NV_PFAULT_CLIENT_HUB_NVDEC2 0x0000003B /* */ +#define NV_PFAULT_CLIENT_HUB_NVJPG0 0x0000003C /* */ +#define NV_PFAULT_CLIENT_HUB_VIP 0x00000000 /* */ +#define NV_PFAULT_CLIENT_HUB_GRCOPY 0x00000018 /* */ +#define NV_PFAULT_CLIENT_HUB_CE2 0x00000018 /* */ +#define NV_PFAULT_CLIENT_HUB_XV 0x00000019 /* */ +#define NV_PFAULT_CLIENT_HUB_MMU_NB 0x0000001A /* */ +#define NV_PFAULT_CLIENT_HUB_NVENC 0x0000001B /* */ +#define NV_PFAULT_CLIENT_HUB_NVENC0 0x0000001B /* */ +#define NV_PFAULT_CLIENT_HUB_DFALCON 0x0000001C /* */ +#define NV_PFAULT_CLIENT_HUB_SKED 0x0000001D /* */ +#define NV_PFAULT_CLIENT_HUB_AFALCON 0x0000001E /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE0 0x00000020 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE1 0x00000021 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE2 0x00000022 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE3 0x00000023 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE4 0x00000024 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE5 0x00000025 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE6 0x00000026 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE7 0x00000027 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE8 0x00000028 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE9 0x00000029 /* */ +#define NV_PFAULT_CLIENT_HUB_HSHUB 0x0000002A /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X0 0x0000002B /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X1 0x0000002C /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X2 0x0000002D /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X3 0x0000002E /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X4 0x0000002F /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X5 0x00000030 /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X6 0x00000031 /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X7 0x00000032 /* */ +#define NV_PFAULT_CLIENT_HUB_VPR_SCRUBBER0 0x00000034 /* */ +#define NV_PFAULT_CLIENT_HUB_VPR_SCRUBBER1 0x00000035 /* */ +#define NV_PFAULT_CLIENT_HUB_DWBIF 0x00000036 /* */ +#define NV_PFAULT_CLIENT_HUB_FBFALCON 0x00000037 /* */ +#define NV_PFAULT_CLIENT_HUB_CE_SHIM 0x00000038 /* */ +#define NV_PFAULT_CLIENT_HUB_GSP 0x00000039 /* */ +#define NV_PFAULT_CLIENT_HUB_DONT_CARE 0x0000001F /* */ +#define NV_PFAULT_ACCESS_TYPE 19:16 /* */ +#define NV_PFAULT_ACCESS_TYPE_READ 0x00000000 /* */ +#define NV_PFAULT_ACCESS_TYPE_WRITE 0x00000001 /* */ +#define NV_PFAULT_ACCESS_TYPE_ATOMIC 0x00000002 /* */ +#define NV_PFAULT_ACCESS_TYPE_PREFETCH 0x00000003 /* */ +#define NV_PFAULT_ACCESS_TYPE_VIRT_READ 0x00000000 /* */ +#define NV_PFAULT_ACCESS_TYPE_VIRT_WRITE 0x00000001 /* */ +#define NV_PFAULT_ACCESS_TYPE_VIRT_ATOMIC 0x00000002 /* */ +#define NV_PFAULT_ACCESS_TYPE_VIRT_ATOMIC_STRONG 0x00000002 /* */ +#define NV_PFAULT_ACCESS_TYPE_VIRT_PREFETCH 0x00000003 /* */ +#define NV_PFAULT_ACCESS_TYPE_VIRT_ATOMIC_WEAK 0x00000004 /* */ +#define NV_PFAULT_ACCESS_TYPE_PHYS_READ 0x00000008 /* */ +#define NV_PFAULT_ACCESS_TYPE_PHYS_WRITE 0x00000009 /* */ +#define NV_PFAULT_ACCESS_TYPE_PHYS_ATOMIC 0x0000000a /* */ +#define NV_PFAULT_ACCESS_TYPE_PHYS_PREFETCH 0x0000000b /* */ +#define NV_PFAULT_MMU_CLIENT_TYPE 20:20 /* */ +#define NV_PFAULT_MMU_CLIENT_TYPE_GPC 0x00000000 /* */ +#define NV_PFAULT_MMU_CLIENT_TYPE_HUB 0x00000001 /* */ +#define NV_PFAULT_GPC_ID 28:24 /* */ +#define NV_PFAULT_PROTECTED_MODE 29:29 /* */ +#define NV_PFAULT_REPLAYABLE_FAULT_EN 30:30 /* */ +#define NV_PFAULT_VALID 31:31 /* */ +#endif // __tu102_dev_fault_h__ diff --git a/src/nouveau/headers/nvidia/hwref/turing/tu102/dev_mmu.h b/src/nouveau/headers/nvidia/hwref/turing/tu102/dev_mmu.h new file mode 100644 index 00000000000..ce9464c2c29 --- /dev/null +++ b/src/nouveau/headers/nvidia/hwref/turing/tu102/dev_mmu.h @@ -0,0 +1,649 @@ +/******************************************************************************* + Copyright (c) 2003-2016 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + + +#ifndef __tu102_dev_mmu_h__ +#define __tu102_dev_mmu_h__ +/* This file is autogenerated. Do not edit */ +#define NV_MMU_PDE /* ----G */ +#define NV_MMU_PDE_APERTURE_BIG (0*32+1):(0*32+0) /* RWXVF */ +#define NV_MMU_PDE_APERTURE_BIG_INVALID 0x00000000 /* RW--V */ +#define NV_MMU_PDE_APERTURE_BIG_VIDEO_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_PDE_APERTURE_BIG_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_PDE_APERTURE_BIG_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_PDE_SIZE (0*32+3):(0*32+2) /* RWXVF */ +#define NV_MMU_PDE_SIZE_FULL 0x00000000 /* RW--V */ +#define NV_MMU_PDE_SIZE_HALF 0x00000001 /* RW--V */ +#define NV_MMU_PDE_SIZE_QUARTER 0x00000002 /* RW--V */ +#define NV_MMU_PDE_SIZE_EIGHTH 0x00000003 /* RW--V */ +#define NV_MMU_PDE_ADDRESS_BIG_SYS (0*32+31):(0*32+4) /* RWXVF */ +#define NV_MMU_PDE_ADDRESS_BIG_VID (0*32+31-3):(0*32+4) /* RWXVF */ +#define NV_MMU_PDE_ADDRESS_BIG_VID_PEER (0*32+31):(0*32+32-3) /* RWXVF */ +#define NV_MMU_PDE_ADDRESS_BIG_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_PDE_APERTURE_SMALL (1*32+1):(1*32+0) /* RWXVF */ +#define NV_MMU_PDE_APERTURE_SMALL_INVALID 0x00000000 /* RW--V */ +#define NV_MMU_PDE_APERTURE_SMALL_VIDEO_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_PDE_APERTURE_SMALL_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_PDE_APERTURE_SMALL_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_PDE_VOL_SMALL (1*32+2):(1*32+2) /* RWXVF */ +#define NV_MMU_PDE_VOL_SMALL_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_PDE_VOL_SMALL_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_PDE_VOL_BIG (1*32+3):(1*32+3) /* RWXVF */ +#define NV_MMU_PDE_VOL_BIG_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_PDE_VOL_BIG_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_PDE_ADDRESS_SMALL_SYS (1*32+31):(1*32+4) /* RWXVF */ +#define NV_MMU_PDE_ADDRESS_SMALL_VID (1*32+31-3):(1*32+4) /* RWXVF */ +#define NV_MMU_PDE_ADDRESS_SMALL_VID_PEER (1*32+31):(1*32+32-3) /* RWXVF */ +#define NV_MMU_PDE_ADDRESS_SMALL_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_PDE_ADDRESS_SHIFT 0x0000000c /* */ +#define NV_MMU_PDE__SIZE 8 +#define NV_MMU_PTE /* ----G */ +#define NV_MMU_PTE_VALID (0*32+0):(0*32+0) /* RWXVF */ +#define NV_MMU_PTE_VALID_TRUE 0x1 /* RW--V */ +#define NV_MMU_PTE_VALID_FALSE 0x0 /* RW--V */ +#define NV_MMU_PTE_PRIVILEGE (0*32+1):(0*32+1) /* RWXVF */ +#define NV_MMU_PTE_PRIVILEGE_TRUE 0x1 /* RW--V */ +#define NV_MMU_PTE_PRIVILEGE_FALSE 0x0 /* RW--V */ +#define NV_MMU_PTE_READ_ONLY (0*32+2):(0*32+2) /* RWXVF */ +#define NV_MMU_PTE_READ_ONLY_TRUE 0x1 /* RW--V */ +#define NV_MMU_PTE_READ_ONLY_FALSE 0x0 /* RW--V */ +#define NV_MMU_PTE_ENCRYPTED (0*32+3):(0*32+3) /* RWXVF */ +#define NV_MMU_PTE_ENCRYPTED_TRUE 0x00000001 /* R---V */ +#define NV_MMU_PTE_ENCRYPTED_FALSE 0x00000000 /* R---V */ +#define NV_MMU_PTE_ADDRESS_SYS (0*32+31):(0*32+4) /* RWXVF */ +#define NV_MMU_PTE_ADDRESS_VID (0*32+31-3):(0*32+4) /* RWXVF */ +#define NV_MMU_PTE_ADDRESS_VID_PEER (0*32+31):(0*32+32-3) /* RWXVF */ +#define NV_MMU_PTE_ADDRESS_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_PTE_ADDRESS_VID_PEER_1 0x00000001 /* RW--V */ +#define NV_MMU_PTE_ADDRESS_VID_PEER_2 0x00000002 /* RW--V */ +#define NV_MMU_PTE_ADDRESS_VID_PEER_3 0x00000003 /* RW--V */ +#define NV_MMU_PTE_ADDRESS_VID_PEER_4 0x00000004 /* RW--V */ +#define NV_MMU_PTE_ADDRESS_VID_PEER_5 0x00000005 /* RW--V */ +#define NV_MMU_PTE_ADDRESS_VID_PEER_6 0x00000006 /* RW--V */ +#define NV_MMU_PTE_ADDRESS_VID_PEER_7 0x00000007 /* RW--V */ +#define NV_MMU_PTE_VOL (1*32+0):(1*32+0) /* RWXVF */ +#define NV_MMU_PTE_VOL_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_PTE_VOL_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_PTE_APERTURE (1*32+2):(1*32+1) /* RWXVF */ +#define NV_MMU_PTE_APERTURE_VIDEO_MEMORY 0x00000000 /* RW--V */ +#define NV_MMU_PTE_APERTURE_PEER_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_PTE_APERTURE_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_PTE_LOCK (1*32+3):(1*32+3) /* RWXVF */ +#define NV_MMU_PTE_LOCK_TRUE 0x1 /* RW--V */ +#define NV_MMU_PTE_LOCK_FALSE 0x0 /* RW--V */ +#define NV_MMU_PTE_ATOMIC_DISABLE (1*32+3):(1*32+3) /* RWXVF */ +#define NV_MMU_PTE_ATOMIC_DISABLE_TRUE 0x1 /* RW--V */ +#define NV_MMU_PTE_ATOMIC_DISABLE_FALSE 0x0 /* RW--V */ +#define NV_MMU_PTE_COMPTAGLINE (1*32+20+11):(1*32+12) /* RWXVF */ +#define NV_MMU_PTE_READ_DISABLE (1*32+30):(1*32+30) /* RWXVF */ +#define NV_MMU_PTE_READ_DISABLE_TRUE 0x1 /* RW--V */ +#define NV_MMU_PTE_READ_DISABLE_FALSE 0x0 /* RW--V */ +#define NV_MMU_PTE_WRITE_DISABLE (1*32+31):(1*32+31) /* RWXVF */ +#define NV_MMU_PTE_WRITE_DISABLE_TRUE 0x1 /* RW--V */ +#define NV_MMU_PTE_WRITE_DISABLE_FALSE 0x0 /* RW--V */ +#define NV_MMU_PTE_ADDRESS_SHIFT 0x0000000c /* */ +#define NV_MMU_PTE__SIZE 8 +#define NV_MMU_PTE_COMPTAGS_NONE 0x0 /* */ +#define NV_MMU_PTE_COMPTAGS_1 0x1 /* */ +#define NV_MMU_PTE_COMPTAGS_2 0x2 /* */ +#define NV_MMU_PTE_KIND (1*32+11):(1*32+4) /* RWXVF */ +#define NV_MMU_PTE_KIND_INVALID 0x07 /* R---V */ +#define NV_MMU_PTE_KIND_PITCH 0x00 /* R---V */ +#define NV_MMU_PTE_KIND_GENERIC_MEMORY 0x06 /* R---V */ +#define NV_MMU_PTE_KIND_Z16 0x01 /* R---V */ +#define NV_MMU_PTE_KIND_S8 0x02 /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24 0x03 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8 0x04 /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8 0x05 /* R---V */ +#define NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE 0x08 /* R---V */ +#define NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE_DISABLE_PLC 0x09 /* R---V */ +#define NV_MMU_PTE_KIND_S8_COMPRESSIBLE_DISABLE_PLC 0x0A /* R---V */ +#define NV_MMU_PTE_KIND_Z16_COMPRESSIBLE_DISABLE_PLC 0x0B /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_COMPRESSIBLE_DISABLE_PLC 0x0C /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8_COMPRESSIBLE_DISABLE_PLC 0x0D /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_COMPRESSIBLE_DISABLE_PLC 0x0E /* R---V */ +#define NV_MMU_PTE_KIND_SMSKED_MESSAGE 0x0F /* R---V */ +#define NV_MMU_PTE_KIND_Z16_2C 0x2a /* R---V */ +#define NV_MMU_PTE_KIND_Z16_MS2_2C 0x11 /* R---V */ +#define NV_MMU_PTE_KIND_Z16_MS4_2C 0xC3 /* R---V */ +#define NV_MMU_PTE_KIND_Z16_MS8_2C 0x46 /* R---V */ +#define NV_MMU_PTE_KIND_Z16_MS16_2C 0x6c /* R---V */ +#define NV_MMU_PTE_KIND_Z16_2Z 0x6b /* R---V */ +#define NV_MMU_PTE_KIND_Z16_MS2_2Z 0x10 /* R---V */ +#define NV_MMU_PTE_KIND_Z16_MS4_2Z 0x60 /* R---V */ +#define NV_MMU_PTE_KIND_Z16_MS8_2Z 0x61 /* R---V */ +#define NV_MMU_PTE_KIND_Z16_MS16_2Z 0x62 /* R---V */ +#define NV_MMU_PTE_KIND_Z16_2CZ 0x36 /* R---V */ +#define NV_MMU_PTE_KIND_Z16_MS2_2CZ 0x37 /* R---V */ +#define NV_MMU_PTE_KIND_Z16_MS4_2CZ 0x38 /* R---V */ +#define NV_MMU_PTE_KIND_Z16_MS8_2CZ 0x39 /* R---V */ +#define NV_MMU_PTE_KIND_Z16_MS16_2CZ 0x5f /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_1Z 0x12 /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_MS2_1Z 0x13 /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_MS4_1Z 0x14 /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_MS8_1Z 0x15 /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_MS16_1Z 0x16 /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_2CZ 0x17 /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_MS2_2CZ 0x18 /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_MS4_2CZ 0x19 /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_MS8_2CZ 0x1a /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_MS16_2CZ 0x1b /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_2CS 0x1c /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_MS2_2CS 0x1d /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_MS4_2CS 0x1e /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_MS8_2CS 0x1f /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_MS16_2CS 0x20 /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_4CSZV 0x21 /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_MS2_4CSZV 0x22 /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_MS4_4CSZV 0x23 /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_MS8_4CSZV 0x24 /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_MS16_4CSZV 0x25 /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12 0x26 /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4 0x27 /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8 0x28 /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24 0x29 /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_1ZV 0x2e /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_1ZV 0x2f /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_1ZV 0x30 /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_1ZV 0x31 /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2CS 0x32 /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2CS 0x33 /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2CS 0x34 /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2CS 0x35 /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2CZV 0x3a /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2CZV 0x3b /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2CZV 0x3c /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2CZV 0x3d /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2ZV 0x3e /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2ZV 0x3f /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2ZV 0x40 /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2ZV 0x41 /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_4CSZV 0x42 /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_4CSZV 0x43 /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_4CSZV 0x44 /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_4CSZV 0x45 /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_1Z 0x47 /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_MS2_1Z 0x48 /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_MS4_1Z 0x49 /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_MS8_1Z 0x4a /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_MS16_1Z 0x4b /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_2CS 0x4c /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_MS2_2CS 0x4d /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_MS4_2CS 0x4e /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_MS8_2CS 0x4f /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_MS16_2CS 0x50 /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_2CZ 0x51 /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_MS2_2CZ 0x52 /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_MS4_2CZ 0x53 /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_MS8_2CZ 0x54 /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_MS16_2CZ 0x55 /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_4CSZV 0x56 /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_MS2_4CSZV 0x57 /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_MS4_4CSZV 0x58 /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_MS8_4CSZV 0x59 /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_MS16_4CSZV 0x5a /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12 0x5b /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4 0x5c /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8 0x5d /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24 0x5e /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_1ZV 0x63 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_1ZV 0x64 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_1ZV 0x65 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_1ZV 0x66 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2CS 0x67 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2CS 0x68 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2CS 0x69 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2CS 0x6a /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2CZV 0x6f /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2CZV 0x70 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2CZV 0x71 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2CZV 0x72 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2ZV 0x73 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2ZV 0x74 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2ZV 0x75 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2ZV 0x76 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_4CSZV 0x77 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_4CSZV 0x78 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_4CSZV 0x79 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_4CSZV 0x7a /* R---V */ +#define NV_MMU_PTE_KIND_ZF32 0x7b /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_1Z 0x7c /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_MS2_1Z 0x7d /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_MS4_1Z 0x7e /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_MS8_1Z 0x7f /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_MS16_1Z 0x80 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_2CS 0x81 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_MS2_2CS 0x82 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_MS4_2CS 0x83 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_MS8_2CS 0x84 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_MS16_2CS 0x85 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_2CZ 0x86 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_MS2_2CZ 0x87 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_MS4_2CZ 0x88 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_MS8_2CZ 0x89 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_MS16_2CZ 0x8a /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12 0x8b /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4 0x8c /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8 0x8d /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24 0x8e /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1CS 0x8f /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1CS 0x90 /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1CS 0x91 /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1CS 0x92 /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1ZV 0x97 /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1ZV 0x98 /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1ZV 0x99 /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1ZV 0x9a /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1CZV 0x9b /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1CZV 0x9c /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1CZV 0x9d /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1CZV 0x9e /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_2CS 0x9f /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_2CS 0xa0 /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_2CS 0xa1 /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_2CS 0xa2 /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_2CSZV 0xa3 /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_2CSZV 0xa4 /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_2CSZV 0xa5 /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_2CSZV 0xa6 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12 0xa7 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4 0xa8 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8 0xa9 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24 0xaa /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1CS 0xab /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1CS 0xac /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1CS 0xad /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1CS 0xae /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1ZV 0xb3 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1ZV 0xb4 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1ZV 0xb5 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1ZV 0xb6 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1CZV 0xb7 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1CZV 0xb8 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1CZV 0xb9 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1CZV 0xba /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_2CS 0xbb /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_2CS 0xbc /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_2CS 0xbd /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_2CS 0xbe /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_2CSZV 0xbf /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_2CSZV 0xc0 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_2CSZV 0xc1 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_2CSZV 0xc2 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8_1CS 0xc4 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_1CS 0xc5 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_1CS 0xc6 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_1CS 0xc7 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_1CS 0xc8 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8_2CSZV 0xce /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_2CSZV 0xcf /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_2CSZV 0xd0 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_2CSZV 0xd1 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_2CSZV 0xd2 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8_2CS 0xd3 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_2CS 0xd4 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_2CS 0xd5 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_2CS 0xd6 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_2CS 0xd7 /* R---V */ +#define NV_MMU_PTE_KIND_S8_2S 0x2b /* R---V */ +#define NV_MMU_PTE_KIND_GENERIC_16BX2 0xfe /* R---V */ +#define NV_MMU_PTE_KIND_C32_2C 0xd8 /* R---V */ +#define NV_MMU_PTE_KIND_C32_2CBR 0xd9 /* R---V */ +#define NV_MMU_PTE_KIND_C32_2CBA 0xda /* R---V */ +#define NV_MMU_PTE_KIND_C32_2CRA 0xdb /* R---V */ +#define NV_MMU_PTE_KIND_C32_2BRA 0xdc /* R---V */ +#define NV_MMU_PTE_KIND_C32_MS2_2C 0xdd /* R---V */ +#define NV_MMU_PTE_KIND_C32_MS2_2CBR 0xde /* R---V */ +#define NV_MMU_PTE_KIND_C32_MS2_4CBRA 0xcc /* R---V */ +#define NV_MMU_PTE_KIND_C32_MS4_2C 0xdf /* R---V */ +#define NV_MMU_PTE_KIND_C32_MS4_2CBR 0xe0 /* R---V */ +#define NV_MMU_PTE_KIND_C32_MS4_2CBA 0xe1 /* R---V */ +#define NV_MMU_PTE_KIND_C32_MS4_2CRA 0xe2 /* R---V */ +#define NV_MMU_PTE_KIND_C32_MS4_2BRA 0xe3 /* R---V */ +#define NV_MMU_PTE_KIND_C32_MS4_4CBRA 0x2c /* R---V */ +#define NV_MMU_PTE_KIND_C32_MS8_MS16_2C 0xe4 /* R---V */ +#define NV_MMU_PTE_KIND_C32_MS8_MS16_2CRA 0xe5 /* R---V */ +#define NV_MMU_PTE_KIND_C64_2C 0xe6 /* R---V */ +#define NV_MMU_PTE_KIND_C64_2CBR 0xe7 /* R---V */ +#define NV_MMU_PTE_KIND_C64_2CBA 0xe8 /* R---V */ +#define NV_MMU_PTE_KIND_C64_2CRA 0xe9 /* R---V */ +#define NV_MMU_PTE_KIND_C64_2BRA 0xea /* R---V */ +#define NV_MMU_PTE_KIND_C64_MS2_2C 0xeb /* R---V */ +#define NV_MMU_PTE_KIND_C64_MS2_2CBR 0xec /* R---V */ +#define NV_MMU_PTE_KIND_C64_MS2_4CBRA 0xcd /* R---V */ +#define NV_MMU_PTE_KIND_C64_MS4_2C 0xed /* R---V */ +#define NV_MMU_PTE_KIND_C64_MS4_2CBR 0xee /* R---V */ +#define NV_MMU_PTE_KIND_C64_MS4_2CBA 0xef /* R---V */ +#define NV_MMU_PTE_KIND_C64_MS4_2CRA 0xf0 /* R---V */ +#define NV_MMU_PTE_KIND_C64_MS4_2BRA 0xf1 /* R---V */ +#define NV_MMU_PTE_KIND_C64_MS4_4CBRA 0x2d /* R---V */ +#define NV_MMU_PTE_KIND_C64_MS8_MS16_2C 0xf2 /* R---V */ +#define NV_MMU_PTE_KIND_C64_MS8_MS16_2CRA 0xf3 /* R---V */ +#define NV_MMU_PTE_KIND_C128_2C 0xf4 /* R---V */ +#define NV_MMU_PTE_KIND_C128_2CR 0xf5 /* R---V */ +#define NV_MMU_PTE_KIND_C128_MS2_2C 0xf6 /* R---V */ +#define NV_MMU_PTE_KIND_C128_MS2_2CR 0xf7 /* R---V */ +#define NV_MMU_PTE_KIND_C128_MS4_2C 0xf8 /* R---V */ +#define NV_MMU_PTE_KIND_C128_MS4_2CR 0xf9 /* R---V */ +#define NV_MMU_PTE_KIND_C128_MS8_MS16_2C 0xfa /* R---V */ +#define NV_MMU_PTE_KIND_C128_MS8_MS16_2CR 0xfb /* R---V */ +#define NV_MMU_PTE_KIND_X8C24 0xfc /* R---V */ +#define NV_MMU_PTE_KIND_PITCH_NO_SWIZZLE 0xfd /* R---V */ +#define NV_MMU_PTE_KIND_SMHOST_MESSAGE 0xcb /* R---V */ +#define NV_MMU_VER1_PDE /* ----G */ +#define NV_MMU_VER1_PDE_APERTURE_BIG (0*32+1):(0*32+0) /* RWXVF */ +#define NV_MMU_VER1_PDE_APERTURE_BIG_INVALID 0x00000000 /* RW--V */ +#define NV_MMU_VER1_PDE_APERTURE_BIG_VIDEO_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_VER1_PDE_APERTURE_BIG_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_VER1_PDE_APERTURE_BIG_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_VER1_PDE_SIZE (0*32+3):(0*32+2) /* RWXVF */ +#define NV_MMU_VER1_PDE_SIZE_FULL 0x00000000 /* RW--V */ +#define NV_MMU_VER1_PDE_SIZE_HALF 0x00000001 /* RW--V */ +#define NV_MMU_VER1_PDE_SIZE_QUARTER 0x00000002 /* RW--V */ +#define NV_MMU_VER1_PDE_SIZE_EIGHTH 0x00000003 /* RW--V */ +#define NV_MMU_VER1_PDE_ADDRESS_BIG_SYS (0*32+31):(0*32+4) /* RWXVF */ +#define NV_MMU_VER1_PDE_ADDRESS_BIG_VID (0*32+31-3):(0*32+4) /* RWXVF */ +#define NV_MMU_VER1_PDE_ADDRESS_BIG_VID_PEER (0*32+31):(0*32+32-3) /* RWXVF */ +#define NV_MMU_VER1_PDE_ADDRESS_BIG_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_VER1_PDE_APERTURE_SMALL (1*32+1):(1*32+0) /* RWXVF */ +#define NV_MMU_VER1_PDE_APERTURE_SMALL_INVALID 0x00000000 /* RW--V */ +#define NV_MMU_VER1_PDE_APERTURE_SMALL_VIDEO_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_VER1_PDE_APERTURE_SMALL_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_VER1_PDE_APERTURE_SMALL_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_VER1_PDE_VOL_SMALL (1*32+2):(1*32+2) /* RWXVF */ +#define NV_MMU_VER1_PDE_VOL_SMALL_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_VER1_PDE_VOL_SMALL_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_VER1_PDE_VOL_BIG (1*32+3):(1*32+3) /* RWXVF */ +#define NV_MMU_VER1_PDE_VOL_BIG_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_VER1_PDE_VOL_BIG_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_VER1_PDE_ADDRESS_SMALL_SYS (1*32+31):(1*32+4) /* RWXVF */ +#define NV_MMU_VER1_PDE_ADDRESS_SMALL_VID (1*32+31-3):(1*32+4) /* RWXVF */ +#define NV_MMU_VER1_PDE_ADDRESS_SMALL_VID_PEER (1*32+31):(1*32+32-3) /* RWXVF */ +#define NV_MMU_VER1_PDE_ADDRESS_SMALL_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_VER1_PDE_ADDRESS_SHIFT 0x0000000c /* */ +#define NV_MMU_VER1_PDE__SIZE 8 +#define NV_MMU_VER1_PTE /* ----G */ +#define NV_MMU_VER1_PTE_VALID (0*32+0):(0*32+0) /* RWXVF */ +#define NV_MMU_VER1_PTE_VALID_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER1_PTE_VALID_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER1_PTE_PRIVILEGE (0*32+1):(0*32+1) /* RWXVF */ +#define NV_MMU_VER1_PTE_PRIVILEGE_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER1_PTE_PRIVILEGE_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER1_PTE_READ_ONLY (0*32+2):(0*32+2) /* RWXVF */ +#define NV_MMU_VER1_PTE_READ_ONLY_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER1_PTE_READ_ONLY_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER1_PTE_ENCRYPTED (0*32+3):(0*32+3) /* RWXVF */ +#define NV_MMU_VER1_PTE_ENCRYPTED_TRUE 0x00000001 /* R---V */ +#define NV_MMU_VER1_PTE_ENCRYPTED_FALSE 0x00000000 /* R---V */ +#define NV_MMU_VER1_PTE_ADDRESS_SYS (0*32+31):(0*32+4) /* RWXVF */ +#define NV_MMU_VER1_PTE_ADDRESS_VID (0*32+31-3):(0*32+4) /* RWXVF */ +#define NV_MMU_VER1_PTE_ADDRESS_VID_PEER (0*32+31):(0*32+32-3) /* RWXVF */ +#define NV_MMU_VER1_PTE_ADDRESS_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_VER1_PTE_ADDRESS_VID_PEER_1 0x00000001 /* RW--V */ +#define NV_MMU_VER1_PTE_ADDRESS_VID_PEER_2 0x00000002 /* RW--V */ +#define NV_MMU_VER1_PTE_ADDRESS_VID_PEER_3 0x00000003 /* RW--V */ +#define NV_MMU_VER1_PTE_ADDRESS_VID_PEER_4 0x00000004 /* RW--V */ +#define NV_MMU_VER1_PTE_ADDRESS_VID_PEER_5 0x00000005 /* RW--V */ +#define NV_MMU_VER1_PTE_ADDRESS_VID_PEER_6 0x00000006 /* RW--V */ +#define NV_MMU_VER1_PTE_ADDRESS_VID_PEER_7 0x00000007 /* RW--V */ +#define NV_MMU_VER1_PTE_VOL (1*32+0):(1*32+0) /* RWXVF */ +#define NV_MMU_VER1_PTE_VOL_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_VER1_PTE_VOL_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_VER1_PTE_APERTURE (1*32+2):(1*32+1) /* RWXVF */ +#define NV_MMU_VER1_PTE_APERTURE_VIDEO_MEMORY 0x00000000 /* RW--V */ +#define NV_MMU_VER1_PTE_APERTURE_PEER_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_VER1_PTE_APERTURE_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_VER1_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_VER1_PTE_ATOMIC_DISABLE (1*32+3):(1*32+3) /* RWXVF */ +#define NV_MMU_VER1_PTE_ATOMIC_DISABLE_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER1_PTE_ATOMIC_DISABLE_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER1_PTE_COMPTAGLINE (1*32+20+11):(1*32+12) /* RWXVF */ +#define NV_MMU_VER1_PTE_KIND (1*32+11):(1*32+4) /* RWXVF */ +#define NV_MMU_VER1_PTE_ADDRESS_SHIFT 0x0000000c /* */ +#define NV_MMU_VER1_PTE__SIZE 8 +#define NV_MMU_VER1_PTE_COMPTAGS_NONE 0x0 /* */ +#define NV_MMU_VER1_PTE_COMPTAGS_1 0x1 /* */ +#define NV_MMU_VER1_PTE_COMPTAGS_2 0x2 /* */ +#define NV_MMU_NEW_PDE /* ----G */ +#define NV_MMU_NEW_PDE_IS_PTE 0:0 /* RWXVF */ +#define NV_MMU_NEW_PDE_IS_PTE_TRUE 0x1 /* RW--V */ +#define NV_MMU_NEW_PDE_IS_PTE_FALSE 0x0 /* RW--V */ +#define NV_MMU_NEW_PDE_IS_PDE 0:0 /* RWXVF */ +#define NV_MMU_NEW_PDE_IS_PDE_TRUE 0x0 /* RW--V */ +#define NV_MMU_NEW_PDE_IS_PDE_FALSE 0x1 /* RW--V */ +#define NV_MMU_NEW_PDE_VALID 0:0 /* RWXVF */ +#define NV_MMU_NEW_PDE_VALID_TRUE 0x1 /* RW--V */ +#define NV_MMU_NEW_PDE_VALID_FALSE 0x0 /* RW--V */ +#define NV_MMU_NEW_PDE_APERTURE 2:1 /* RWXVF */ +#define NV_MMU_NEW_PDE_APERTURE_INVALID 0x00000000 /* RW--V */ +#define NV_MMU_NEW_PDE_APERTURE_VIDEO_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_NEW_PDE_APERTURE_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_NEW_PDE_APERTURE_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_NEW_PDE_VOL 3:3 /* RWXVF */ +#define NV_MMU_NEW_PDE_VOL_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_NEW_PDE_VOL_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_NEW_PDE_NO_ATS 5:5 /* RWXVF */ +#define NV_MMU_NEW_PDE_NO_ATS_TRUE 0x1 /* RW--V */ +#define NV_MMU_NEW_PDE_NO_ATS_FALSE 0x0 /* RW--V */ +#define NV_MMU_NEW_PDE_ADDRESS_SYS 53:8 /* RWXVF */ +#define NV_MMU_NEW_PDE_ADDRESS_VID (35-3):8 /* RWXVF */ +#define NV_MMU_NEW_PDE_ADDRESS_VID_PEER 35:(36-3) /* RWXVF */ +#define NV_MMU_NEW_PDE_ADDRESS_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_NEW_PDE_ADDRESS_SHIFT 0x0000000c /* */ +#define NV_MMU_NEW_PDE__SIZE 8 +#define NV_MMU_NEW_DUAL_PDE /* ----G */ +#define NV_MMU_NEW_DUAL_PDE_IS_PTE 0:0 /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_IS_PTE_TRUE 0x1 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_IS_PTE_FALSE 0x0 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_IS_PDE 0:0 /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_IS_PDE_TRUE 0x0 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_IS_PDE_FALSE 0x1 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_VALID 0:0 /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_VALID_TRUE 0x1 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_VALID_FALSE 0x0 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_APERTURE_BIG 2:1 /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_APERTURE_BIG_INVALID 0x00000000 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_APERTURE_BIG_VIDEO_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_APERTURE_BIG_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_APERTURE_BIG_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_VOL_BIG 3:3 /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_VOL_BIG_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_VOL_BIG_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_NO_ATS 5:5 /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_NO_ATS_TRUE 0x1 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_NO_ATS_FALSE 0x0 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_ADDRESS_BIG_SYS 53:(8-4) /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_ADDRESS_BIG_VID (35-3):(8-4) /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_ADDRESS_BIG_VID_PEER 35:(36-3) /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_ADDRESS_BIG_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_APERTURE_SMALL 66:65 /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_APERTURE_SMALL_INVALID 0x00000000 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_APERTURE_SMALL_VIDEO_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_APERTURE_SMALL_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_APERTURE_SMALL_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_VOL_SMALL 67:67 /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_VOL_SMALL_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_VOL_SMALL_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_ADDRESS_SMALL_SYS 117:72 /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_ADDRESS_SMALL_VID (99-3):72 /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_ADDRESS_SMALL_VID_PEER 99:(100-3) /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_ADDRESS_SMALL_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_ADDRESS_SHIFT 0x0000000c /* */ +#define NV_MMU_NEW_DUAL_PDE_ADDRESS_BIG_SHIFT 8 /* */ +#define NV_MMU_NEW_DUAL_PDE__SIZE 16 +#define NV_MMU_NEW_PTE /* ----G */ +#define NV_MMU_NEW_PTE_VALID 0:0 /* RWXVF */ +#define NV_MMU_NEW_PTE_VALID_TRUE 0x1 /* RW--V */ +#define NV_MMU_NEW_PTE_VALID_FALSE 0x0 /* RW--V */ +#define NV_MMU_NEW_PTE_APERTURE 2:1 /* RWXVF */ +#define NV_MMU_NEW_PTE_APERTURE_VIDEO_MEMORY 0x00000000 /* RW--V */ +#define NV_MMU_NEW_PTE_APERTURE_PEER_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_NEW_PTE_APERTURE_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_NEW_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_NEW_PTE_VOL 3:3 /* RWXVF */ +#define NV_MMU_NEW_PTE_VOL_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_NEW_PTE_VOL_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_NEW_PTE_ENCRYPTED 4:4 /* RWXVF */ +#define NV_MMU_NEW_PTE_ENCRYPTED_TRUE 0x00000001 /* R---V */ +#define NV_MMU_NEW_PTE_ENCRYPTED_FALSE 0x00000000 /* R---V */ +#define NV_MMU_NEW_PTE_PRIVILEGE 5:5 /* RWXVF */ +#define NV_MMU_NEW_PTE_PRIVILEGE_TRUE 0x1 /* RW--V */ +#define NV_MMU_NEW_PTE_PRIVILEGE_FALSE 0x0 /* RW--V */ +#define NV_MMU_NEW_PTE_READ_ONLY 6:6 /* RWXVF */ +#define NV_MMU_NEW_PTE_READ_ONLY_TRUE 0x1 /* RW--V */ +#define NV_MMU_NEW_PTE_READ_ONLY_FALSE 0x0 /* RW--V */ +#define NV_MMU_NEW_PTE_ATOMIC_DISABLE 7:7 /* RWXVF */ +#define NV_MMU_NEW_PTE_ATOMIC_DISABLE_TRUE 0x1 /* RW--V */ +#define NV_MMU_NEW_PTE_ATOMIC_DISABLE_FALSE 0x0 /* RW--V */ +#define NV_MMU_NEW_PTE_ADDRESS_SYS 53:8 /* RWXVF */ +#define NV_MMU_NEW_PTE_ADDRESS_VID (35-3):8 /* RWXVF */ +#define NV_MMU_NEW_PTE_ADDRESS_VID_PEER 35:(36-3) /* RWXVF */ +#define NV_MMU_NEW_PTE_ADDRESS_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_NEW_PTE_ADDRESS_VID_PEER_1 0x00000001 /* RW--V */ +#define NV_MMU_NEW_PTE_ADDRESS_VID_PEER_2 0x00000002 /* RW--V */ +#define NV_MMU_NEW_PTE_ADDRESS_VID_PEER_3 0x00000003 /* RW--V */ +#define NV_MMU_NEW_PTE_ADDRESS_VID_PEER_4 0x00000004 /* RW--V */ +#define NV_MMU_NEW_PTE_ADDRESS_VID_PEER_5 0x00000005 /* RW--V */ +#define NV_MMU_NEW_PTE_ADDRESS_VID_PEER_6 0x00000006 /* RW--V */ +#define NV_MMU_NEW_PTE_ADDRESS_VID_PEER_7 0x00000007 /* RW--V */ +#define NV_MMU_NEW_PTE_COMPTAGLINE (20+35):36 /* RWXVF */ +#define NV_MMU_NEW_PTE_KIND 63:56 /* RWXVF */ +#define NV_MMU_NEW_PTE_ADDRESS_SHIFT 0x0000000c /* */ +#define NV_MMU_NEW_PTE__SIZE 8 +#define NV_MMU_VER2_PDE /* ----G */ +#define NV_MMU_VER2_PDE_IS_PTE 0:0 /* RWXVF */ +#define NV_MMU_VER2_PDE_IS_PTE_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER2_PDE_IS_PTE_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER2_PDE_IS_PDE 0:0 /* RWXVF */ +#define NV_MMU_VER2_PDE_IS_PDE_TRUE 0x0 /* RW--V */ +#define NV_MMU_VER2_PDE_IS_PDE_FALSE 0x1 /* RW--V */ +#define NV_MMU_VER2_PDE_VALID 0:0 /* RWXVF */ +#define NV_MMU_VER2_PDE_VALID_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER2_PDE_VALID_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER2_PDE_APERTURE 2:1 /* RWXVF */ +#define NV_MMU_VER2_PDE_APERTURE_INVALID 0x00000000 /* RW--V */ +#define NV_MMU_VER2_PDE_APERTURE_VIDEO_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_VER2_PDE_APERTURE_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_VER2_PDE_APERTURE_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_VER2_PDE_VOL 3:3 /* RWXVF */ +#define NV_MMU_VER2_PDE_VOL_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_VER2_PDE_VOL_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_VER2_PDE_NO_ATS 5:5 /* RWXVF */ +#define NV_MMU_VER2_PDE_NO_ATS_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER2_PDE_NO_ATS_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER2_PDE_ADDRESS_SYS 53:8 /* RWXVF */ +#define NV_MMU_VER2_PDE_ADDRESS_VID (35-3):8 /* RWXVF */ +#define NV_MMU_VER2_PDE_ADDRESS_VID_PEER 35:(36-3) /* RWXVF */ +#define NV_MMU_VER2_PDE_ADDRESS_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_VER2_PDE_ADDRESS_SHIFT 0x0000000c /* */ +#define NV_MMU_VER2_PDE__SIZE 8 +#define NV_MMU_VER2_DUAL_PDE /* ----G */ +#define NV_MMU_VER2_DUAL_PDE_IS_PTE 0:0 /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_IS_PTE_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_IS_PTE_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_IS_PDE 0:0 /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_IS_PDE_TRUE 0x0 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_IS_PDE_FALSE 0x1 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_VALID 0:0 /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_VALID_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_VALID_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_APERTURE_BIG 2:1 /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_APERTURE_BIG_INVALID 0x00000000 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_APERTURE_BIG_VIDEO_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_APERTURE_BIG_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_APERTURE_BIG_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_VOL_BIG 3:3 /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_VOL_BIG_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_VOL_BIG_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_NO_ATS 5:5 /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_NO_ATS_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_NO_ATS_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_ADDRESS_BIG_SYS 53:(8-4) /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_ADDRESS_BIG_VID (35-3):(8-4) /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_ADDRESS_BIG_VID_PEER 35:(36-3) /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_ADDRESS_BIG_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_APERTURE_SMALL 66:65 /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_APERTURE_SMALL_INVALID 0x00000000 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_APERTURE_SMALL_VIDEO_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_APERTURE_SMALL_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_APERTURE_SMALL_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_VOL_SMALL 67:67 /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_VOL_SMALL_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_VOL_SMALL_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_ADDRESS_SMALL_SYS 117:72 /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_ADDRESS_SMALL_VID (99-3):72 /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_ADDRESS_SMALL_VID_PEER 99:(100-3) /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_ADDRESS_SMALL_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_ADDRESS_SHIFT 0x0000000c /* */ +#define NV_MMU_VER2_DUAL_PDE_ADDRESS_BIG_SHIFT 8 /* */ +#define NV_MMU_VER2_DUAL_PDE__SIZE 16 +#define NV_MMU_VER2_PTE /* ----G */ +#define NV_MMU_VER2_PTE_VALID 0:0 /* RWXVF */ +#define NV_MMU_VER2_PTE_VALID_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER2_PTE_VALID_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER2_PTE_APERTURE 2:1 /* RWXVF */ +#define NV_MMU_VER2_PTE_APERTURE_VIDEO_MEMORY 0x00000000 /* RW--V */ +#define NV_MMU_VER2_PTE_APERTURE_PEER_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_VER2_PTE_APERTURE_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_VER2_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_VER2_PTE_VOL 3:3 /* RWXVF */ +#define NV_MMU_VER2_PTE_VOL_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_VER2_PTE_VOL_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_VER2_PTE_ENCRYPTED 4:4 /* RWXVF */ +#define NV_MMU_VER2_PTE_ENCRYPTED_TRUE 0x00000001 /* R---V */ +#define NV_MMU_VER2_PTE_ENCRYPTED_FALSE 0x00000000 /* R---V */ +#define NV_MMU_VER2_PTE_PRIVILEGE 5:5 /* RWXVF */ +#define NV_MMU_VER2_PTE_PRIVILEGE_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER2_PTE_PRIVILEGE_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER2_PTE_READ_ONLY 6:6 /* RWXVF */ +#define NV_MMU_VER2_PTE_READ_ONLY_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER2_PTE_READ_ONLY_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER2_PTE_ATOMIC_DISABLE 7:7 /* RWXVF */ +#define NV_MMU_VER2_PTE_ATOMIC_DISABLE_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER2_PTE_ATOMIC_DISABLE_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER2_PTE_ADDRESS_SYS 53:8 /* RWXVF */ +#define NV_MMU_VER2_PTE_ADDRESS_VID (35-3):8 /* RWXVF */ +#define NV_MMU_VER2_PTE_ADDRESS_VID_PEER 35:(36-3) /* RWXVF */ +#define NV_MMU_VER2_PTE_ADDRESS_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_VER2_PTE_ADDRESS_VID_PEER_1 0x00000001 /* RW--V */ +#define NV_MMU_VER2_PTE_ADDRESS_VID_PEER_2 0x00000002 /* RW--V */ +#define NV_MMU_VER2_PTE_ADDRESS_VID_PEER_3 0x00000003 /* RW--V */ +#define NV_MMU_VER2_PTE_ADDRESS_VID_PEER_4 0x00000004 /* RW--V */ +#define NV_MMU_VER2_PTE_ADDRESS_VID_PEER_5 0x00000005 /* RW--V */ +#define NV_MMU_VER2_PTE_ADDRESS_VID_PEER_6 0x00000006 /* RW--V */ +#define NV_MMU_VER2_PTE_ADDRESS_VID_PEER_7 0x00000007 /* RW--V */ +#define NV_MMU_VER2_PTE_COMPTAGLINE (20+35):36 /* RWXVF */ +#define NV_MMU_VER2_PTE_KIND 63:56 /* RWXVF */ +#define NV_MMU_VER2_PTE_ADDRESS_SHIFT 0x0000000c /* */ +#define NV_MMU_VER2_PTE__SIZE 8 +#define NV_MMU_CLIENT /* ----G */ +#define NV_MMU_CLIENT_KIND 2:0 /* RWXVF */ +#define NV_MMU_CLIENT_KIND_Z16 0x1 /* R---V */ +#define NV_MMU_CLIENT_KIND_S8 0x2 /* R---V */ +#define NV_MMU_CLIENT_KIND_S8Z24 0x3 /* R---V */ +#define NV_MMU_CLIENT_KIND_ZF32_X24S8 0x4 /* R---V */ +#define NV_MMU_CLIENT_KIND_Z24S8 0x5 /* R---V */ +#define NV_MMU_CLIENT_KIND_GENERIC_MEMORY 0x6 /* R---V */ +#define NV_MMU_CLIENT_KIND_INVALID 0x7 /* R---V */ +#endif // __tu102_dev_mmu_h__ diff --git a/src/nouveau/headers/nvidia/hwref/volta/gv100/dev_fault.h b/src/nouveau/headers/nvidia/hwref/volta/gv100/dev_fault.h new file mode 100644 index 00000000000..6981215acbd --- /dev/null +++ b/src/nouveau/headers/nvidia/hwref/volta/gv100/dev_fault.h @@ -0,0 +1,263 @@ +/******************************************************************************* + Copyright (c) 2003-2016 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + + +#ifndef __gv100_dev_fault_h__ +#define __gv100_dev_fault_h__ +/* This file is autogenerated. Do not edit */ +#define NV_PFAULT_MMU_ENG_ID_GRAPHICS 64 /* */ +#define NV_PFAULT_MMU_ENG_ID_DISPLAY 1 /* */ +#define NV_PFAULT_MMU_ENG_ID_GSP 2 /* */ +#define NV_PFAULT_MMU_ENG_ID_IFB 8 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR1 4 /* */ +#define NV_PFAULT_MMU_ENG_ID_BAR2 5 /* */ +#define NV_PFAULT_MMU_ENG_ID_SEC 14 /* */ +#define NV_PFAULT_MMU_ENG_ID_PERF 9 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVDEC 10 /* */ +#define NV_PFAULT_MMU_ENG_ID_GRCOPY 15 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE0 15 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE1 16 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE2 17 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE3 18 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE4 19 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE5 20 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE6 21 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE7 22 /* */ +#define NV_PFAULT_MMU_ENG_ID_CE8 23 /* */ +#define NV_PFAULT_MMU_ENG_ID_PWR_PMU 6 /* */ +#define NV_PFAULT_MMU_ENG_ID_PTP 3 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVENC0 11 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVENC1 12 /* */ +#define NV_PFAULT_MMU_ENG_ID_NVENC2 13 /* */ +#define NV_PFAULT_MMU_ENG_ID_PHYSICAL 31 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST0 32 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST1 33 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST2 34 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST3 35 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST4 36 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST5 37 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST6 38 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST7 39 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST8 40 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST9 41 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST10 42 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST11 43 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST12 44 /* */ +#define NV_PFAULT_MMU_ENG_ID_HOST13 45 /* */ +#define NV_PFAULT_FAULT_TYPE 4:0 /* */ +#define NV_PFAULT_FAULT_TYPE_PDE 0x00000000 /* */ +#define NV_PFAULT_FAULT_TYPE_PDE_SIZE 0x00000001 /* */ +#define NV_PFAULT_FAULT_TYPE_PTE 0x00000002 /* */ +#define NV_PFAULT_FAULT_TYPE_VA_LIMIT_VIOLATION 0x00000003 /* */ +#define NV_PFAULT_FAULT_TYPE_UNBOUND_INST_BLOCK 0x00000004 /* */ +#define NV_PFAULT_FAULT_TYPE_PRIV_VIOLATION 0x00000005 /* */ +#define NV_PFAULT_FAULT_TYPE_RO_VIOLATION 0x00000006 /* */ +#define NV_PFAULT_FAULT_TYPE_WO_VIOLATION 0x00000007 /* */ +#define NV_PFAULT_FAULT_TYPE_PITCH_MASK_VIOLATION 0x00000008 /* */ +#define NV_PFAULT_FAULT_TYPE_WORK_CREATION 0x00000009 /* */ +#define NV_PFAULT_FAULT_TYPE_UNSUPPORTED_APERTURE 0x0000000a /* */ +#define NV_PFAULT_FAULT_TYPE_COMPRESSION_FAILURE 0x0000000b /* */ +#define NV_PFAULT_FAULT_TYPE_UNSUPPORTED_KIND 0x0000000c /* */ +#define NV_PFAULT_FAULT_TYPE_REGION_VIOLATION 0x0000000d /* */ +#define NV_PFAULT_FAULT_TYPE_POISONED 0x0000000e /* */ +#define NV_PFAULT_FAULT_TYPE_ATOMIC_VIOLATION 0x0000000f /* */ +#define NV_PFAULT_CLIENT 14:8 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_0 0x00000000 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_1 0x00000001 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_2 0x00000002 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_3 0x00000003 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_4 0x00000004 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_5 0x00000005 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_6 0x00000006 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_7 0x00000007 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_0 0x00000008 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_1 0x00000009 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_2 0x0000000A /* */ +#define NV_PFAULT_CLIENT_GPC_PE_3 0x0000000B /* */ +#define NV_PFAULT_CLIENT_GPC_PE_4 0x0000000C /* */ +#define NV_PFAULT_CLIENT_GPC_PE_5 0x0000000D /* */ +#define NV_PFAULT_CLIENT_GPC_PE_6 0x0000000E /* */ +#define NV_PFAULT_CLIENT_GPC_PE_7 0x0000000F /* */ +#define NV_PFAULT_CLIENT_GPC_RAST 0x00000010 /* */ +#define NV_PFAULT_CLIENT_GPC_GCC 0x00000011 /* */ +#define NV_PFAULT_CLIENT_GPC_GPCCS 0x00000012 /* */ +#define NV_PFAULT_CLIENT_GPC_PROP_0 0x00000013 /* */ +#define NV_PFAULT_CLIENT_GPC_PROP_1 0x00000014 /* */ +#define NV_PFAULT_CLIENT_GPC_PROP_2 0x00000015 /* */ +#define NV_PFAULT_CLIENT_GPC_PROP_3 0x00000016 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_8 0x00000021 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_9 0x00000022 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_10 0x00000023 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_11 0x00000024 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_12 0x00000025 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_13 0x00000026 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_14 0x00000027 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_15 0x00000028 /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_0 0x00000029 /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_1 0x0000002A /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_2 0x0000002B /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_3 0x0000002C /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_4 0x0000002D /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_5 0x0000002E /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_6 0x0000002F /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_7 0x00000030 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_8 0x00000031 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_9 0x00000032 /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_8 0x00000033 /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_9 0x00000034 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_16 0x00000035 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_17 0x00000036 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_18 0x00000037 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_19 0x00000038 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_10 0x00000039 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_11 0x0000003A /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_10 0x0000003B /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_11 0x0000003C /* */ +#define NV_PFAULT_CLIENT_GPC_T1_20 0x0000003D /* */ +#define NV_PFAULT_CLIENT_GPC_T1_21 0x0000003E /* */ +#define NV_PFAULT_CLIENT_GPC_T1_22 0x0000003F /* */ +#define NV_PFAULT_CLIENT_GPC_T1_23 0x00000040 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_12 0x00000041 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_13 0x00000042 /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_12 0x00000043 /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_13 0x00000044 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_24 0x00000045 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_25 0x00000046 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_26 0x00000047 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_27 0x00000048 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_14 0x00000049 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_15 0x0000004A /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_14 0x0000004B /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_15 0x0000004C /* */ +#define NV_PFAULT_CLIENT_GPC_T1_28 0x0000004D /* */ +#define NV_PFAULT_CLIENT_GPC_T1_29 0x0000004E /* */ +#define NV_PFAULT_CLIENT_GPC_T1_30 0x0000004F /* */ +#define NV_PFAULT_CLIENT_GPC_T1_31 0x00000050 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_16 0x00000051 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_17 0x00000052 /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_16 0x00000053 /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_17 0x00000054 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_32 0x00000055 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_33 0x00000056 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_34 0x00000057 /* */ +#define NV_PFAULT_CLIENT_GPC_T1_35 0x00000058 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_18 0x00000059 /* */ +#define NV_PFAULT_CLIENT_GPC_PE_19 0x0000005A /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_18 0x0000005B /* */ +#define NV_PFAULT_CLIENT_GPC_TPCCS_19 0x0000005C /* */ +#define NV_PFAULT_CLIENT_GPC_T1_36 0x0000005D /* */ +#define NV_PFAULT_CLIENT_GPC_T1_37 0x0000005E /* */ +#define NV_PFAULT_CLIENT_GPC_T1_38 0x0000005F /* */ +#define NV_PFAULT_CLIENT_GPC_T1_39 0x00000060 /* */ +#define NV_PFAULT_CLIENT_GPC_GPM 0x00000017 /* */ +#define NV_PFAULT_CLIENT_GPC_LTP_UTLB_0 0x00000018 /* */ +#define NV_PFAULT_CLIENT_GPC_LTP_UTLB_1 0x00000019 /* */ +#define NV_PFAULT_CLIENT_GPC_LTP_UTLB_2 0x0000001A /* */ +#define NV_PFAULT_CLIENT_GPC_LTP_UTLB_3 0x0000001B /* */ +#define NV_PFAULT_CLIENT_GPC_LTP_UTLB_4 0x0000001C /* */ +#define NV_PFAULT_CLIENT_GPC_LTP_UTLB_5 0x0000001D /* */ +#define NV_PFAULT_CLIENT_GPC_LTP_UTLB_6 0x0000001E /* */ +#define NV_PFAULT_CLIENT_GPC_LTP_UTLB_7 0x0000001F /* */ +#define NV_PFAULT_CLIENT_GPC_RGG_UTLB 0x00000020 /* */ +#define NV_PFAULT_CLIENT_HUB_CE0 0x00000001 /* */ +#define NV_PFAULT_CLIENT_HUB_CE1 0x00000002 /* */ +#define NV_PFAULT_CLIENT_HUB_DNISO 0x00000003 /* */ +#define NV_PFAULT_CLIENT_HUB_FE 0x00000004 /* */ +#define NV_PFAULT_CLIENT_HUB_FECS 0x00000005 /* */ +#define NV_PFAULT_CLIENT_HUB_HOST 0x00000006 /* */ +#define NV_PFAULT_CLIENT_HUB_HOST_CPU 0x00000007 /* */ +#define NV_PFAULT_CLIENT_HUB_HOST_CPU_NB 0x00000008 /* */ +#define NV_PFAULT_CLIENT_HUB_ISO 0x00000009 /* */ +#define NV_PFAULT_CLIENT_HUB_MMU 0x0000000A /* */ +#define NV_PFAULT_CLIENT_HUB_NVDEC 0x0000000B /* */ +#define NV_PFAULT_CLIENT_HUB_NVENC1 0x0000000D /* */ +#define NV_PFAULT_CLIENT_HUB_NVENC2 0x00000033 /* */ +#define NV_PFAULT_CLIENT_HUB_NISO 0x0000000E /* */ +#define NV_PFAULT_CLIENT_HUB_P2P 0x0000000F /* */ +#define NV_PFAULT_CLIENT_HUB_PD 0x00000010 /* */ +#define NV_PFAULT_CLIENT_HUB_PERF 0x00000011 /* */ +#define NV_PFAULT_CLIENT_HUB_PMU 0x00000012 /* */ +#define NV_PFAULT_CLIENT_HUB_RASTERTWOD 0x00000013 /* */ +#define NV_PFAULT_CLIENT_HUB_SCC 0x00000014 /* */ +#define NV_PFAULT_CLIENT_HUB_SCC_NB 0x00000015 /* */ +#define NV_PFAULT_CLIENT_HUB_SEC 0x00000016 /* */ +#define NV_PFAULT_CLIENT_HUB_SSYNC 0x00000017 /* */ +#define NV_PFAULT_CLIENT_HUB_VIP 0x00000000 /* */ +#define NV_PFAULT_CLIENT_HUB_GRCOPY 0x00000018 /* */ +#define NV_PFAULT_CLIENT_HUB_CE2 0x00000018 /* */ +#define NV_PFAULT_CLIENT_HUB_XV 0x00000019 /* */ +#define NV_PFAULT_CLIENT_HUB_MMU_NB 0x0000001A /* */ +#define NV_PFAULT_CLIENT_HUB_NVENC 0x0000001B /* */ +#define NV_PFAULT_CLIENT_HUB_NVENC0 0x0000001B /* */ +#define NV_PFAULT_CLIENT_HUB_DFALCON 0x0000001C /* */ +#define NV_PFAULT_CLIENT_HUB_SKED 0x0000001D /* */ +#define NV_PFAULT_CLIENT_HUB_AFALCON 0x0000001E /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE0 0x00000020 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE1 0x00000021 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE2 0x00000022 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE3 0x00000023 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE4 0x00000024 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE5 0x00000025 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE6 0x00000026 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE7 0x00000027 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE8 0x00000028 /* */ +#define NV_PFAULT_CLIENT_HUB_HSCE9 0x00000029 /* */ +#define NV_PFAULT_CLIENT_HUB_HSHUB 0x0000002A /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X0 0x0000002B /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X1 0x0000002C /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X2 0x0000002D /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X3 0x0000002E /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X4 0x0000002F /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X5 0x00000030 /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X6 0x00000031 /* */ +#define NV_PFAULT_CLIENT_HUB_PTP_X7 0x00000032 /* */ +#define NV_PFAULT_CLIENT_HUB_VPR_SCRUBBER0 0x00000034 /* */ +#define NV_PFAULT_CLIENT_HUB_VPR_SCRUBBER1 0x00000035 /* */ +#define NV_PFAULT_CLIENT_HUB_DWBIF 0x00000036 /* */ +#define NV_PFAULT_CLIENT_HUB_FBFALCON 0x00000037 /* */ +#define NV_PFAULT_CLIENT_HUB_CE_SHIM 0x00000038 /* */ +#define NV_PFAULT_CLIENT_HUB_GSP 0x00000039 /* */ +#define NV_PFAULT_CLIENT_HUB_DONT_CARE 0x0000001F /* */ +#define NV_PFAULT_ACCESS_TYPE 19:16 /* */ +#define NV_PFAULT_ACCESS_TYPE_READ 0x00000000 /* */ +#define NV_PFAULT_ACCESS_TYPE_WRITE 0x00000001 /* */ +#define NV_PFAULT_ACCESS_TYPE_ATOMIC 0x00000002 /* */ +#define NV_PFAULT_ACCESS_TYPE_PREFETCH 0x00000003 /* */ +#define NV_PFAULT_ACCESS_TYPE_VIRT_READ 0x00000000 /* */ +#define NV_PFAULT_ACCESS_TYPE_VIRT_WRITE 0x00000001 /* */ +#define NV_PFAULT_ACCESS_TYPE_VIRT_ATOMIC 0x00000002 /* */ +#define NV_PFAULT_ACCESS_TYPE_VIRT_ATOMIC_STRONG 0x00000002 /* */ +#define NV_PFAULT_ACCESS_TYPE_VIRT_PREFETCH 0x00000003 /* */ +#define NV_PFAULT_ACCESS_TYPE_VIRT_ATOMIC_WEAK 0x00000004 /* */ +#define NV_PFAULT_ACCESS_TYPE_PHYS_READ 0x00000008 /* */ +#define NV_PFAULT_ACCESS_TYPE_PHYS_WRITE 0x00000009 /* */ +#define NV_PFAULT_ACCESS_TYPE_PHYS_ATOMIC 0x0000000a /* */ +#define NV_PFAULT_ACCESS_TYPE_PHYS_PREFETCH 0x0000000b /* */ +#define NV_PFAULT_MMU_CLIENT_TYPE 20:20 /* */ +#define NV_PFAULT_MMU_CLIENT_TYPE_GPC 0x00000000 /* */ +#define NV_PFAULT_MMU_CLIENT_TYPE_HUB 0x00000001 /* */ +#define NV_PFAULT_GPC_ID 28:24 /* */ +#define NV_PFAULT_PROTECTED_MODE 29:29 /* */ +#define NV_PFAULT_ATS_FAULT 30:30 /* */ +#define NV_PFAULT_VALID 31:31 /* */ +#endif // __gv100_dev_fault_h__ diff --git a/src/nouveau/headers/nvidia/hwref/volta/gv100/dev_fb.h b/src/nouveau/headers/nvidia/hwref/volta/gv100/dev_fb.h new file mode 100644 index 00000000000..ed1c3bfe25c --- /dev/null +++ b/src/nouveau/headers/nvidia/hwref/volta/gv100/dev_fb.h @@ -0,0 +1,103 @@ +/******************************************************************************* + Copyright (c) 2017 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +// Excerpt of gv100/dev_fb.h + +#ifndef __dev_fb_h__ +#define __dev_fb_h__ + +#define NV_PFB_PRI_MMU_FAULT_BUFFER_LO(i) (0x00100E24+(i)*20) /* RW-4A */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_LO__SIZE_1 2 /* */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_LO_ADDR_MODE 0:0 /* RW-VF */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_LO_ADDR_MODE_VIRTUAL 0x00000000 /* RW--V */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_LO_ADDR_MODE_PHYSICAL 0x00000001 /* RW--V */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_LO_PHYS_APERTURE 2:1 /* RW-VF */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_LO_PHYS_APERTURE_LOCAL 0x00000000 /* RW--V */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_LO_PHYS_APERTURE_SYS_COH 0x00000002 /* RW--V */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_LO_PHYS_APERTURE_SYS_NCOH 0x00000003 /* RW--V */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_LO_PHYS_VOL 3:3 /* RW-VF */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_LO_ADDR 31:12 /* RW-VF */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_HI(i) (0x00100E28+(i)*20) /* RW-4A */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_HI__SIZE_1 2 /* */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_HI_ADDR 31:0 /* RW-VF */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_GET(i) (0x00100E2C+(i)*20) /* RW-4A */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_GET__SIZE_1 2 /* */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_PTR 19:0 /* RWEVF */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_PTR_RESET 0x00000000 /* RWE-V */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_GETPTR_CORRUPTED 30:30 /* RWEVF */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_GETPTR_CORRUPTED_NO 0x00000000 /* RWE-V */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_GETPTR_CORRUPTED_YES 0x00000001 /* RW--V */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_GETPTR_CORRUPTED_CLEAR 0x00000001 /* RW--V */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_OVERFLOW 31:31 /* RWEVF */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_OVERFLOW_NO 0x00000000 /* RWE-V */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_OVERFLOW_YES 0x00000001 /* RW--V */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_GET_OVERFLOW_CLEAR 0x00000001 /* RW--V */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT(i) (0x00100E30+(i)*20) /* R--4A */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT__SIZE_1 2 /* */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_PTR 19:0 /* R-EVF */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_PTR_RESET 0x00000000 /* R-E-V */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_GETPTR_CORRUPTED 30:30 /* R-EVF */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_GETPTR_CORRUPTED_NO 0x00000000 /* R-E-V */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_GETPTR_CORRUPTED_YES 0x00000001 /* R---V */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_OVERFLOW 31:31 /* R-EVF */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_OVERFLOW_NO 0x00000000 /* R-E-V */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_OVERFLOW_YES 0x00000001 /* R---V */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE(i) (0x00100E34+(i)*20) /* RW-4A */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE__SIZE_1 2 /* */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_VAL 19:0 /* RWEVF */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_VAL_RESET 0x00000000 /* RWE-V */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_OVERFLOW_INTR 29:29 /* RWEVF */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_OVERFLOW_INTR_DISABLE 0x00000000 /* RWE-V */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_OVERFLOW_INTR_ENABLE 0x00000001 /* RW--V */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_SET_DEFAULT 30:30 /* RWEVF */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_SET_DEFAULT_NO 0x00000000 /* RWE-V */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_SET_DEFAULT_YES 0x00000001 /* RW--V */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_ENABLE 31:31 /* RWEVF */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_ENABLE_FALSE 0x00000000 /* RWE-V */ +#define NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_ENABLE_TRUE 0x00000001 /* RW--V */ +#define NV_PFB_PRI_MMU_FAULT_ADDR_LO 0x00100E4C /* R--4R */ +#define NV_PFB_PRI_MMU_FAULT_ADDR_LO_PHYS_APERTURE 1:0 /* R-EVF */ +#define NV_PFB_PRI_MMU_FAULT_ADDR_LO_PHYS_APERTURE_LOCAL 0x00000000 /* R-E-V */ +#define NV_PFB_PRI_MMU_FAULT_ADDR_LO_PHYS_APERTURE_PEER 0x00000001 /* R---V */ +#define NV_PFB_PRI_MMU_FAULT_ADDR_LO_PHYS_APERTURE_SYS_COH 0x00000002 /* R---V */ +#define NV_PFB_PRI_MMU_FAULT_ADDR_LO_PHYS_APERTURE_SYS_NCOH 0x00000003 /* R---V */ +#define NV_PFB_PRI_MMU_FAULT_ADDR_LO_ADDR 31:12 /* R-EVF */ +#define NV_PFB_PRI_MMU_FAULT_ADDR_LO_ADDR_RESET 0x00000000 /* R-E-V */ +#define NV_PFB_PRI_MMU_FAULT_ADDR_HI 0x00100E50 /* R--4R */ +#define NV_PFB_PRI_MMU_FAULT_ADDR_HI_ADDR 31:0 /* R-EVF */ +#define NV_PFB_PRI_MMU_FAULT_ADDR_HI_ADDR_RESET 0x00000000 /* R-E-V */ +#define NV_PFB_PRI_MMU_FAULT_INST_LO 0x00100E54 /* R--4R */ +#define NV_PFB_PRI_MMU_FAULT_INST_LO_ENGINE_ID 8:0 /* R-EVF */ +#define NV_PFB_PRI_MMU_FAULT_INST_LO_ENGINE_ID_RESET 0x00000000 /* R-E-V */ +#define NV_PFB_PRI_MMU_FAULT_INST_LO_APERTURE 11:10 /* R-EVF */ +#define NV_PFB_PRI_MMU_FAULT_INST_LO_APERTURE_VID_MEM 0x00000000 /* R---V */ +#define NV_PFB_PRI_MMU_FAULT_INST_LO_APERTURE_SYS_MEM_COHERENT 0x00000002 /* R---V */ +#define NV_PFB_PRI_MMU_FAULT_INST_LO_APERTURE_SYS_MEM_NONCOHERENT 0x00000003 /* R---V */ +#define NV_PFB_PRI_MMU_FAULT_INST_LO_APERTURE_RESET 0x00000000 /* R-E-V */ +#define NV_PFB_PRI_MMU_FAULT_INST_LO_ADDR 31:12 /* R-EVF */ +#define NV_PFB_PRI_MMU_FAULT_INST_LO_ADDR_RESET 0x00000000 /* R-E-V */ +#define NV_PFB_PRI_MMU_FAULT_INST_HI 0x00100E58 /* R--4R */ +#define NV_PFB_PRI_MMU_FAULT_INST_HI_ADDR 31:0 /* R-EVF */ +#define NV_PFB_PRI_MMU_FAULT_INST_HI_ADDR_RESET 0x00000000 /* R-E-V */ + +#endif diff --git a/src/nouveau/headers/nvidia/hwref/volta/gv100/dev_mmu.h b/src/nouveau/headers/nvidia/hwref/volta/gv100/dev_mmu.h new file mode 100644 index 00000000000..6903839575b --- /dev/null +++ b/src/nouveau/headers/nvidia/hwref/volta/gv100/dev_mmu.h @@ -0,0 +1,661 @@ +/******************************************************************************* + Copyright (c) 2003-2016 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + + +#ifndef __gv100_dev_mmu_h__ +#define __gv100_dev_mmu_h__ +/* This file is autogenerated. Do not edit */ +#define NV_MMU_PDE /* ----G */ +#define NV_MMU_PDE_APERTURE_BIG (0*32+1):(0*32+0) /* RWXVF */ +#define NV_MMU_PDE_APERTURE_BIG_INVALID 0x00000000 /* RW--V */ +#define NV_MMU_PDE_APERTURE_BIG_VIDEO_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_PDE_APERTURE_BIG_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_PDE_APERTURE_BIG_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_PDE_SIZE (0*32+3):(0*32+2) /* RWXVF */ +#define NV_MMU_PDE_SIZE_FULL 0x00000000 /* RW--V */ +#define NV_MMU_PDE_SIZE_HALF 0x00000001 /* RW--V */ +#define NV_MMU_PDE_SIZE_QUARTER 0x00000002 /* RW--V */ +#define NV_MMU_PDE_SIZE_EIGHTH 0x00000003 /* RW--V */ +#define NV_MMU_PDE_ADDRESS_BIG_SYS (0*32+31):(0*32+4) /* RWXVF */ +#define NV_MMU_PDE_ADDRESS_BIG_VID (0*32+31-3):(0*32+4) /* RWXVF */ +#define NV_MMU_PDE_ADDRESS_BIG_VID_PEER (0*32+31):(0*32+32-3) /* RWXVF */ +#define NV_MMU_PDE_ADDRESS_BIG_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_PDE_APERTURE_SMALL (1*32+1):(1*32+0) /* RWXVF */ +#define NV_MMU_PDE_APERTURE_SMALL_INVALID 0x00000000 /* RW--V */ +#define NV_MMU_PDE_APERTURE_SMALL_VIDEO_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_PDE_APERTURE_SMALL_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_PDE_APERTURE_SMALL_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_PDE_VOL_SMALL (1*32+2):(1*32+2) /* RWXVF */ +#define NV_MMU_PDE_VOL_SMALL_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_PDE_VOL_SMALL_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_PDE_VOL_BIG (1*32+3):(1*32+3) /* RWXVF */ +#define NV_MMU_PDE_VOL_BIG_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_PDE_VOL_BIG_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_PDE_ADDRESS_SMALL_SYS (1*32+31):(1*32+4) /* RWXVF */ +#define NV_MMU_PDE_ADDRESS_SMALL_VID (1*32+31-3):(1*32+4) /* RWXVF */ +#define NV_MMU_PDE_ADDRESS_SMALL_VID_PEER (1*32+31):(1*32+32-3) /* RWXVF */ +#define NV_MMU_PDE_ADDRESS_SMALL_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_PDE_ADDRESS_SHIFT 0x0000000c /* */ +#define NV_MMU_PDE__SIZE 8 +#define NV_MMU_PTE /* ----G */ +#define NV_MMU_PTE_VALID (0*32+0):(0*32+0) /* RWXVF */ +#define NV_MMU_PTE_VALID_TRUE 0x1 /* RW--V */ +#define NV_MMU_PTE_VALID_FALSE 0x0 /* RW--V */ +#define NV_MMU_PTE_PRIVILEGE (0*32+1):(0*32+1) /* RWXVF */ +#define NV_MMU_PTE_PRIVILEGE_TRUE 0x1 /* RW--V */ +#define NV_MMU_PTE_PRIVILEGE_FALSE 0x0 /* RW--V */ +#define NV_MMU_PTE_READ_ONLY (0*32+2):(0*32+2) /* RWXVF */ +#define NV_MMU_PTE_READ_ONLY_TRUE 0x1 /* RW--V */ +#define NV_MMU_PTE_READ_ONLY_FALSE 0x0 /* RW--V */ +#define NV_MMU_PTE_ENCRYPTED (0*32+3):(0*32+3) /* RWXVF */ +#define NV_MMU_PTE_ENCRYPTED_TRUE 0x00000001 /* R---V */ +#define NV_MMU_PTE_ENCRYPTED_FALSE 0x00000000 /* R---V */ +#define NV_MMU_PTE_ADDRESS_SYS (0*32+31):(0*32+4) /* RWXVF */ +#define NV_MMU_PTE_ADDRESS_VID (0*32+31-3):(0*32+4) /* RWXVF */ +#define NV_MMU_PTE_ADDRESS_VID_PEER (0*32+31):(0*32+32-3) /* RWXVF */ +#define NV_MMU_PTE_ADDRESS_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_PTE_ADDRESS_VID_PEER_1 0x00000001 /* RW--V */ +#define NV_MMU_PTE_ADDRESS_VID_PEER_2 0x00000002 /* RW--V */ +#define NV_MMU_PTE_ADDRESS_VID_PEER_3 0x00000003 /* RW--V */ +#define NV_MMU_PTE_ADDRESS_VID_PEER_4 0x00000004 /* RW--V */ +#define NV_MMU_PTE_ADDRESS_VID_PEER_5 0x00000005 /* RW--V */ +#define NV_MMU_PTE_ADDRESS_VID_PEER_6 0x00000006 /* RW--V */ +#define NV_MMU_PTE_ADDRESS_VID_PEER_7 0x00000007 /* RW--V */ +#define NV_MMU_PTE_VOL (1*32+0):(1*32+0) /* RWXVF */ +#define NV_MMU_PTE_VOL_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_PTE_VOL_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_PTE_APERTURE (1*32+2):(1*32+1) /* RWXVF */ +#define NV_MMU_PTE_APERTURE_VIDEO_MEMORY 0x00000000 /* RW--V */ +#define NV_MMU_PTE_APERTURE_PEER_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_PTE_APERTURE_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_PTE_LOCK (1*32+3):(1*32+3) /* RWXVF */ +#define NV_MMU_PTE_LOCK_TRUE 0x1 /* RW--V */ +#define NV_MMU_PTE_LOCK_FALSE 0x0 /* RW--V */ +#define NV_MMU_PTE_ATOMIC_DISABLE (1*32+3):(1*32+3) /* RWXVF */ +#define NV_MMU_PTE_ATOMIC_DISABLE_TRUE 0x1 /* RW--V */ +#define NV_MMU_PTE_ATOMIC_DISABLE_FALSE 0x0 /* RW--V */ +#define NV_MMU_PTE_COMPTAGLINE (1*32+18+11):(1*32+12) /* RWXVF */ +#define NV_MMU_PTE_READ_DISABLE (1*32+30):(1*32+30) /* RWXVF */ +#define NV_MMU_PTE_READ_DISABLE_TRUE 0x1 /* RW--V */ +#define NV_MMU_PTE_READ_DISABLE_FALSE 0x0 /* RW--V */ +#define NV_MMU_PTE_WRITE_DISABLE (1*32+31):(1*32+31) /* RWXVF */ +#define NV_MMU_PTE_WRITE_DISABLE_TRUE 0x1 /* RW--V */ +#define NV_MMU_PTE_WRITE_DISABLE_FALSE 0x0 /* RW--V */ +#define NV_MMU_PTE_ADDRESS_SHIFT 0x0000000c /* */ +#define NV_MMU_PTE__SIZE 8 +#define NV_MMU_PTE_COMPTAGS_NONE 0x0 /* */ +#define NV_MMU_PTE_COMPTAGS_1 0x1 /* */ +#define NV_MMU_PTE_COMPTAGS_2 0x2 /* */ +#define NV_MMU_PTE_KIND (1*32+11):(1*32+4) /* RWXVF */ +#define NV_MMU_PTE_KIND_INVALID 0xff /* R---V */ +#define NV_MMU_PTE_KIND_PITCH 0x00 /* R---V */ +#define NV_MMU_PTE_KIND_Z16 0x01 /* R---V */ +#define NV_MMU_PTE_KIND_Z16_2C 0x02 /* R---V */ +#define NV_MMU_PTE_KIND_Z16_MS2_2C 0x03 /* R---V */ +#define NV_MMU_PTE_KIND_Z16_MS4_2C 0x04 /* R---V */ +#define NV_MMU_PTE_KIND_Z16_MS8_2C 0x05 /* R---V */ +#define NV_MMU_PTE_KIND_Z16_MS16_2C 0x06 /* R---V */ +#define NV_MMU_PTE_KIND_Z16_2Z 0x07 /* R---V */ +#define NV_MMU_PTE_KIND_Z16_MS2_2Z 0x08 /* R---V */ +#define NV_MMU_PTE_KIND_Z16_MS4_2Z 0x09 /* R---V */ +#define NV_MMU_PTE_KIND_Z16_MS8_2Z 0x0a /* R---V */ +#define NV_MMU_PTE_KIND_Z16_MS16_2Z 0x0b /* R---V */ +#define NV_MMU_PTE_KIND_Z16_2CZ 0x36 /* R---V */ +#define NV_MMU_PTE_KIND_Z16_MS2_2CZ 0x37 /* R---V */ +#define NV_MMU_PTE_KIND_Z16_MS4_2CZ 0x38 /* R---V */ +#define NV_MMU_PTE_KIND_Z16_MS8_2CZ 0x39 /* R---V */ +#define NV_MMU_PTE_KIND_Z16_MS16_2CZ 0x5f /* R---V */ +#define NV_MMU_PTE_KIND_Z16_4CZ 0x0c /* R---V */ +#define NV_MMU_PTE_KIND_Z16_MS2_4CZ 0x0d /* R---V */ +#define NV_MMU_PTE_KIND_Z16_MS4_4CZ 0x0e /* R---V */ +#define NV_MMU_PTE_KIND_Z16_MS8_4CZ 0x0f /* R---V */ +#define NV_MMU_PTE_KIND_Z16_MS16_4CZ 0x10 /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24 0x11 /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_1Z 0x12 /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_MS2_1Z 0x13 /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_MS4_1Z 0x14 /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_MS8_1Z 0x15 /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_MS16_1Z 0x16 /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_2CZ 0x17 /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_MS2_2CZ 0x18 /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_MS4_2CZ 0x19 /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_MS8_2CZ 0x1a /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_MS16_2CZ 0x1b /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_2CS 0x1c /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_MS2_2CS 0x1d /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_MS4_2CS 0x1e /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_MS8_2CS 0x1f /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_MS16_2CS 0x20 /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_4CSZV 0x21 /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_MS2_4CSZV 0x22 /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_MS4_4CSZV 0x23 /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_MS8_4CSZV 0x24 /* R---V */ +#define NV_MMU_PTE_KIND_S8Z24_MS16_4CSZV 0x25 /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12 0x26 /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4 0x27 /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8 0x28 /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24 0x29 /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_1ZV 0x2e /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_1ZV 0x2f /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_1ZV 0x30 /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_1ZV 0x31 /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2CS 0x32 /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2CS 0x33 /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2CS 0x34 /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2CS 0x35 /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2CZV 0x3a /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2CZV 0x3b /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2CZV 0x3c /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2CZV 0x3d /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2ZV 0x3e /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2ZV 0x3f /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2ZV 0x40 /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2ZV 0x41 /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_4CSZV 0x42 /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_4CSZV 0x43 /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_4CSZV 0x44 /* R---V */ +#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_4CSZV 0x45 /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8 0x46 /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_1Z 0x47 /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_MS2_1Z 0x48 /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_MS4_1Z 0x49 /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_MS8_1Z 0x4a /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_MS16_1Z 0x4b /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_2CS 0x4c /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_MS2_2CS 0x4d /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_MS4_2CS 0x4e /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_MS8_2CS 0x4f /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_MS16_2CS 0x50 /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_2CZ 0x51 /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_MS2_2CZ 0x52 /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_MS4_2CZ 0x53 /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_MS8_2CZ 0x54 /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_MS16_2CZ 0x55 /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_4CSZV 0x56 /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_MS2_4CSZV 0x57 /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_MS4_4CSZV 0x58 /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_MS8_4CSZV 0x59 /* R---V */ +#define NV_MMU_PTE_KIND_Z24S8_MS16_4CSZV 0x5a /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12 0x5b /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4 0x5c /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8 0x5d /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24 0x5e /* R---V */ +#define NV_MMU_PTE_KIND_YUV_B8C1_2Y 0x60 /* R---V */ +#define NV_MMU_PTE_KIND_YUV_B8C2_2Y 0x61 /* R---V */ +#define NV_MMU_PTE_KIND_YUV_B10C1_2Y 0x62 /* R---V */ +#define NV_MMU_PTE_KIND_YUV_B10C2_2Y 0x6b /* R---V */ +#define NV_MMU_PTE_KIND_YUV_B12C1_2Y 0x6c /* R---V */ +#define NV_MMU_PTE_KIND_YUV_B12C2_2Y 0x6d /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_1ZV 0x63 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_1ZV 0x64 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_1ZV 0x65 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_1ZV 0x66 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2CS 0x67 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2CS 0x68 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2CS 0x69 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2CS 0x6a /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2CZV 0x6f /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2CZV 0x70 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2CZV 0x71 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2CZV 0x72 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2ZV 0x73 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2ZV 0x74 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2ZV 0x75 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2ZV 0x76 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_4CSZV 0x77 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_4CSZV 0x78 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_4CSZV 0x79 /* R---V */ +#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_4CSZV 0x7a /* R---V */ +#define NV_MMU_PTE_KIND_ZF32 0x7b /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_1Z 0x7c /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_MS2_1Z 0x7d /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_MS4_1Z 0x7e /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_MS8_1Z 0x7f /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_MS16_1Z 0x80 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_2CS 0x81 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_MS2_2CS 0x82 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_MS4_2CS 0x83 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_MS8_2CS 0x84 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_MS16_2CS 0x85 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_2CZ 0x86 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_MS2_2CZ 0x87 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_MS4_2CZ 0x88 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_MS8_2CZ 0x89 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_MS16_2CZ 0x8a /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12 0x8b /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4 0x8c /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8 0x8d /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24 0x8e /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1CS 0x8f /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1CS 0x90 /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1CS 0x91 /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1CS 0x92 /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1ZV 0x97 /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1ZV 0x98 /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1ZV 0x99 /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1ZV 0x9a /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1CZV 0x9b /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1CZV 0x9c /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1CZV 0x9d /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1CZV 0x9e /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_2CS 0x9f /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_2CS 0xa0 /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_2CS 0xa1 /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_2CS 0xa2 /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_2CSZV 0xa3 /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_2CSZV 0xa4 /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_2CSZV 0xa5 /* R---V */ +#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_2CSZV 0xa6 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12 0xa7 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4 0xa8 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8 0xa9 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24 0xaa /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1CS 0xab /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1CS 0xac /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1CS 0xad /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1CS 0xae /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1ZV 0xb3 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1ZV 0xb4 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1ZV 0xb5 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1ZV 0xb6 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1CZV 0xb7 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1CZV 0xb8 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1CZV 0xb9 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1CZV 0xba /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_2CS 0xbb /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_2CS 0xbc /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_2CS 0xbd /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_2CS 0xbe /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_2CSZV 0xbf /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_2CSZV 0xc0 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_2CSZV 0xc1 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_2CSZV 0xc2 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8 0xc3 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8_1CS 0xc4 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_1CS 0xc5 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_1CS 0xc6 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_1CS 0xc7 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_1CS 0xc8 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8_2CSZV 0xce /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_2CSZV 0xcf /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_2CSZV 0xd0 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_2CSZV 0xd1 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_2CSZV 0xd2 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8_2CS 0xd3 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_2CS 0xd4 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_2CS 0xd5 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_2CS 0xd6 /* R---V */ +#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_2CS 0xd7 /* R---V */ +#define NV_MMU_PTE_KIND_S8 0x2a /* R---V */ +#define NV_MMU_PTE_KIND_S8_2S 0x2b /* R---V */ +#define NV_MMU_PTE_KIND_GENERIC_16BX2 0xfe /* R---V */ +#define NV_MMU_PTE_KIND_C32_2C 0xd8 /* R---V */ +#define NV_MMU_PTE_KIND_C32_2CBR 0xd9 /* R---V */ +#define NV_MMU_PTE_KIND_C32_2CBA 0xda /* R---V */ +#define NV_MMU_PTE_KIND_C32_2CRA 0xdb /* R---V */ +#define NV_MMU_PTE_KIND_C32_2BRA 0xdc /* R---V */ +#define NV_MMU_PTE_KIND_C32_MS2_2C 0xdd /* R---V */ +#define NV_MMU_PTE_KIND_C32_MS2_2CBR 0xde /* R---V */ +#define NV_MMU_PTE_KIND_C32_MS2_4CBRA 0xcc /* R---V */ +#define NV_MMU_PTE_KIND_C32_MS4_2C 0xdf /* R---V */ +#define NV_MMU_PTE_KIND_C32_MS4_2CBR 0xe0 /* R---V */ +#define NV_MMU_PTE_KIND_C32_MS4_2CBA 0xe1 /* R---V */ +#define NV_MMU_PTE_KIND_C32_MS4_2CRA 0xe2 /* R---V */ +#define NV_MMU_PTE_KIND_C32_MS4_2BRA 0xe3 /* R---V */ +#define NV_MMU_PTE_KIND_C32_MS4_4CBRA 0x2c /* R---V */ +#define NV_MMU_PTE_KIND_C32_MS8_MS16_2C 0xe4 /* R---V */ +#define NV_MMU_PTE_KIND_C32_MS8_MS16_2CRA 0xe5 /* R---V */ +#define NV_MMU_PTE_KIND_C64_2C 0xe6 /* R---V */ +#define NV_MMU_PTE_KIND_C64_2CBR 0xe7 /* R---V */ +#define NV_MMU_PTE_KIND_C64_2CBA 0xe8 /* R---V */ +#define NV_MMU_PTE_KIND_C64_2CRA 0xe9 /* R---V */ +#define NV_MMU_PTE_KIND_C64_2BRA 0xea /* R---V */ +#define NV_MMU_PTE_KIND_C64_MS2_2C 0xeb /* R---V */ +#define NV_MMU_PTE_KIND_C64_MS2_2CBR 0xec /* R---V */ +#define NV_MMU_PTE_KIND_C64_MS2_4CBRA 0xcd /* R---V */ +#define NV_MMU_PTE_KIND_C64_MS4_2C 0xed /* R---V */ +#define NV_MMU_PTE_KIND_C64_MS4_2CBR 0xee /* R---V */ +#define NV_MMU_PTE_KIND_C64_MS4_2CBA 0xef /* R---V */ +#define NV_MMU_PTE_KIND_C64_MS4_2CRA 0xf0 /* R---V */ +#define NV_MMU_PTE_KIND_C64_MS4_2BRA 0xf1 /* R---V */ +#define NV_MMU_PTE_KIND_C64_MS4_4CBRA 0x2d /* R---V */ +#define NV_MMU_PTE_KIND_C64_MS8_MS16_2C 0xf2 /* R---V */ +#define NV_MMU_PTE_KIND_C64_MS8_MS16_2CRA 0xf3 /* R---V */ +#define NV_MMU_PTE_KIND_C128_2C 0xf4 /* R---V */ +#define NV_MMU_PTE_KIND_C128_2CR 0xf5 /* R---V */ +#define NV_MMU_PTE_KIND_C128_MS2_2C 0xf6 /* R---V */ +#define NV_MMU_PTE_KIND_C128_MS2_2CR 0xf7 /* R---V */ +#define NV_MMU_PTE_KIND_C128_MS4_2C 0xf8 /* R---V */ +#define NV_MMU_PTE_KIND_C128_MS4_2CR 0xf9 /* R---V */ +#define NV_MMU_PTE_KIND_C128_MS8_MS16_2C 0xfa /* R---V */ +#define NV_MMU_PTE_KIND_C128_MS8_MS16_2CR 0xfb /* R---V */ +#define NV_MMU_PTE_KIND_X8C24 0xfc /* R---V */ +#define NV_MMU_PTE_KIND_PITCH_NO_SWIZZLE 0xfd /* R---V */ +#define NV_MMU_PTE_KIND_SMSKED_MESSAGE 0xca /* R---V */ +#define NV_MMU_PTE_KIND_SMHOST_MESSAGE 0xcb /* R---V */ +#define NV_MMU_VER1_PDE /* ----G */ +#define NV_MMU_VER1_PDE_APERTURE_BIG (0*32+1):(0*32+0) /* RWXVF */ +#define NV_MMU_VER1_PDE_APERTURE_BIG_INVALID 0x00000000 /* RW--V */ +#define NV_MMU_VER1_PDE_APERTURE_BIG_VIDEO_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_VER1_PDE_APERTURE_BIG_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_VER1_PDE_APERTURE_BIG_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_VER1_PDE_SIZE (0*32+3):(0*32+2) /* RWXVF */ +#define NV_MMU_VER1_PDE_SIZE_FULL 0x00000000 /* RW--V */ +#define NV_MMU_VER1_PDE_SIZE_HALF 0x00000001 /* RW--V */ +#define NV_MMU_VER1_PDE_SIZE_QUARTER 0x00000002 /* RW--V */ +#define NV_MMU_VER1_PDE_SIZE_EIGHTH 0x00000003 /* RW--V */ +#define NV_MMU_VER1_PDE_ADDRESS_BIG_SYS (0*32+31):(0*32+4) /* RWXVF */ +#define NV_MMU_VER1_PDE_ADDRESS_BIG_VID (0*32+31-3):(0*32+4) /* RWXVF */ +#define NV_MMU_VER1_PDE_ADDRESS_BIG_VID_PEER (0*32+31):(0*32+32-3) /* RWXVF */ +#define NV_MMU_VER1_PDE_ADDRESS_BIG_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_VER1_PDE_APERTURE_SMALL (1*32+1):(1*32+0) /* RWXVF */ +#define NV_MMU_VER1_PDE_APERTURE_SMALL_INVALID 0x00000000 /* RW--V */ +#define NV_MMU_VER1_PDE_APERTURE_SMALL_VIDEO_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_VER1_PDE_APERTURE_SMALL_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_VER1_PDE_APERTURE_SMALL_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_VER1_PDE_VOL_SMALL (1*32+2):(1*32+2) /* RWXVF */ +#define NV_MMU_VER1_PDE_VOL_SMALL_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_VER1_PDE_VOL_SMALL_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_VER1_PDE_VOL_BIG (1*32+3):(1*32+3) /* RWXVF */ +#define NV_MMU_VER1_PDE_VOL_BIG_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_VER1_PDE_VOL_BIG_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_VER1_PDE_ADDRESS_SMALL_SYS (1*32+31):(1*32+4) /* RWXVF */ +#define NV_MMU_VER1_PDE_ADDRESS_SMALL_VID (1*32+31-3):(1*32+4) /* RWXVF */ +#define NV_MMU_VER1_PDE_ADDRESS_SMALL_VID_PEER (1*32+31):(1*32+32-3) /* RWXVF */ +#define NV_MMU_VER1_PDE_ADDRESS_SMALL_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_VER1_PDE_ADDRESS_SHIFT 0x0000000c /* */ +#define NV_MMU_VER1_PDE__SIZE 8 +#define NV_MMU_VER1_PTE /* ----G */ +#define NV_MMU_VER1_PTE_VALID (0*32+0):(0*32+0) /* RWXVF */ +#define NV_MMU_VER1_PTE_VALID_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER1_PTE_VALID_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER1_PTE_PRIVILEGE (0*32+1):(0*32+1) /* RWXVF */ +#define NV_MMU_VER1_PTE_PRIVILEGE_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER1_PTE_PRIVILEGE_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER1_PTE_READ_ONLY (0*32+2):(0*32+2) /* RWXVF */ +#define NV_MMU_VER1_PTE_READ_ONLY_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER1_PTE_READ_ONLY_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER1_PTE_ENCRYPTED (0*32+3):(0*32+3) /* RWXVF */ +#define NV_MMU_VER1_PTE_ENCRYPTED_TRUE 0x00000001 /* R---V */ +#define NV_MMU_VER1_PTE_ENCRYPTED_FALSE 0x00000000 /* R---V */ +#define NV_MMU_VER1_PTE_ADDRESS_SYS (0*32+31):(0*32+4) /* RWXVF */ +#define NV_MMU_VER1_PTE_ADDRESS_VID (0*32+31-3):(0*32+4) /* RWXVF */ +#define NV_MMU_VER1_PTE_ADDRESS_VID_PEER (0*32+31):(0*32+32-3) /* RWXVF */ +#define NV_MMU_VER1_PTE_ADDRESS_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_VER1_PTE_ADDRESS_VID_PEER_1 0x00000001 /* RW--V */ +#define NV_MMU_VER1_PTE_ADDRESS_VID_PEER_2 0x00000002 /* RW--V */ +#define NV_MMU_VER1_PTE_ADDRESS_VID_PEER_3 0x00000003 /* RW--V */ +#define NV_MMU_VER1_PTE_ADDRESS_VID_PEER_4 0x00000004 /* RW--V */ +#define NV_MMU_VER1_PTE_ADDRESS_VID_PEER_5 0x00000005 /* RW--V */ +#define NV_MMU_VER1_PTE_ADDRESS_VID_PEER_6 0x00000006 /* RW--V */ +#define NV_MMU_VER1_PTE_ADDRESS_VID_PEER_7 0x00000007 /* RW--V */ +#define NV_MMU_VER1_PTE_VOL (1*32+0):(1*32+0) /* RWXVF */ +#define NV_MMU_VER1_PTE_VOL_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_VER1_PTE_VOL_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_VER1_PTE_APERTURE (1*32+2):(1*32+1) /* RWXVF */ +#define NV_MMU_VER1_PTE_APERTURE_VIDEO_MEMORY 0x00000000 /* RW--V */ +#define NV_MMU_VER1_PTE_APERTURE_PEER_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_VER1_PTE_APERTURE_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_VER1_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_VER1_PTE_ATOMIC_DISABLE (1*32+3):(1*32+3) /* RWXVF */ +#define NV_MMU_VER1_PTE_ATOMIC_DISABLE_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER1_PTE_ATOMIC_DISABLE_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER1_PTE_COMPTAGLINE (1*32+18+11):(1*32+12) /* RWXVF */ +#define NV_MMU_VER1_PTE_KIND (1*32+11):(1*32+4) /* RWXVF */ +#define NV_MMU_VER1_PTE_ADDRESS_SHIFT 0x0000000c /* */ +#define NV_MMU_VER1_PTE__SIZE 8 +#define NV_MMU_VER1_PTE_COMPTAGS_NONE 0x0 /* */ +#define NV_MMU_VER1_PTE_COMPTAGS_1 0x1 /* */ +#define NV_MMU_VER1_PTE_COMPTAGS_2 0x2 /* */ +#define NV_MMU_NEW_PDE /* ----G */ +#define NV_MMU_NEW_PDE_IS_PTE 0:0 /* RWXVF */ +#define NV_MMU_NEW_PDE_IS_PTE_TRUE 0x1 /* RW--V */ +#define NV_MMU_NEW_PDE_IS_PTE_FALSE 0x0 /* RW--V */ +#define NV_MMU_NEW_PDE_IS_PDE 0:0 /* RWXVF */ +#define NV_MMU_NEW_PDE_IS_PDE_TRUE 0x0 /* RW--V */ +#define NV_MMU_NEW_PDE_IS_PDE_FALSE 0x1 /* RW--V */ +#define NV_MMU_NEW_PDE_VALID 0:0 /* RWXVF */ +#define NV_MMU_NEW_PDE_VALID_TRUE 0x1 /* RW--V */ +#define NV_MMU_NEW_PDE_VALID_FALSE 0x0 /* RW--V */ +#define NV_MMU_NEW_PDE_APERTURE 2:1 /* RWXVF */ +#define NV_MMU_NEW_PDE_APERTURE_INVALID 0x00000000 /* RW--V */ +#define NV_MMU_NEW_PDE_APERTURE_VIDEO_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_NEW_PDE_APERTURE_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_NEW_PDE_APERTURE_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_NEW_PDE_VOL 3:3 /* RWXVF */ +#define NV_MMU_NEW_PDE_VOL_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_NEW_PDE_VOL_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_NEW_PDE_NO_ATS 5:5 /* RWXVF */ +#define NV_MMU_NEW_PDE_NO_ATS_TRUE 0x1 /* RW--V */ +#define NV_MMU_NEW_PDE_NO_ATS_FALSE 0x0 /* RW--V */ +#define NV_MMU_NEW_PDE_ADDRESS_SYS 53:8 /* RWXVF */ +#define NV_MMU_NEW_PDE_ADDRESS_VID (35-3):8 /* RWXVF */ +#define NV_MMU_NEW_PDE_ADDRESS_VID_PEER 35:(36-3) /* RWXVF */ +#define NV_MMU_NEW_PDE_ADDRESS_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_NEW_PDE_ADDRESS_SHIFT 0x0000000c /* */ +#define NV_MMU_NEW_PDE__SIZE 8 +#define NV_MMU_NEW_DUAL_PDE /* ----G */ +#define NV_MMU_NEW_DUAL_PDE_IS_PTE 0:0 /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_IS_PTE_TRUE 0x1 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_IS_PTE_FALSE 0x0 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_IS_PDE 0:0 /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_IS_PDE_TRUE 0x0 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_IS_PDE_FALSE 0x1 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_VALID 0:0 /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_VALID_TRUE 0x1 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_VALID_FALSE 0x0 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_APERTURE_BIG 2:1 /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_APERTURE_BIG_INVALID 0x00000000 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_APERTURE_BIG_VIDEO_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_APERTURE_BIG_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_APERTURE_BIG_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_VOL_BIG 3:3 /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_VOL_BIG_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_VOL_BIG_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_NO_ATS 5:5 /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_NO_ATS_TRUE 0x1 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_NO_ATS_FALSE 0x0 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_ADDRESS_BIG_SYS 53:(8-4) /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_ADDRESS_BIG_VID (35-3):(8-4) /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_ADDRESS_BIG_VID_PEER 35:(36-3) /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_ADDRESS_BIG_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_APERTURE_SMALL 66:65 /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_APERTURE_SMALL_INVALID 0x00000000 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_APERTURE_SMALL_VIDEO_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_APERTURE_SMALL_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_APERTURE_SMALL_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_VOL_SMALL 67:67 /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_VOL_SMALL_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_VOL_SMALL_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_ADDRESS_SMALL_SYS 117:72 /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_ADDRESS_SMALL_VID (99-3):72 /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_ADDRESS_SMALL_VID_PEER 99:(100-3) /* RWXVF */ +#define NV_MMU_NEW_DUAL_PDE_ADDRESS_SMALL_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_NEW_DUAL_PDE_ADDRESS_SHIFT 0x0000000c /* */ +#define NV_MMU_NEW_DUAL_PDE_ADDRESS_BIG_SHIFT 8 /* */ +#define NV_MMU_NEW_DUAL_PDE__SIZE 16 +#define NV_MMU_NEW_PTE /* ----G */ +#define NV_MMU_NEW_PTE_VALID 0:0 /* RWXVF */ +#define NV_MMU_NEW_PTE_VALID_TRUE 0x1 /* RW--V */ +#define NV_MMU_NEW_PTE_VALID_FALSE 0x0 /* RW--V */ +#define NV_MMU_NEW_PTE_APERTURE 2:1 /* RWXVF */ +#define NV_MMU_NEW_PTE_APERTURE_VIDEO_MEMORY 0x00000000 /* RW--V */ +#define NV_MMU_NEW_PTE_APERTURE_PEER_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_NEW_PTE_APERTURE_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_NEW_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_NEW_PTE_VOL 3:3 /* RWXVF */ +#define NV_MMU_NEW_PTE_VOL_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_NEW_PTE_VOL_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_NEW_PTE_ENCRYPTED 4:4 /* RWXVF */ +#define NV_MMU_NEW_PTE_ENCRYPTED_TRUE 0x00000001 /* R---V */ +#define NV_MMU_NEW_PTE_ENCRYPTED_FALSE 0x00000000 /* R---V */ +#define NV_MMU_NEW_PTE_PRIVILEGE 5:5 /* RWXVF */ +#define NV_MMU_NEW_PTE_PRIVILEGE_TRUE 0x1 /* RW--V */ +#define NV_MMU_NEW_PTE_PRIVILEGE_FALSE 0x0 /* RW--V */ +#define NV_MMU_NEW_PTE_READ_ONLY 6:6 /* RWXVF */ +#define NV_MMU_NEW_PTE_READ_ONLY_TRUE 0x1 /* RW--V */ +#define NV_MMU_NEW_PTE_READ_ONLY_FALSE 0x0 /* RW--V */ +#define NV_MMU_NEW_PTE_ATOMIC_DISABLE 7:7 /* RWXVF */ +#define NV_MMU_NEW_PTE_ATOMIC_DISABLE_TRUE 0x1 /* RW--V */ +#define NV_MMU_NEW_PTE_ATOMIC_DISABLE_FALSE 0x0 /* RW--V */ +#define NV_MMU_NEW_PTE_ADDRESS_SYS 53:8 /* RWXVF */ +#define NV_MMU_NEW_PTE_ADDRESS_VID (35-3):8 /* RWXVF */ +#define NV_MMU_NEW_PTE_ADDRESS_VID_PEER 35:(36-3) /* RWXVF */ +#define NV_MMU_NEW_PTE_ADDRESS_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_NEW_PTE_ADDRESS_VID_PEER_1 0x00000001 /* RW--V */ +#define NV_MMU_NEW_PTE_ADDRESS_VID_PEER_2 0x00000002 /* RW--V */ +#define NV_MMU_NEW_PTE_ADDRESS_VID_PEER_3 0x00000003 /* RW--V */ +#define NV_MMU_NEW_PTE_ADDRESS_VID_PEER_4 0x00000004 /* RW--V */ +#define NV_MMU_NEW_PTE_ADDRESS_VID_PEER_5 0x00000005 /* RW--V */ +#define NV_MMU_NEW_PTE_ADDRESS_VID_PEER_6 0x00000006 /* RW--V */ +#define NV_MMU_NEW_PTE_ADDRESS_VID_PEER_7 0x00000007 /* RW--V */ +#define NV_MMU_NEW_PTE_COMPTAGLINE (18+35):36 /* RWXVF */ +#define NV_MMU_NEW_PTE_KIND 63:56 /* RWXVF */ +#define NV_MMU_NEW_PTE_ADDRESS_SHIFT 0x0000000c /* */ +#define NV_MMU_NEW_PTE__SIZE 8 +#define NV_MMU_VER2_PDE /* ----G */ +#define NV_MMU_VER2_PDE_IS_PTE 0:0 /* RWXVF */ +#define NV_MMU_VER2_PDE_IS_PTE_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER2_PDE_IS_PTE_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER2_PDE_IS_PDE 0:0 /* RWXVF */ +#define NV_MMU_VER2_PDE_IS_PDE_TRUE 0x0 /* RW--V */ +#define NV_MMU_VER2_PDE_IS_PDE_FALSE 0x1 /* RW--V */ +#define NV_MMU_VER2_PDE_VALID 0:0 /* RWXVF */ +#define NV_MMU_VER2_PDE_VALID_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER2_PDE_VALID_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER2_PDE_APERTURE 2:1 /* RWXVF */ +#define NV_MMU_VER2_PDE_APERTURE_INVALID 0x00000000 /* RW--V */ +#define NV_MMU_VER2_PDE_APERTURE_VIDEO_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_VER2_PDE_APERTURE_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_VER2_PDE_APERTURE_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_VER2_PDE_VOL 3:3 /* RWXVF */ +#define NV_MMU_VER2_PDE_VOL_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_VER2_PDE_VOL_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_VER2_PDE_NO_ATS 5:5 /* RWXVF */ +#define NV_MMU_VER2_PDE_NO_ATS_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER2_PDE_NO_ATS_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER2_PDE_ADDRESS_SYS 53:8 /* RWXVF */ +#define NV_MMU_VER2_PDE_ADDRESS_VID (35-3):8 /* RWXVF */ +#define NV_MMU_VER2_PDE_ADDRESS_VID_PEER 35:(36-3) /* RWXVF */ +#define NV_MMU_VER2_PDE_ADDRESS_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_VER2_PDE_ADDRESS_SHIFT 0x0000000c /* */ +#define NV_MMU_VER2_PDE__SIZE 8 +#define NV_MMU_VER2_DUAL_PDE /* ----G */ +#define NV_MMU_VER2_DUAL_PDE_IS_PTE 0:0 /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_IS_PTE_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_IS_PTE_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_IS_PDE 0:0 /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_IS_PDE_TRUE 0x0 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_IS_PDE_FALSE 0x1 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_VALID 0:0 /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_VALID_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_VALID_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_APERTURE_BIG 2:1 /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_APERTURE_BIG_INVALID 0x00000000 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_APERTURE_BIG_VIDEO_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_APERTURE_BIG_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_APERTURE_BIG_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_VOL_BIG 3:3 /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_VOL_BIG_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_VOL_BIG_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_NO_ATS 5:5 /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_NO_ATS_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_NO_ATS_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_ADDRESS_BIG_SYS 53:(8-4) /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_ADDRESS_BIG_VID (35-3):(8-4) /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_ADDRESS_BIG_VID_PEER 35:(36-3) /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_ADDRESS_BIG_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_APERTURE_SMALL 66:65 /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_APERTURE_SMALL_INVALID 0x00000000 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_APERTURE_SMALL_VIDEO_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_APERTURE_SMALL_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_APERTURE_SMALL_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_VOL_SMALL 67:67 /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_VOL_SMALL_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_VOL_SMALL_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_ADDRESS_SMALL_SYS 117:72 /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_ADDRESS_SMALL_VID (99-3):72 /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_ADDRESS_SMALL_VID_PEER 99:(100-3) /* RWXVF */ +#define NV_MMU_VER2_DUAL_PDE_ADDRESS_SMALL_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_VER2_DUAL_PDE_ADDRESS_SHIFT 0x0000000c /* */ +#define NV_MMU_VER2_DUAL_PDE_ADDRESS_BIG_SHIFT 8 /* */ +#define NV_MMU_VER2_DUAL_PDE__SIZE 16 +#define NV_MMU_VER2_PTE /* ----G */ +#define NV_MMU_VER2_PTE_VALID 0:0 /* RWXVF */ +#define NV_MMU_VER2_PTE_VALID_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER2_PTE_VALID_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER2_PTE_APERTURE 2:1 /* RWXVF */ +#define NV_MMU_VER2_PTE_APERTURE_VIDEO_MEMORY 0x00000000 /* RW--V */ +#define NV_MMU_VER2_PTE_APERTURE_PEER_MEMORY 0x00000001 /* RW--V */ +#define NV_MMU_VER2_PTE_APERTURE_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */ +#define NV_MMU_VER2_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */ +#define NV_MMU_VER2_PTE_VOL 3:3 /* RWXVF */ +#define NV_MMU_VER2_PTE_VOL_TRUE 0x00000001 /* RW--V */ +#define NV_MMU_VER2_PTE_VOL_FALSE 0x00000000 /* RW--V */ +#define NV_MMU_VER2_PTE_ENCRYPTED 4:4 /* RWXVF */ +#define NV_MMU_VER2_PTE_ENCRYPTED_TRUE 0x00000001 /* R---V */ +#define NV_MMU_VER2_PTE_ENCRYPTED_FALSE 0x00000000 /* R---V */ +#define NV_MMU_VER2_PTE_PRIVILEGE 5:5 /* RWXVF */ +#define NV_MMU_VER2_PTE_PRIVILEGE_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER2_PTE_PRIVILEGE_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER2_PTE_READ_ONLY 6:6 /* RWXVF */ +#define NV_MMU_VER2_PTE_READ_ONLY_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER2_PTE_READ_ONLY_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER2_PTE_ATOMIC_DISABLE 7:7 /* RWXVF */ +#define NV_MMU_VER2_PTE_ATOMIC_DISABLE_TRUE 0x1 /* RW--V */ +#define NV_MMU_VER2_PTE_ATOMIC_DISABLE_FALSE 0x0 /* RW--V */ +#define NV_MMU_VER2_PTE_ADDRESS_SYS 53:8 /* RWXVF */ +#define NV_MMU_VER2_PTE_ADDRESS_VID (35-3):8 /* RWXVF */ +#define NV_MMU_VER2_PTE_ADDRESS_VID_PEER 35:(36-3) /* RWXVF */ +#define NV_MMU_VER2_PTE_ADDRESS_VID_PEER_0 0x00000000 /* RW--V */ +#define NV_MMU_VER2_PTE_ADDRESS_VID_PEER_1 0x00000001 /* RW--V */ +#define NV_MMU_VER2_PTE_ADDRESS_VID_PEER_2 0x00000002 /* RW--V */ +#define NV_MMU_VER2_PTE_ADDRESS_VID_PEER_3 0x00000003 /* RW--V */ +#define NV_MMU_VER2_PTE_ADDRESS_VID_PEER_4 0x00000004 /* RW--V */ +#define NV_MMU_VER2_PTE_ADDRESS_VID_PEER_5 0x00000005 /* RW--V */ +#define NV_MMU_VER2_PTE_ADDRESS_VID_PEER_6 0x00000006 /* RW--V */ +#define NV_MMU_VER2_PTE_ADDRESS_VID_PEER_7 0x00000007 /* RW--V */ +#define NV_MMU_VER2_PTE_COMPTAGLINE (18+35):36 /* RWXVF */ +#define NV_MMU_VER2_PTE_KIND 63:56 /* RWXVF */ +#define NV_MMU_VER2_PTE_ADDRESS_SHIFT 0x0000000c /* */ +#define NV_MMU_VER2_PTE__SIZE 8 +#define NV_MMU_BASIC /* ----G */ +#define NV_MMU_BASIC_KIND 3:0 /* RWXVF */ +#define NV_MMU_BASIC_KIND_TRANSPARENT 0x0 /* R---V */ +#define NV_MMU_BASIC_KIND_GENERIC 0x1 /* R---V */ +#define NV_MMU_BASIC_KIND_S8 0x2 /* R---V */ +#define NV_MMU_BASIC_KIND_Z16 0x3 /* R---V */ +#define NV_MMU_BASIC_KIND_Z24S8 0x4 /* R---V */ +#define NV_MMU_BASIC_KIND_ZF32 0x5 /* R---V */ +#define NV_MMU_BASIC_KIND_ZF32_X24S8 0x6 /* R---V */ +#define NV_MMU_BASIC_KIND_RSVRD0 0x7 /* R---V */ +#define NV_MMU_BASIC_KIND_PITCH 0x8 /* R---V */ +#define NV_MMU_BASIC_KIND_GENERIC_C 0x9 /* R---V */ +#define NV_MMU_BASIC_KIND_S8_C 0xa /* R---V */ +#define NV_MMU_BASIC_KIND_Z16_C 0xb /* R---V */ +#define NV_MMU_BASIC_KIND_Z24S8_C 0xc /* R---V */ +#define NV_MMU_BASIC_KIND_ZF32_C 0xd /* R---V */ +#define NV_MMU_BASIC_KIND_ZF32_X24S8_C 0xe /* R---V */ +#define NV_MMU_BASIC_KIND_INVALID 0xf /* R---V */ +#endif // __gv100_dev_mmu_h__