From 39db5a569b9213c84bf8b3e7f092a8d3a19e5b2b Mon Sep 17 00:00:00 2001 From: Rhys Perry Date: Fri, 30 Jul 2021 13:25:26 +0100 Subject: [PATCH] radv: set image_dim and image_array intrinsic indices Signed-off-by: Rhys Perry Reviewed-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/radv_meta_bufimage.c | 15 ++++++++------- src/amd/vulkan/radv_meta_dcc_retile.c | 2 ++ src/amd/vulkan/radv_meta_fast_clear.c | 9 +++++---- src/amd/vulkan/radv_meta_fmask_expand.c | 2 +- src/amd/vulkan/radv_meta_resolve_cs.c | 6 ++++-- 5 files changed, 20 insertions(+), 14 deletions(-) diff --git a/src/amd/vulkan/radv_meta_bufimage.c b/src/amd/vulkan/radv_meta_bufimage.c index 36d7637a82a..ea3bec3323a 100644 --- a/src/amd/vulkan/radv_meta_bufimage.c +++ b/src/amd/vulkan/radv_meta_bufimage.c @@ -92,7 +92,8 @@ build_nir_itob_compute_shader(struct radv_device *dev, bool is_3d) nir_ssa_def *outval = &tex->dest.ssa; nir_image_deref_store(&b, &nir_build_deref_var(&b, output_img)->dest.ssa, coord, - nir_ssa_undef(&b, 1, 32), outval, nir_imm_int(&b, 0)); + nir_ssa_undef(&b, 1, 32), outval, nir_imm_int(&b, 0), + .image_dim = GLSL_SAMPLER_DIM_BUF); return b.shader; } @@ -279,7 +280,7 @@ build_nir_btoi_compute_shader(struct radv_device *dev, bool is_3d) nir_ssa_def *outval = &tex->dest.ssa; nir_image_deref_store(&b, &nir_build_deref_var(&b, output_img)->dest.ssa, img_coord, - nir_ssa_undef(&b, 1, 32), outval, nir_imm_int(&b, 0)); + nir_ssa_undef(&b, 1, 32), outval, nir_imm_int(&b, 0), .image_dim = dim); return b.shader; } @@ -472,7 +473,7 @@ build_nir_btoi_r32g32b32_compute_shader(struct radv_device *dev) nir_image_deref_store(&b, &nir_build_deref_var(&b, output_img)->dest.ssa, coord, nir_ssa_undef(&b, 1, 32), nir_channel(&b, outval, chan), - nir_imm_int(&b, 0)); + nir_imm_int(&b, 0), .image_dim = GLSL_SAMPLER_DIM_BUF); } return b.shader; @@ -628,7 +629,7 @@ build_nir_itoi_compute_shader(struct radv_device *dev, bool is_3d, int samples) for (uint32_t i = 0; i < samples; i++) { nir_ssa_def *outval = &tex_instr[i]->dest.ssa; nir_image_deref_store(&b, &nir_build_deref_var(&b, output_img)->dest.ssa, dst_coord, - nir_imm_int(&b, i), outval, nir_imm_int(&b, 0)); + nir_imm_int(&b, i), outval, nir_imm_int(&b, 0), .image_dim = dim); } return b.shader; @@ -843,7 +844,7 @@ build_nir_itoi_r32g32b32_compute_shader(struct radv_device *dev) nir_image_deref_store(&b, &nir_build_deref_var(&b, output_img)->dest.ssa, dst_coord, nir_ssa_undef(&b, 1, 32), nir_channel(&b, outval, 0), - nir_imm_int(&b, 0)); + nir_imm_int(&b, 0), .image_dim = GLSL_SAMPLER_DIM_BUF); } return b.shader; @@ -972,7 +973,7 @@ build_nir_cleari_compute_shader(struct radv_device *dev, bool is_3d, int samples for (uint32_t i = 0; i < samples; i++) { nir_image_deref_store(&b, &nir_build_deref_var(&b, output_img)->dest.ssa, global_id, - nir_imm_int(&b, i), clear_val, nir_imm_int(&b, 0)); + nir_imm_int(&b, i), clear_val, nir_imm_int(&b, 0), .image_dim = dim); } return b.shader; @@ -1140,7 +1141,7 @@ build_nir_cleari_r32g32b32_compute_shader(struct radv_device *dev) nir_image_deref_store(&b, &nir_build_deref_var(&b, output_img)->dest.ssa, coord, nir_ssa_undef(&b, 1, 32), nir_channel(&b, clear_val, chan), - nir_imm_int(&b, 0)); + nir_imm_int(&b, 0), .image_dim = GLSL_SAMPLER_DIM_BUF); } return b.shader; diff --git a/src/amd/vulkan/radv_meta_dcc_retile.c b/src/amd/vulkan/radv_meta_dcc_retile.c index 6f598176a2a..9fbd958114d 100644 --- a/src/amd/vulkan/radv_meta_dcc_retile.c +++ b/src/amd/vulkan/radv_meta_dcc_retile.c @@ -93,6 +93,7 @@ build_dcc_retile_compute_shader(struct radv_device *dev, struct radeon_surf *sur dcc_val->src[2] = nir_src_for_ssa(nir_ssa_undef(&b, 1, 32)); dcc_val->src[3] = nir_src_for_ssa(nir_imm_int(&b, 0)); nir_ssa_dest_init(&dcc_val->instr, &dcc_val->dest, 1, 32, "dcc_val"); + nir_intrinsic_set_image_dim(dcc_val, GLSL_SAMPLER_DIM_BUF); nir_builder_instr_insert(&b, &dcc_val->instr); nir_intrinsic_instr *store = @@ -103,6 +104,7 @@ build_dcc_retile_compute_shader(struct radv_device *dev, struct radeon_surf *sur store->src[2] = nir_src_for_ssa(nir_ssa_undef(&b, 1, 32)); store->src[3] = nir_src_for_ssa(&dcc_val->dest.ssa); store->src[4] = nir_src_for_ssa(nir_imm_int(&b, 0)); + nir_intrinsic_set_image_dim(store, GLSL_SAMPLER_DIM_BUF); nir_builder_instr_insert(&b, &store->instr); return b.shader; diff --git a/src/amd/vulkan/radv_meta_fast_clear.c b/src/amd/vulkan/radv_meta_fast_clear.c index ccd66226f22..77cf16c8b99 100644 --- a/src/amd/vulkan/radv_meta_fast_clear.c +++ b/src/amd/vulkan/radv_meta_fast_clear.c @@ -56,9 +56,9 @@ build_dcc_decompress_compute_shader(struct radv_device *dev) nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id); - nir_ssa_def *data = - nir_image_deref_load(&b, 4, 32, &nir_build_deref_var(&b, input_img)->dest.ssa, global_id, - nir_ssa_undef(&b, 1, 32), nir_imm_int(&b, 0)); + nir_ssa_def *data = nir_image_deref_load( + &b, 4, 32, &nir_build_deref_var(&b, input_img)->dest.ssa, global_id, nir_ssa_undef(&b, 1, 32), + nir_imm_int(&b, 0), .image_dim = GLSL_SAMPLER_DIM_2D); /* We need a NIR_SCOPE_DEVICE memory_scope because ACO will avoid * creating a vmcnt(0) because it expects the L1 cache to keep memory @@ -68,7 +68,8 @@ build_dcc_decompress_compute_shader(struct radv_device *dev) .memory_semantics = NIR_MEMORY_ACQ_REL, .memory_modes = nir_var_mem_ssbo); nir_image_deref_store(&b, &nir_build_deref_var(&b, output_img)->dest.ssa, global_id, - nir_ssa_undef(&b, 1, 32), data, nir_imm_int(&b, 0)); + nir_ssa_undef(&b, 1, 32), data, nir_imm_int(&b, 0), + .image_dim = GLSL_SAMPLER_DIM_2D); return b.shader; } diff --git a/src/amd/vulkan/radv_meta_fmask_expand.c b/src/amd/vulkan/radv_meta_fmask_expand.c index d0c3e149ffc..a6acfdd8d2a 100644 --- a/src/amd/vulkan/radv_meta_fmask_expand.c +++ b/src/amd/vulkan/radv_meta_fmask_expand.c @@ -92,7 +92,7 @@ build_fmask_expand_compute_shader(struct radv_device *device, int samples) nir_ssa_def *outval = &tex_instr[i]->dest.ssa; nir_image_deref_store(&b, output_img_deref, img_coord, nir_imm_int(&b, i), outval, - nir_imm_int(&b, 0)); + nir_imm_int(&b, 0), .image_dim = GLSL_SAMPLER_DIM_MS, .image_array = true); } return b.shader; diff --git a/src/amd/vulkan/radv_meta_resolve_cs.c b/src/amd/vulkan/radv_meta_resolve_cs.c index 95e8f6b23e9..b659d4aae1c 100644 --- a/src/amd/vulkan/radv_meta_resolve_cs.c +++ b/src/amd/vulkan/radv_meta_resolve_cs.c @@ -100,7 +100,8 @@ build_resolve_compute_shader(struct radv_device *dev, bool is_integer, bool is_s nir_ssa_def *coord = nir_iadd(&b, global_id, dst_offset); nir_image_deref_store(&b, &nir_build_deref_var(&b, output_img)->dest.ssa, coord, - nir_ssa_undef(&b, 1, 32), outval, nir_imm_int(&b, 0)); + nir_ssa_undef(&b, 1, 32), outval, nir_imm_int(&b, 0), + .image_dim = GLSL_SAMPLER_DIM_2D); return b.shader; } @@ -229,7 +230,8 @@ build_depth_stencil_resolve_compute_shader(struct radv_device *dev, int samples, nir_ssa_def *coord = nir_vec4(&b, nir_channel(&b, img_coord, 0), nir_channel(&b, img_coord, 1), nir_channel(&b, img_coord, 2), nir_imm_int(&b, 0)); nir_image_deref_store(&b, &nir_build_deref_var(&b, output_img)->dest.ssa, coord, - nir_ssa_undef(&b, 1, 32), outval, nir_imm_int(&b, 0)); + nir_ssa_undef(&b, 1, 32), outval, nir_imm_int(&b, 0), + .image_dim = GLSL_SAMPLER_DIM_2D, .image_array = true); return b.shader; }