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intel/brw/xe3+: Tweak render target write timings in performance modeling pass.

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Reduce the cycle-count cost estimate used by the performance model for
render target writes on xe3+ in order to match the real-world
observation of shaders with latency lower than the previously
estimated cost of its render target write.

In a shader used by Factorio this would have led us to incorrectly
model the shader as fillrate-bound, even though in reality the shader
is EU-bound and benefits from the higher parallelism of SIMD32, so the
subsequent commit that re-enables the static analysis-based SIMD32
heuristic on PTL would lead to a ~2% regression without this tweak.

There appear to be no other regressions nor other changes from this in
combination with the subsequent commit that enables it to have an
effect, but it is possible that the real cycle count cost of a render
target write still lies below the estimated value, ~400 is just the
upper bound that can be inferred from the behavior of this test case.

Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36618>
This commit is contained in:
Francisco Jerez
2025-07-28 08:24:49 +00:00
committed by Marge Bot
parent 6ccf2a375a
commit 3936a43496
1 changed files with 10 additions and 4 deletions
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src/intel/compiler/brw_analysis_performance.cpp
+10 -4
View File
@@ -599,10 +599,16 @@ namespace {
30 /* XXX */, 0,
10 /* XXX */, 300 /* XXX */, 0, 0, 0, 0);
default:
return calculate_desc(info, EU_UNIT_DP_RC, 2, 0, 0,
0, 450 /* XXX */,
10 /* XXX */, 300 /* XXX */, 0, 0,
0, 0);
if (devinfo->ver >= 30)
return calculate_desc(info, EU_UNIT_DP_RC, 2, 0, 0,
0, 400 /* XXX */,
10 /* XXX */, 300 /* XXX */, 0, 0,
0, 0);
else
return calculate_desc(info, EU_UNIT_DP_RC, 2, 0, 0,
0, 450 /* XXX */,
10 /* XXX */, 300 /* XXX */, 0, 0,
0, 0);
}
case BRW_SFID_SAMPLER: {
return calculate_desc(info, EU_UNIT_SAMPLER, 2, 0, 0, 0, 16,