From 38f74d62771a401bd179a0fc3636b876128e6136 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Mon, 25 Mar 2024 15:06:52 -0400 Subject: [PATCH] radeonsi: disable VRS flat shading for selected 8xMSAA and thick tiling cases for better slow clear performance Reviewed-by: Pierre-Eric Pelloux-Prayer Part-of: --- src/gallium/drivers/radeonsi/si_pipe.h | 1 + src/gallium/drivers/radeonsi/si_state.c | 10 ++++++++++ src/gallium/drivers/radeonsi/si_state_shaders.cpp | 2 +- 3 files changed, 12 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h index 85f9255d420..3745f134f26 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.h +++ b/src/gallium/drivers/radeonsi/si_pipe.h @@ -803,6 +803,7 @@ struct si_framebuffer { bool DB_has_shader_readable_metadata; bool all_DCC_pipe_aligned; bool has_dcc_msaa; + bool disable_vrs_flat_shading; }; enum si_quant_mode diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 61b6195f085..94660d19883 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -3132,6 +3132,7 @@ static void si_set_framebuffer_state(struct pipe_context *ctx, sctx->framebuffer.all_DCC_pipe_aligned = true; sctx->framebuffer.has_dcc_msaa = false; sctx->framebuffer.min_bytes_per_pixel = 0; + sctx->framebuffer.disable_vrs_flat_shading = false; for (i = 0; i < state->nr_cbufs; i++) { if (!state->cbufs[i]) @@ -3190,6 +3191,14 @@ static void si_set_framebuffer_state(struct pipe_context *ctx, if (!sctx->framebuffer.min_bytes_per_pixel || tex->surface.bpe < sctx->framebuffer.min_bytes_per_pixel) sctx->framebuffer.min_bytes_per_pixel = tex->surface.bpe; + + /* Disable VRS flat shading where it decreases performance. + * This gives the best results for slow clears for AMD_TEST=blitperf on Navi31. + */ + if ((sctx->framebuffer.nr_samples == 8 && tex->surface.bpe != 2) || + (tex->surface.thick_tiling && tex->surface.bpe == 4 && + util_format_get_nr_components(surf->base.format) == 4)) + sctx->framebuffer.disable_vrs_flat_shading = true; } struct si_texture *zstex = NULL; @@ -3285,6 +3294,7 @@ static void si_set_framebuffer_state(struct pipe_context *ctx, si_ps_key_update_framebuffer_rasterizer_sample_shading(sctx); si_vs_ps_key_update_rast_prim_smooth_stipple(sctx); si_update_ps_inputs_read_or_disabled(sctx); + si_update_vrs_flat_shading(sctx); sctx->do_update_shaders = true; if (!sctx->decompression_enabled) { diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.cpp b/src/gallium/drivers/radeonsi/si_state_shaders.cpp index 2aeb2bafb3e..cbf136d9b74 100644 --- a/src/gallium/drivers/radeonsi/si_state_shaders.cpp +++ b/src/gallium/drivers/radeonsi/si_state_shaders.cpp @@ -3713,7 +3713,7 @@ void si_update_vrs_flat_shading(struct si_context *sctx) struct si_state_rasterizer *rs = sctx->queued.named.rasterizer; struct si_shader_info *info = &sctx->shader.ps.cso->info; bool allow_flat_shading = - info->allow_flat_shading && + info->allow_flat_shading && !sctx->framebuffer.disable_vrs_flat_shading && !rs->line_smooth && !rs->poly_smooth && !rs->poly_stipple_enable && !rs->point_smooth && (rs->flatshade || !info->uses_interp_color);