From 36e58a14cc3dd057b2535e43ae87f25663113e52 Mon Sep 17 00:00:00 2001
From: Rhys Perry <pendingchaos02@gmail.com>
Date: Mon, 7 Sep 2020 20:20:34 +0100
Subject: [PATCH] aco: fix v_writelane_b32 with two sgprs
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

v_writelane_b32 can take two sgprs but only if one is m0.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Cc: 20.2 <mesa-stable>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6662>
---
 src/amd/compiler/aco_register_allocation.cpp | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/src/amd/compiler/aco_register_allocation.cpp b/src/amd/compiler/aco_register_allocation.cpp
index d5746e5a636..675e575341a 100644
--- a/src/amd/compiler/aco_register_allocation.cpp
+++ b/src/amd/compiler/aco_register_allocation.cpp
@@ -1485,6 +1485,19 @@ bool operand_can_use_reg(chip_class chip, aco_ptr<Instruction>& instr, unsigned
    if (instr->operands[idx].isFixed())
       return instr->operands[idx].physReg() == reg;
 
+   bool is_writelane = instr->opcode == aco_opcode::v_writelane_b32 ||
+                       instr->opcode == aco_opcode::v_writelane_b32_e64;
+   if (chip <= GFX9 && is_writelane && idx <= 1) {
+      /* v_writelane_b32 can take two sgprs but only if one is m0. */
+      bool is_other_sgpr = instr->operands[!idx].isTemp() &&
+                           (!instr->operands[!idx].isFixed() ||
+                            instr->operands[!idx].physReg() != m0);
+      if (is_other_sgpr && instr->operands[!idx].tempId() != instr->operands[idx].tempId()) {
+         instr->operands[idx].setFixed(m0);
+         return reg == m0;
+      }
+   }
+
    if (reg.byte()) {
       unsigned stride = get_subdword_operand_stride(chip, instr, idx, rc);
       if (reg.byte() % stride)