diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index f126ce887a9..c04fff8b943 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -1688,24 +1688,22 @@ static void si_emit_db_render_state(struct si_context *sctx, unsigned index)
    }
 
    if (sctx->gfx_level >= GFX11) {
-      unsigned max_allowed_tiles_in_wave = 0;
+      unsigned max_allowed_tiles_in_wave;
 
       if (sctx->screen->info.has_dedicated_vram) {
          if (sctx->framebuffer.nr_samples == 8)
-            max_allowed_tiles_in_wave = 7;
+            max_allowed_tiles_in_wave = 6;
          else if (sctx->framebuffer.nr_samples == 4)
-            max_allowed_tiles_in_wave = 14;
+            max_allowed_tiles_in_wave = 13;
+         else
+            max_allowed_tiles_in_wave = 0;
       } else {
          if (sctx->framebuffer.nr_samples == 8)
-            max_allowed_tiles_in_wave = 8;
-      }
-
-      /* TODO: We may want to disable this workaround for future chips. */
-      if (sctx->framebuffer.nr_samples >= 4) {
-         if (max_allowed_tiles_in_wave)
-            max_allowed_tiles_in_wave--;
-         else
+            max_allowed_tiles_in_wave = 7;
+         else if (sctx->framebuffer.nr_samples == 4)
             max_allowed_tiles_in_wave = 15;
+         else
+            max_allowed_tiles_in_wave = 0;
       }
 
       db_render_control |= S_028000_MAX_ALLOWED_TILES_IN_WAVE(max_allowed_tiles_in_wave);