diff --git a/src/amd/common/sid.h b/src/amd/common/sid.h index ffc1f0d1f88..66f507da8df 100644 --- a/src/amd/common/sid.h +++ b/src/amd/common/sid.h @@ -50,15 +50,121 @@ #define SI_SHADOWED_REG_BUFFER_SIZE \ (SI_SH_REG_SPACE_SIZE + SI_CONTEXT_REG_SPACE_SIZE + SI_UCONFIG_REG_SPACE_SIZE) -#define EVENT_TYPE_CACHE_FLUSH 0x6 -#define EVENT_TYPE_PS_PARTIAL_FLUSH 0x10 -#define EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT 0x14 -#define EVENT_TYPE_ZPASS_DONE 0x15 -#define EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT 0x16 -#define EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH 0x1f -#define EVENT_TYPE_SAMPLE_STREAMOUTSTATS 0x20 -#define EVENT_TYPE(x) ((x) << 0) -#define EVENT_INDEX(x) ((x) << 8) +/* All registers defined in this packet section don't exist and the only + * purpose of these definitions is to define packet encoding that + * the IB parser understands, and also to have an accurate documentation. + */ +#define PKT3_NOP 0x10 +#define PKT3_SET_BASE 0x11 +#define PKT3_CLEAR_STATE 0x12 +#define PKT3_INDEX_BUFFER_SIZE 0x13 +#define PKT3_DISPATCH_DIRECT 0x15 +#define PKT3_DISPATCH_INDIRECT 0x16 +#define PKT3_ATOMIC_MEM 0x1E +#define ATOMIC_OP(x) ((unsigned)((x)&0x7f) << 0) +#define TC_OP_ATOMIC_SUB_32 0x10 +#define TC_OP_ATOMIC_CMPSWAP_32 0x48 +#define ATOMIC_COMMAND(x) ((unsigned)((x)&0x3) << 8) +#define ATOMIC_COMMAND_SINGLE_PASS 0x0 +#define ATOMIC_COMMAND_LOOP 0x1 +#define PKT3_OCCLUSION_QUERY 0x1F /* GFX7+ */ +#define PKT3_SET_PREDICATION 0x20 +#define PREDICATION_DRAW_NOT_VISIBLE (0 << 8) +#define PREDICATION_DRAW_VISIBLE (1 << 8) +#define PREDICATION_HINT_WAIT (0 << 12) +#define PREDICATION_HINT_NOWAIT_DRAW (1 << 12) +#define PRED_OP(x) ((x) << 16) +#define PREDICATION_OP_CLEAR 0x0 +#define PREDICATION_OP_ZPASS 0x1 +#define PREDICATION_OP_PRIMCOUNT 0x2 +#define PREDICATION_OP_BOOL64 0x3 +#define PREDICATION_OP_BOOL32 0x4 +#define PREDICATION_CONTINUE (1 << 31) +#define PKT3_COND_EXEC 0x22 +#define PKT3_PRED_EXEC 0x23 +#define PKT3_DRAW_INDIRECT 0x24 +#define PKT3_DRAW_INDEX_INDIRECT 0x25 +#define PKT3_INDEX_BASE 0x26 +#define PKT3_DRAW_INDEX_2 0x27 +#define PKT3_CONTEXT_CONTROL 0x28 +#define CC0_LOAD_GLOBAL_CONFIG(x) (((unsigned)(x)&0x1) << 0) +#define CC0_LOAD_PER_CONTEXT_STATE(x) (((unsigned)(x)&0x1) << 1) +#define CC0_LOAD_GLOBAL_UCONFIG(x) (((unsigned)(x)&0x1) << 15) +#define CC0_LOAD_GFX_SH_REGS(x) (((unsigned)(x)&0x1) << 16) +#define CC0_LOAD_CS_SH_REGS(x) (((unsigned)(x)&0x1) << 24) +#define CC0_LOAD_CE_RAM(x) (((unsigned)(x)&0x1) << 28) +#define CC0_UPDATE_LOAD_ENABLES(x) (((unsigned)(x)&0x1) << 31) +#define CC1_SHADOW_GLOBAL_CONFIG(x) (((unsigned)(x)&0x1) << 0) +#define CC1_SHADOW_PER_CONTEXT_STATE(x) (((unsigned)(x)&0x1) << 1) +#define CC1_SHADOW_GLOBAL_UCONFIG(x) (((unsigned)(x)&0x1) << 15) +#define CC1_SHADOW_GFX_SH_REGS(x) (((unsigned)(x)&0x1) << 16) +#define CC1_SHADOW_CS_SH_REGS(x) (((unsigned)(x)&0x1) << 24) +#define CC1_UPDATE_SHADOW_ENABLES(x) (((unsigned)(x)&0x1) << 31) +#define PKT3_INDEX_TYPE 0x2A /* GFX6-8 */ +#define PKT3_DRAW_INDIRECT_MULTI 0x2C +#define R_2C3_DRAW_INDEX_LOC 0x2C3 +#define S_2C3_COUNT_INDIRECT_ENABLE(x) (((unsigned)(x)&0x1) << 30) +#define S_2C3_DRAW_INDEX_ENABLE(x) (((unsigned)(x)&0x1) << 31) +#define PKT3_DRAW_INDEX_AUTO 0x2D +#define PKT3_DRAW_INDEX_IMMD 0x2E /* GFX6 only */ +#define PKT3_NUM_INSTANCES 0x2F +#define PKT3_DRAW_INDEX_MULTI_AUTO 0x30 +#define PKT3_INDIRECT_BUFFER_SI 0x32 /* GFX6 only */ +#define PKT3_INDIRECT_BUFFER_CONST 0x33 +#define PKT3_STRMOUT_BUFFER_UPDATE 0x34 +#define STRMOUT_STORE_BUFFER_FILLED_SIZE 1 +#define STRMOUT_OFFSET_SOURCE(x) (((unsigned)(x)&0x3) << 1) +#define STRMOUT_OFFSET_FROM_PACKET 0 +#define STRMOUT_OFFSET_FROM_VGT_FILLED_SIZE 1 +#define STRMOUT_OFFSET_FROM_MEM 2 +#define STRMOUT_OFFSET_NONE 3 +#define STRMOUT_DATA_TYPE(x) (((unsigned)(x)&0x1) << 7) +#define STRMOUT_SELECT_BUFFER(x) (((unsigned)(x)&0x3) << 8) +#define PKT3_DRAW_INDEX_OFFSET_2 0x35 +#define PKT3_WRITE_DATA 0x37 +#define PKT3_DRAW_INDEX_INDIRECT_MULTI 0x38 +#define PKT3_MEM_SEMAPHORE 0x39 +#define PKT3_MPEG_INDEX 0x3A /* GFX6 only */ +#define PKT3_WAIT_REG_MEM 0x3C +#define WAIT_REG_MEM_EQUAL 3 +#define WAIT_REG_MEM_NOT_EQUAL 4 +#define WAIT_REG_MEM_GREATER_OR_EQUAL 5 +#define WAIT_REG_MEM_MEM_SPACE(x) (((unsigned)(x)&0x3) << 4) +#define WAIT_REG_MEM_PFP (1 << 8) +#define PKT3_MEM_WRITE 0x3D /* GFX6 only */ +#define PKT3_INDIRECT_BUFFER_CIK 0x3F /* GFX7+ */ +#define PKT3_COPY_DATA 0x40 +#define COPY_DATA_SRC_SEL(x) ((x)&0xf) +#define COPY_DATA_REG 0 +#define COPY_DATA_SRC_MEM 1 /* only valid as source */ +#define COPY_DATA_TC_L2 2 +#define COPY_DATA_GDS 3 +#define COPY_DATA_PERF 4 +#define COPY_DATA_IMM 5 +#define COPY_DATA_TIMESTAMP 9 +#define COPY_DATA_DST_SEL(x) (((unsigned)(x)&0xf) << 8) +#define COPY_DATA_DST_MEM_GRBM 1 /* sync across GRBM, deprecated */ +#define COPY_DATA_TC_L2 2 +#define COPY_DATA_GDS 3 +#define COPY_DATA_PERF 4 +#define COPY_DATA_DST_MEM 5 +#define COPY_DATA_COUNT_SEL (1 << 16) +#define COPY_DATA_WR_CONFIRM (1 << 20) +#define COPY_DATA_ENGINE_PFP (1 << 30) +/* 1. header + * 2. SRC_ADDR_LO [31:0] or DATA [31:0] + * 3. CP_SYNC [31] | SRC_SEL [30:29] | ENGINE [27] | DST_SEL [21:20] | SRC_ADDR_HI [15:0] + * 4. DST_ADDR_LO [31:0] + * 5. DST_ADDR_HI [15:0] + * 6. COMMAND [29:22] | BYTE_COUNT [20:0] + */ +#define PKT3_CP_DMA 0x41 /* GFX6 only */ +#define PKT3_PFP_SYNC_ME 0x42 +#define PKT3_SURFACE_SYNC 0x43 /* deprecated on GFX7, use ACQUIRE_MEM */ +#define PKT3_ME_INITIALIZE 0x44 /* GFX6 only */ +#define PKT3_COND_WRITE 0x45 +#define PKT3_EVENT_WRITE 0x46 +#define EVENT_TYPE(x) ((x) << 0) /* 0 - any non-TS event * 1 - ZPASS_DONE * 2 - SAMPLE_PIPELINESTAT @@ -66,198 +172,88 @@ * 4 - *S_PARTIAL_FLUSH * 5 - TS events */ -#define PIXEL_PIPE_STATE_CNTL_COUNTER_ID(x) ((x) << 3) -#define PIXEL_PIPE_STATE_CNTL_STRIDE(x) ((x) << 9) +#define EVENT_INDEX(x) ((x) << 8) +#define PIXEL_PIPE_STATE_CNTL_COUNTER_ID(x) ((x) << 3) +#define PIXEL_PIPE_STATE_CNTL_STRIDE(x) ((x) << 9) /* 0 - 32 bits * 1 - 64 bits * 2 - 128 bits * 3 - 256 bits */ -#define PIXEL_PIPE_STATE_CNTL_INSTANCE_EN_LO(x) ((x) << 11) -#define PIXEL_PIPE_STATE_CNTL_INSTANCE_EN_HI(x) ((x) >> 21) - -/* EVENT_WRITE_EOP (SI-VI) & RELEASE_MEM (GFX9) */ -#define EVENT_TCL1_VOL_ACTION_ENA (1 << 12) -#define EVENT_TC_VOL_ACTION_ENA (1 << 13) -#define EVENT_TC_WB_ACTION_ENA (1 << 15) -#define EVENT_TCL1_ACTION_ENA (1 << 16) -#define EVENT_TC_ACTION_ENA (1 << 17) -#define EVENT_TC_NC_ACTION_ENA (1 << 19) /* GFX9+ */ -#define EVENT_TC_WC_ACTION_ENA (1 << 20) /* GFX9+ */ -#define EVENT_TC_MD_ACTION_ENA (1 << 21) /* GFX9+ */ - -#define PREDICATION_OP_CLEAR 0x0 -#define PREDICATION_OP_ZPASS 0x1 -#define PREDICATION_OP_PRIMCOUNT 0x2 -#define PREDICATION_OP_BOOL64 0x3 -#define PREDICATION_OP_BOOL32 0x4 - -#define PRED_OP(x) ((x) << 16) - -#define PREDICATION_CONTINUE (1 << 31) - -#define PREDICATION_HINT_WAIT (0 << 12) -#define PREDICATION_HINT_NOWAIT_DRAW (1 << 12) - -#define PREDICATION_DRAW_NOT_VISIBLE (0 << 8) -#define PREDICATION_DRAW_VISIBLE (1 << 8) - -#define R600_TEXEL_PITCH_ALIGNMENT_MASK 0x7 - -/* All registers defined in this packet section don't exist and the only - * purpose of these definitions is to define packet encoding that - * the IB parser understands, and also to have an accurate documentation. - */ -#define PKT3_NOP 0x10 -#define PKT3_SET_BASE 0x11 -#define PKT3_CLEAR_STATE 0x12 -#define PKT3_INDEX_BUFFER_SIZE 0x13 -#define PKT3_DISPATCH_DIRECT 0x15 -#define PKT3_DISPATCH_INDIRECT 0x16 -#define PKT3_ATOMIC_MEM 0x1E -#define ATOMIC_OP(x) ((unsigned)((x)&0x7f) << 0) -#define TC_OP_ATOMIC_SUB_32 0x10 -#define TC_OP_ATOMIC_CMPSWAP_32 0x48 -#define ATOMIC_COMMAND(x) ((unsigned)((x)&0x3) << 8) -#define ATOMIC_COMMAND_SINGLE_PASS 0x0 -#define ATOMIC_COMMAND_LOOP 0x1 -#define PKT3_OCCLUSION_QUERY 0x1F /* new for CIK */ -#define PKT3_SET_PREDICATION 0x20 -#define PKT3_COND_EXEC 0x22 -#define PKT3_PRED_EXEC 0x23 -#define PKT3_DRAW_INDIRECT 0x24 -#define PKT3_DRAW_INDEX_INDIRECT 0x25 -#define PKT3_INDEX_BASE 0x26 -#define PKT3_DRAW_INDEX_2 0x27 -#define PKT3_CONTEXT_CONTROL 0x28 -#define CC0_LOAD_GLOBAL_CONFIG(x) (((unsigned)(x)&0x1) << 0) -#define CC0_LOAD_PER_CONTEXT_STATE(x) (((unsigned)(x)&0x1) << 1) -#define CC0_LOAD_GLOBAL_UCONFIG(x) (((unsigned)(x)&0x1) << 15) -#define CC0_LOAD_GFX_SH_REGS(x) (((unsigned)(x)&0x1) << 16) -#define CC0_LOAD_CS_SH_REGS(x) (((unsigned)(x)&0x1) << 24) -#define CC0_LOAD_CE_RAM(x) (((unsigned)(x)&0x1) << 28) -#define CC0_UPDATE_LOAD_ENABLES(x) (((unsigned)(x)&0x1) << 31) -#define CC1_SHADOW_GLOBAL_CONFIG(x) (((unsigned)(x)&0x1) << 0) -#define CC1_SHADOW_PER_CONTEXT_STATE(x) (((unsigned)(x)&0x1) << 1) -#define CC1_SHADOW_GLOBAL_UCONFIG(x) (((unsigned)(x)&0x1) << 15) -#define CC1_SHADOW_GFX_SH_REGS(x) (((unsigned)(x)&0x1) << 16) -#define CC1_SHADOW_CS_SH_REGS(x) (((unsigned)(x)&0x1) << 24) -#define CC1_UPDATE_SHADOW_ENABLES(x) (((unsigned)(x)&0x1) << 31) -#define PKT3_INDEX_TYPE 0x2A /* not on GFX9 */ -#define PKT3_DRAW_INDIRECT_MULTI 0x2C -#define R_2C3_DRAW_INDEX_LOC 0x2C3 -#define S_2C3_COUNT_INDIRECT_ENABLE(x) (((unsigned)(x)&0x1) << 30) -#define S_2C3_DRAW_INDEX_ENABLE(x) (((unsigned)(x)&0x1) << 31) -#define PKT3_DRAW_INDEX_AUTO 0x2D -#define PKT3_DRAW_INDEX_IMMD 0x2E /* not on CIK */ -#define PKT3_NUM_INSTANCES 0x2F -#define PKT3_DRAW_INDEX_MULTI_AUTO 0x30 -#define PKT3_INDIRECT_BUFFER_SI 0x32 /* not on CIK */ -#define PKT3_INDIRECT_BUFFER_CONST 0x33 -#define PKT3_STRMOUT_BUFFER_UPDATE 0x34 -#define STRMOUT_STORE_BUFFER_FILLED_SIZE 1 -#define STRMOUT_OFFSET_SOURCE(x) (((unsigned)(x)&0x3) << 1) -#define STRMOUT_OFFSET_FROM_PACKET 0 -#define STRMOUT_OFFSET_FROM_VGT_FILLED_SIZE 1 -#define STRMOUT_OFFSET_FROM_MEM 2 -#define STRMOUT_OFFSET_NONE 3 -#define STRMOUT_DATA_TYPE(x) (((unsigned)(x)&0x1) << 7) -#define STRMOUT_SELECT_BUFFER(x) (((unsigned)(x)&0x3) << 8) -#define PKT3_DRAW_INDEX_OFFSET_2 0x35 -#define PKT3_WRITE_DATA 0x37 -#define PKT3_DRAW_INDEX_INDIRECT_MULTI 0x38 -#define PKT3_MEM_SEMAPHORE 0x39 -#define PKT3_MPEG_INDEX 0x3A /* not on CIK */ -#define PKT3_WAIT_REG_MEM 0x3C -#define WAIT_REG_MEM_EQUAL 3 -#define WAIT_REG_MEM_NOT_EQUAL 4 -#define WAIT_REG_MEM_GREATER_OR_EQUAL 5 -#define WAIT_REG_MEM_MEM_SPACE(x) (((unsigned)(x)&0x3) << 4) -#define WAIT_REG_MEM_PFP (1 << 8) -#define PKT3_MEM_WRITE 0x3D /* not on CIK */ -#define PKT3_INDIRECT_BUFFER_CIK 0x3F /* new on CIK */ - -#define PKT3_COPY_DATA 0x40 -#define COPY_DATA_SRC_SEL(x) ((x)&0xf) -#define COPY_DATA_REG 0 -#define COPY_DATA_SRC_MEM 1 /* only valid as source */ -#define COPY_DATA_TC_L2 2 -#define COPY_DATA_GDS 3 -#define COPY_DATA_PERF 4 -#define COPY_DATA_IMM 5 -#define COPY_DATA_TIMESTAMP 9 -#define COPY_DATA_DST_SEL(x) (((unsigned)(x)&0xf) << 8) -#define COPY_DATA_DST_MEM_GRBM 1 /* sync across GRBM, deprecated */ -#define COPY_DATA_TC_L2 2 -#define COPY_DATA_GDS 3 -#define COPY_DATA_PERF 4 -#define COPY_DATA_DST_MEM 5 -#define COPY_DATA_COUNT_SEL (1 << 16) -#define COPY_DATA_WR_CONFIRM (1 << 20) -#define COPY_DATA_ENGINE_PFP (1 << 30) -#define PKT3_PFP_SYNC_ME 0x42 -#define PKT3_SURFACE_SYNC 0x43 /* deprecated on CIK, use ACQUIRE_MEM */ -#define PKT3_ME_INITIALIZE 0x44 /* not on CIK */ -#define PKT3_COND_WRITE 0x45 -#define PKT3_EVENT_WRITE 0x46 -#define PKT3_EVENT_WRITE_EOP 0x47 /* not on GFX9 */ -#define PKT3_EVENT_WRITE_EOS 0x48 /* not on GFX9 */ -#define EOP_DST_SEL(x) ((x) << 16) -#define EOP_DST_SEL_MEM 0 -#define EOP_DST_SEL_TC_L2 1 -#define EOP_INT_SEL(x) ((x) << 24) -#define EOP_INT_SEL_NONE 0 -#define EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM 3 -#define EOP_DATA_SEL(x) ((x) << 29) -#define EOP_DATA_SEL_DISCARD 0 -#define EOP_DATA_SEL_VALUE_32BIT 1 -#define EOP_DATA_SEL_VALUE_64BIT 2 -#define EOP_DATA_SEL_TIMESTAMP 3 -#define EOP_DATA_SEL_GDS 5 -#define EOP_DATA_GDS(dw_offset, num_dwords) ((dw_offset) | ((unsigned)(num_dwords) << 16)) - -#define EOS_DATA_SEL(x) ((x) << 29) -#define EOS_DATA_SEL_APPEND_COUNT 0 -#define EOS_DATA_SEL_GDS 1 -#define EOS_DATA_SEL_VALUE_32BIT 2 - +#define PIXEL_PIPE_STATE_CNTL_INSTANCE_EN_LO(x) ((x) << 11) +#define PIXEL_PIPE_STATE_CNTL_INSTANCE_EN_HI(x) ((x) >> 21) +#define PKT3_EVENT_WRITE_EOP 0x47 /* GFX6-8 */ +/* EVENT_WRITE_EOP (GFX6-8) & RELEASE_MEM (GFX9) */ +#define EVENT_TCL1_VOL_ACTION_ENA (1 << 12) +#define EVENT_TC_VOL_ACTION_ENA (1 << 13) +#define EVENT_TC_WB_ACTION_ENA (1 << 15) +#define EVENT_TCL1_ACTION_ENA (1 << 16) +#define EVENT_TC_ACTION_ENA (1 << 17) +#define EVENT_TC_NC_ACTION_ENA (1 << 19) /* GFX9+ */ +#define EVENT_TC_WC_ACTION_ENA (1 << 20) /* GFX9+ */ +#define EVENT_TC_MD_ACTION_ENA (1 << 21) /* GFX9+ */ +#define EOP_DST_SEL(x) ((x) << 16) +#define EOP_DST_SEL_MEM 0 +#define EOP_DST_SEL_TC_L2 1 +#define EOP_INT_SEL(x) ((x) << 24) +#define EOP_INT_SEL_NONE 0 +#define EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM 3 +#define EOP_DATA_SEL(x) ((x) << 29) +#define EOP_DATA_SEL_DISCARD 0 +#define EOP_DATA_SEL_VALUE_32BIT 1 +#define EOP_DATA_SEL_VALUE_64BIT 2 +#define EOP_DATA_SEL_TIMESTAMP 3 +#define EOP_DATA_SEL_GDS 5 +#define EOP_DATA_GDS(dw_offset, num_dwords) ((dw_offset) | ((unsigned)(num_dwords) << 16)) +#define PKT3_EVENT_WRITE_EOS 0x48 /* GFX6-8 */ +#define EOS_DATA_SEL(x) ((x) << 29) +#define EOS_DATA_SEL_APPEND_COUNT 0 +#define EOS_DATA_SEL_GDS 1 +#define EOS_DATA_SEL_VALUE_32BIT 2 /* CP DMA bug: Any use of CP_DMA.DST_SEL=TC must be avoided when EOS packets * are used. Use DST_SEL=MC instead. For prefetch, use SRC_SEL=TC and - * DST_SEL=MC. Only CIK chips are affected. + * DST_SEL=MC. Only GFX7 chips are affected. */ -/* fix CP DMA before uncommenting: */ -/*#define PKT3_EVENT_WRITE_EOS 0x48*/ /* not on GFX9 */ -#define PKT3_RELEASE_MEM 0x49 /* GFX9+ [any ring] or GFX8 [compute ring only] */ -#define PKT3_CONTEXT_REG_RMW 0x51 /* older firmware versions on older chips don't have this */ -#define PKT3_ONE_REG_WRITE 0x57 /* not on CIK */ -#define PKT3_ACQUIRE_MEM 0x58 /* new for CIK */ -#define PKT3_REWIND 0x59 /* VI+ [any ring] or CIK [compute ring only] */ -#define PKT3_LOAD_UCONFIG_REG 0x5E /* GFX7+ */ -#define PKT3_LOAD_SH_REG 0x5F -#define PKT3_LOAD_CONTEXT_REG 0x61 -#define PKT3_LOAD_SH_REG_INDEX 0x63 /* GFX8+ */ -#define PKT3_SET_CONFIG_REG 0x68 -#define PKT3_SET_CONTEXT_REG 0x69 -#define PKT3_SET_SH_REG 0x76 -#define PKT3_SET_SH_REG_OFFSET 0x77 -#define PKT3_SET_UCONFIG_REG 0x79 /* new for CIK */ -#define PKT3_SET_UCONFIG_REG_INDEX 0x7A /* new for GFX9, CP ucode version >= 26 */ -#define PKT3_LOAD_CONST_RAM 0x80 -#define PKT3_WRITE_CONST_RAM 0x81 -#define PKT3_DUMP_CONST_RAM 0x83 -#define PKT3_INCREMENT_CE_COUNTER 0x84 -#define PKT3_INCREMENT_DE_COUNTER 0x85 -#define PKT3_WAIT_ON_CE_COUNTER 0x86 -#define PKT3_SET_SH_REG_INDEX 0x9B -#define PKT3_LOAD_CONTEXT_REG_INDEX 0x9F /* new for VI */ -#define PKT3_EVENT_WRITE_ZPASS 0xB1 /* GFX11+ & PFP version >= 1458 */ -#define EVENT_WRITE_ZPASS_PFP_VERSION 1458 - -#define PKT3_DISPATCH_TASK_STATE_INIT 0xA9 /* Tells the HW about the task control buffer */ -#define PKT3_DISPATCH_MESH_INDIRECT_MULTI 0x4C /* Indirect mesh shader only dispatch [GFX only] */ -#define PKT3_DISPATCH_TASKMESH_GFX 0x4D /* Task+mesh shader dispatch [GFX side] */ -#define PKT3_DISPATCH_TASKMESH_DIRECT_ACE 0xAA /* Direct task+mesh shader dispatch [ACE side] */ -#define PKT3_DISPATCH_TASKMESH_INDIRECT_MULTI_ACE 0xAD /* Indirect task+mesh shader dispatch [ACE side] */ +#define PKT3_EVENT_WRITE_EOS 0x48 /* GFX6-8, breaks CP DMA */ +#define PKT3_RELEASE_MEM 0x49 /* GFX9+ [any ring] or GFX8 [compute ring only] */ +/* 1. header + * 2. CP_SYNC [31] | SRC_SEL [30:29] | DST_SEL [21:20] | ENGINE [0] + * 2. SRC_ADDR_LO [31:0] or DATA [31:0] + * 3. SRC_ADDR_HI [31:0] + * 4. DST_ADDR_LO [31:0] + * 5. DST_ADDR_HI [31:0] + * 6. COMMAND [29:22] | BYTE_COUNT [20:0] + */ +#define PKT3_DMA_DATA 0x50 /* GFX7+ */ +#define PKT3_DISPATCH_MESH_INDIRECT_MULTI 0x4C /* Indirect mesh shader only dispatch [GFX only] */ +#define PKT3_DISPATCH_TASKMESH_GFX 0x4D /* Task+mesh shader dispatch [GFX side] */ +#define PKT3_CONTEXT_REG_RMW 0x51 /* older firmware versions on older chips don't have this */ +#define PKT3_ONE_REG_WRITE 0x57 /* GFX6 only */ +#define PKT3_ACQUIRE_MEM 0x58 /* GFX7+ */ +#define PKT3_REWIND 0x59 /* GFX8+ [any ring] or GFX7 [compute ring only] */ +#define PKT3_LOAD_UCONFIG_REG 0x5E /* GFX7+ */ +#define PKT3_LOAD_SH_REG 0x5F +#define PKT3_LOAD_CONTEXT_REG 0x61 +#define PKT3_LOAD_SH_REG_INDEX 0x63 /* GFX8+ */ +#define PKT3_SET_CONFIG_REG 0x68 +#define PKT3_SET_CONTEXT_REG 0x69 +#define PKT3_SET_SH_REG 0x76 +#define PKT3_SET_SH_REG_OFFSET 0x77 +#define PKT3_SET_UCONFIG_REG 0x79 /* GFX7+ */ +#define PKT3_SET_UCONFIG_REG_INDEX 0x7A /* new for GFX9, CP ucode version >= 26 */ +#define PKT3_LOAD_CONST_RAM 0x80 +#define PKT3_WRITE_CONST_RAM 0x81 +#define PKT3_DUMP_CONST_RAM 0x83 +#define PKT3_INCREMENT_CE_COUNTER 0x84 +#define PKT3_INCREMENT_DE_COUNTER 0x85 +#define PKT3_WAIT_ON_CE_COUNTER 0x86 +#define PKT3_SET_SH_REG_INDEX 0x9B +#define PKT3_LOAD_CONTEXT_REG_INDEX 0x9F /* GFX8+ */ +#define PKT3_DISPATCH_TASK_STATE_INIT 0xA9 /* Tells the HW about the task control buffer */ +#define PKT3_DISPATCH_TASKMESH_DIRECT_ACE 0xAA /* Direct task+mesh shader dispatch [ACE side] */ +#define PKT3_DISPATCH_TASKMESH_INDIRECT_MULTI_ACE 0xAD /* Indirect task+mesh shader dispatch [ACE side] */ +#define PKT3_EVENT_WRITE_ZPASS 0xB1 /* GFX11+ & PFP version >= 1458 */ +#define EVENT_WRITE_ZPASS_PFP_VERSION 1458 #define PKT_TYPE_S(x) (((unsigned)(x)&0x3) << 30) #define PKT_TYPE_G(x) (((x) >> 30) & 0x3) @@ -281,25 +277,6 @@ #define PKT2_NOP_PAD PKT_TYPE_S(2) #define PKT3_NOP_PAD PKT3(PKT3_NOP, 0x3fff, 0) /* header-only version */ -#define PKT3_CP_DMA 0x41 -/* 1. header - * 2. SRC_ADDR_LO [31:0] or DATA [31:0] - * 3. CP_SYNC [31] | SRC_SEL [30:29] | ENGINE [27] | DST_SEL [21:20] | SRC_ADDR_HI [15:0] - * 4. DST_ADDR_LO [31:0] - * 5. DST_ADDR_HI [15:0] - * 6. COMMAND [29:22] | BYTE_COUNT [20:0] - */ - -#define PKT3_DMA_DATA 0x50 /* new for CIK */ -/* 1. header - * 2. CP_SYNC [31] | SRC_SEL [30:29] | DST_SEL [21:20] | ENGINE [0] - * 2. SRC_ADDR_LO [31:0] or DATA [31:0] - * 3. SRC_ADDR_HI [31:0] - * 4. DST_ADDR_LO [31:0] - * 5. DST_ADDR_HI [31:0] - * 6. COMMAND [29:22] | BYTE_COUNT [20:0] - */ - /* SI async DMA packets */ #define SI_DMA_PACKET(cmd, sub_cmd, n) \ ((((unsigned)(cmd)&0xF) << 28) | (((unsigned)(sub_cmd)&0xFF) << 20) | \ diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 278e71b4704..43a8e96cf35 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -10852,7 +10852,7 @@ radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer) } radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); - radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0)); + radeon_emit(cs, EVENT_TYPE(V_028A90_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0)); radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0)); radeon_emit(cs, diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c index 13e43352d45..06ab5f15d7d 100644 --- a/src/amd/vulkan/si_cmd_buffer.c +++ b/src/amd/vulkan/si_cmd_buffer.c @@ -999,7 +999,7 @@ si_cs_emit_write_event_eop(struct radeon_cmdbuf *cs, enum amd_gfx_level gfx_leve */ if (gfx_level == GFX9 && !is_mec) { radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0)); - radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1)); + radeon_emit(cs, EVENT_TYPE(V_028A90_ZPASS_DONE) | EVENT_INDEX(1)); radeon_emit(cs, gfx9_eop_bug_va); radeon_emit(cs, gfx9_eop_bug_va >> 32); } diff --git a/src/gallium/drivers/radeonsi/si_fence.c b/src/gallium/drivers/radeonsi/si_fence.c index c255af55e2f..3dea23cacaa 100644 --- a/src/gallium/drivers/radeonsi/si_fence.c +++ b/src/gallium/drivers/radeonsi/si_fence.c @@ -109,7 +109,7 @@ void si_cp_release_mem(struct si_context *ctx, struct radeon_cmdbuf *cs, unsigne assert(16 * ctx->screen->info.max_render_backends <= scratch->b.b.width0); radeon_emit(PKT3(PKT3_EVENT_WRITE, 2, 0)); - radeon_emit(EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1)); + radeon_emit(EVENT_TYPE(V_028A90_ZPASS_DONE) | EVENT_INDEX(1)); radeon_emit(scratch->gpu_address); radeon_emit(scratch->gpu_address >> 32); diff --git a/src/gallium/drivers/radeonsi/si_state_streamout.c b/src/gallium/drivers/radeonsi/si_state_streamout.c index 230dcf00bf9..d6b0f3f3e86 100644 --- a/src/gallium/drivers/radeonsi/si_state_streamout.c +++ b/src/gallium/drivers/radeonsi/si_state_streamout.c @@ -236,7 +236,7 @@ static void si_flush_vgt_streamout(struct si_context *sctx) } radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0)); - radeon_emit(EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0)); + radeon_emit(EVENT_TYPE(V_028A90_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0)); radeon_emit(PKT3(PKT3_WAIT_REG_MEM, 5, 0)); radeon_emit(WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */