diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 870ecc5c04d..b7724bf8e8d 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -799,7 +799,7 @@ VkResult anv_CreateDevice(
    /* Emit the CPS states before running the initialization batch as those
     * structures are referenced.
     */
-   if (device->info->ver >= 12) {
+   if (device->info->ver >= 12 && device->info->ver < 30) {
       uint32_t n_cps_states = 3 * 3; /* All combinaisons of X by Y CP sizes (1, 2, 4) */
 
       if (device->info->has_coarse_pixel_primitive_and_cb)
@@ -965,8 +965,13 @@ VkResult anv_CreateDevice(
    }
    if (!device->vk.enabled_extensions.EXT_sample_locations)
       BITSET_CLEAR(device->gfx_dirty_state, ANV_GFX_STATE_SAMPLE_PATTERN);
-   if (!device->vk.enabled_extensions.KHR_fragment_shading_rate)
-      BITSET_CLEAR(device->gfx_dirty_state, ANV_GFX_STATE_CPS);
+   if (!device->vk.enabled_extensions.KHR_fragment_shading_rate) {
+      if (device->info->ver >= 30) {
+         BITSET_CLEAR(device->gfx_dirty_state, ANV_GFX_STATE_COARSE_PIXEL);
+      } else {
+         BITSET_CLEAR(device->gfx_dirty_state, ANV_GFX_STATE_CPS);
+      }
+   }
    if (!device->vk.enabled_extensions.EXT_mesh_shader) {
       BITSET_CLEAR(device->gfx_dirty_state, ANV_GFX_STATE_SBE_MESH);
       BITSET_CLEAR(device->gfx_dirty_state, ANV_GFX_STATE_CLIP_MESH);
diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 179df1d4b10..f3bd6c5c4e9 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -1457,6 +1457,7 @@ enum anv_gfx_state_bits {
    ANV_GFX_STATE_CLIP,
    ANV_GFX_STATE_CC_STATE,
    ANV_GFX_STATE_CC_STATE_PTR,
+   ANV_GFX_STATE_COARSE_PIXEL,
    ANV_GFX_STATE_CPS,
    ANV_GFX_STATE_DEPTH_BOUNDS,
    ANV_GFX_STATE_INDEX_BUFFER,
@@ -1554,6 +1555,15 @@ struct anv_gfx_dynamic_state {
       uint32_t TriangleFanProvokingVertexSelect;
    } clip;
 
+   /* 3DSTATE_COARSE_PIXEL */
+   struct {
+      uint32_t    CPSizeX;
+      uint32_t    CPSizeY;
+      uint32_t    CPSizeCombiner0Opcode;
+      uint32_t    CPSizeCombiner1Opcode;
+      bool        DisableCPSPointers;
+   } coarse_pixel;
+
    /* 3DSTATE_CPS/3DSTATE_CPS_POINTERS */
    struct {
       /* Gfx11 */
diff --git a/src/intel/vulkan/genX_gfx_state.c b/src/intel/vulkan/genX_gfx_state.c
index 6266ce0f891..f88e02c138c 100644
--- a/src/intel/vulkan/genX_gfx_state.c
+++ b/src/intel/vulkan/genX_gfx_state.c
@@ -164,7 +164,7 @@ genX(streamout_prologue)(struct anv_cmd_buffer *cmd_buffer)
 #endif
 }
 
-#if GFX_VER >= 12
+#if GFX_VER >= 12 && GFX_VER < 30
 static uint32_t
 get_cps_state_offset(const struct anv_device *device, bool cps_enabled,
                      const struct vk_fragment_shading_rate_state *fsr)
@@ -197,7 +197,32 @@ get_cps_state_offset(const struct anv_device *device, bool cps_enabled,
 
    return device->cps_states.offset + offset;
 }
-#endif /* GFX_VER >= 12 */
+#endif /* GFX_VER >= 12 && GFX_VER < 30 */
+
+#if GFX_VER >= 30
+static uint32_t
+get_cps_size(uint32_t size)
+{
+   switch (size) {
+   case 1:
+      return CPSIZE_1;
+   case 2:
+      return CPSIZE_2;
+   case 4:
+      return CPSIZE_4;
+   default:
+      unreachable("Invalid size");
+   }
+}
+
+static const uint32_t vk_to_intel_shading_rate_combiner_op[] = {
+   [VK_FRAGMENT_SHADING_RATE_COMBINER_OP_KEEP_KHR] = CPS_COMB_OP_PASSTHROUGH,
+   [VK_FRAGMENT_SHADING_RATE_COMBINER_OP_REPLACE_KHR] = CPS_COMB_OP_OVERRIDE,
+   [VK_FRAGMENT_SHADING_RATE_COMBINER_OP_MIN_KHR] = CPS_COMB_OP_HIGH_QUALITY,
+   [VK_FRAGMENT_SHADING_RATE_COMBINER_OP_MAX_KHR] = CPS_COMB_OP_LOW_QUALITY,
+   [VK_FRAGMENT_SHADING_RATE_COMBINER_OP_MUL_KHR] = CPS_COMB_OP_RELATIVE,
+};
+#endif
 
 static bool
 has_ds_feedback_loop(const struct vk_dynamic_graphics_state *dyn)
@@ -960,17 +985,27 @@ update_cps(struct anv_gfx_dynamic_state *hw_state,
    if (!wm_prog_data)
       return;
 
-   const bool cps_enable =
+   UNUSED const bool cps_enable =
       brw_wm_prog_data_is_coarse(wm_prog_data, hw_state->fs_msaa_flags);
 
-#if GFX_VER == 11
+#if GFX_VER >= 30
+   SET(COARSE_PIXEL, coarse_pixel.CPSizeX,
+       get_cps_size(dyn->fsr.fragment_size.width));
+   SET(COARSE_PIXEL, coarse_pixel.CPSizeY,
+       get_cps_size(dyn->fsr.fragment_size.height));
+   SET(COARSE_PIXEL, coarse_pixel.CPSizeCombiner0Opcode,
+       vk_to_intel_shading_rate_combiner_op[dyn->fsr.combiner_ops[0]]);
+   SET(COARSE_PIXEL, coarse_pixel.CPSizeCombiner1Opcode,
+       vk_to_intel_shading_rate_combiner_op[dyn->fsr.combiner_ops[1]]);
+#elif GFX_VER >= 12
+   SET(CPS, cps.CoarsePixelShadingStateArrayPointer,
+       get_cps_state_offset(device, cps_enable, &dyn->fsr));
+#else
+   STATIC_ASSERT(GFX_VER == 11);
    SET(CPS, cps.CoarsePixelShadingMode,
             cps_enable ? CPS_MODE_CONSTANT : CPS_MODE_NONE);
    SET(CPS, cps.MinCPSizeX, dyn->fsr.fragment_size.width);
    SET(CPS, cps.MinCPSizeY, dyn->fsr.fragment_size.height);
-#elif GFX_VER >= 12
-   SET(CPS, cps.CoarsePixelShadingStateArrayPointer,
-            get_cps_state_offset(device, cps_enable, &dyn->fsr));
 #endif
 }
 #endif
@@ -2430,6 +2465,17 @@ cmd_buffer_gfx_state_emission(struct anv_cmd_buffer *cmd_buffer)
       }
    }
 
+#if GFX_VER >= 30
+   if (BITSET_TEST(hw_state->dirty, ANV_GFX_STATE_COARSE_PIXEL)) {
+      anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_COARSE_PIXEL), coarse_pixel) {
+         coarse_pixel.DisableCPSPointers = true;
+         SET(coarse_pixel, coarse_pixel, CPSizeX);
+         SET(coarse_pixel, coarse_pixel, CPSizeY);
+         SET(coarse_pixel, coarse_pixel, CPSizeCombiner0Opcode);
+         SET(coarse_pixel, coarse_pixel, CPSizeCombiner1Opcode);
+      }
+   }
+#else
    if (BITSET_TEST(hw_state->dirty, ANV_GFX_STATE_CPS)) {
 #if GFX_VER == 11
       anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CPS), cps) {
@@ -2461,6 +2507,7 @@ cmd_buffer_gfx_state_emission(struct anv_cmd_buffer *cmd_buffer)
       }
 #endif
    }
+#endif /* GFX_VER >= 30 */
 
    if (BITSET_TEST(hw_state->dirty, ANV_GFX_STATE_SF)) {
       anv_batch_emit_merge(&cmd_buffer->batch, GENX(3DSTATE_SF),
diff --git a/src/intel/vulkan/genX_init_state.c b/src/intel/vulkan/genX_init_state.c
index f0830da3422..877a2c41324 100644
--- a/src/intel/vulkan/genX_init_state.c
+++ b/src/intel/vulkan/genX_init_state.c
@@ -617,8 +617,8 @@ init_render_queue_state(struct anv_queue *queue, bool is_companion_rcs_batch)
     * the dynamic state base address we need to emit this instruction after
     * STATE_BASE_ADDRESS in init_common_queue_state().
     */
-#if GFX_VER == 11
-   anv_batch_emit(batch, GENX(3DSTATE_CPS), cps);
+#if GFX_VER >= 30
+   anv_batch_emit(batch, GENX(3DSTATE_COARSE_PIXEL), cps);
 #elif GFX_VER >= 12
    anv_batch_emit(batch, GENX(3DSTATE_CPS_POINTERS), cps) {
       assert(device->cps_states.alloc_size != 0);
@@ -626,6 +626,8 @@ init_render_queue_state(struct anv_queue *queue, bool is_companion_rcs_batch)
       cps.CoarsePixelShadingStateArrayPointer =
          device->cps_states.offset;
    }
+#elif GFX_VER == 11
+   anv_batch_emit(batch, GENX(3DSTATE_CPS), cps);
 #endif
 
 #if GFX_VERx10 >= 125
@@ -977,7 +979,7 @@ genX(init_device_state)(struct anv_device *device)
 void
 genX(init_cps_device_state)(struct anv_device *device)
 {
-#if GFX_VER >= 12
+#if GFX_VER >= 12 && GFX_VER < 30
    void *cps_state_ptr = device->cps_states.map;
 
    /* Disabled CPS mode */
@@ -1032,7 +1034,7 @@ genX(init_cps_device_state)(struct anv_device *device)
          }
       }
    }
-#endif /* GFX_VER >= 12 */
+#endif /* GFX_VER >= 12 && GFX_VER < 30 */
 }
 
 void