diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index e481791ad5a..b22b32e5112 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -2849,9 +2849,9 @@ fs_visitor::opt_zero_samples()
    /* Gfx4 infers the texturing opcode based on the message length so we can't
     * change it.  Gfx12.5 has restrictions on the number of coordinate
     * parameters that have to be provided for some texture types
-    * (Wa_14013363432).
+    * (Wa_14012688258).
     */
-   if (devinfo->ver < 5 || devinfo->verx10 == 125)
+   if (devinfo->ver < 5 || intel_needs_workaround(devinfo, 14012688258))
       return false;
 
    bool progress = false;
diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index 470936549e9..36d822eb747 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -6043,11 +6043,12 @@ fs_visitor::nir_emit_texture(const fs_builder &bld, nir_tex_instr *instr)
             break;
          }
 
-         /* Wa_14013363432:
+         /* Wa_14012688258:
           *
           * Compiler should send U,V,R parameters even if V,R are 0.
           */
-         if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE && devinfo->verx10 == 125)
+         if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
+             intel_needs_workaround(devinfo, 14012688258))
             assert(instr->coord_components >= 3u);
          break;
       case nir_tex_src_ddx: