intel/compiler: Fix SIMD lowering when instruction needs a larger SIMD

When lower_simd_width() encounters an instruction that needs a larger
SIMD, for example SHADER_OPCODE_TXS_LOGICAL in Gfx4 needs at least
SIMD16.  In this case the builder needs to be at least as large as
max_width, otherwise the group() setup will assert.

Turns out this did not assert before "by accident", since it was
relying on the default fs_visitor builder that had a dispatch width of 64,
a bogus placeholder value, expected not to be used.

However, when we changed the code to remove that builder (and the bogus
value), we created a new builder in the pass shader dispatch_width --
which work fine except in the case where we want to "lower" the SIMD above
the shader dispatch width.  The fix is to also consider the already
calculated max_width when creating the builder.

Fixes: 5b8ec015f2 ("intel/compiler: Don't use fs_visitor::bld in remaining places")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10338
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27782>

src/intel/compiler/brw_fs_lower_simd_width.cpp

@@ -637,7 +637,8 @@ brw_fs_lower_simd_width(fs_visitor &s)
           */
          const unsigned max_width = MAX2(inst->exec_size, lower_width);
 
-         const fs_builder bld = fs_builder(&s).at_end();
+         const fs_builder bld =
+            fs_builder(&s, MAX2(max_width, s.dispatch_width)).at_end();
          const fs_builder ibld = bld.at(block, inst)
                                     .exec_all(inst->force_writemask_all)
                                     .group(max_width, inst->group / max_width);