diff --git a/src/intel/compiler/brw_builder.h b/src/intel/compiler/brw_builder.h
index 37faa045743..fc2e708baa2 100644
--- a/src/intel/compiler/brw_builder.h
+++ b/src/intel/compiler/brw_builder.h
@@ -53,13 +53,13 @@ public:
    explicit brw_builder(brw_shader *s) : brw_builder(s, s->dispatch_width) {}
 
    /**
-    * Construct an brw_builder that inserts instructions into \p shader
-    * before instruction \p inst in basic block \p block.  The default
+    * Construct an brw_builder that inserts instructions before
+    * instruction \p inst in the same basic block.  The default
     * execution controls and debug annotation are initialized from the
     * instruction passed as argument.
     */
-   brw_builder(brw_shader *shader, bblock_t *block, brw_inst *inst) :
-      shader(shader), block(block), cursor(inst),
+   explicit brw_builder(brw_inst *inst) :
+      shader(inst->block->cfg->s), block(inst->block), cursor(inst),
       _dispatch_width(inst->exec_size),
       _group(inst->group),
       force_writemask_all(inst->force_writemask_all)
diff --git a/src/intel/compiler/brw_cfg.cpp b/src/intel/compiler/brw_cfg.cpp
index 949cb2e9601..e0db87116fb 100644
--- a/src/intel/compiler/brw_cfg.cpp
+++ b/src/intel/compiler/brw_cfg.cpp
@@ -195,7 +195,7 @@ append_inst(bblock_t *block, brw_inst *inst)
    block->instructions.push_tail(inst);
 }
 
-cfg_t::cfg_t(const brw_shader *s, exec_list *instructions) :
+cfg_t::cfg_t(brw_shader *s, exec_list *instructions) :
    s(s)
 {
    mem_ctx = ralloc_context(NULL);
diff --git a/src/intel/compiler/brw_cfg.h b/src/intel/compiler/brw_cfg.h
index 2f1d9d7c015..18b5bf574cc 100644
--- a/src/intel/compiler/brw_cfg.h
+++ b/src/intel/compiler/brw_cfg.h
@@ -319,7 +319,7 @@ bblock_t::last_non_control_flow_inst()
 struct cfg_t {
    DECLARE_RALLOC_CXX_OPERATORS(cfg_t)
 
-   cfg_t(const brw_shader *s, exec_list *instructions);
+   cfg_t(brw_shader *s, exec_list *instructions);
    ~cfg_t();
 
    void remove_block(bblock_t *block);
@@ -347,7 +347,7 @@ struct cfg_t {
     */
    inline void adjust_block_ips();
 
-   const struct brw_shader *s;
+   struct brw_shader *s;
    void *mem_ctx;
 
    /** Ordered list (by ip) of basic blocks */
diff --git a/src/intel/compiler/brw_lower.cpp b/src/intel/compiler/brw_lower.cpp
index daade3a3e34..2eb714c31f4 100644
--- a/src/intel/compiler/brw_lower.cpp
+++ b/src/intel/compiler/brw_lower.cpp
@@ -60,7 +60,7 @@ brw_lower_load_payload(brw_shader &s)
       assert(inst->saturate == false);
       brw_reg dst = inst->dst;
 
-      const brw_builder ibld(&s, block, inst);
+      const brw_builder ibld(inst);
       const brw_builder ubld = ibld.exec_all();
 
       for (uint8_t i = 0; i < inst->header_size;) {
@@ -155,7 +155,7 @@ brw_lower_csel(brw_shader &s)
       }
 
       if (!supported) {
-         const brw_builder ibld(&s, block, inst);
+         const brw_builder ibld(inst);
 
          /* CSEL: dst = src2 <op> 0 ? src0 : src1 */
          brw_reg zero = brw_imm_reg(orig_type);
@@ -187,7 +187,7 @@ brw_lower_sub_sat(brw_shader &s)
    bool progress = false;
 
    foreach_block_and_inst_safe(block, brw_inst, inst, s.cfg) {
-      const brw_builder ibld(&s, block, inst);
+      const brw_builder ibld(inst);
 
       if (inst->opcode == SHADER_OPCODE_USUB_SAT ||
           inst->opcode == SHADER_OPCODE_ISUB_SAT) {
@@ -296,7 +296,7 @@ brw_lower_barycentrics(brw_shader &s)
       if (inst->exec_size < 16)
          continue;
 
-      const brw_builder ibld(&s, block, inst);
+      const brw_builder ibld(inst);
       const brw_builder ubld = ibld.exec_all().group(8, 0);
 
       switch (inst->opcode) {
@@ -357,7 +357,7 @@ static bool
 lower_derivative(brw_shader &s, bblock_t *block, brw_inst *inst,
                  unsigned swz0, unsigned swz1)
 {
-   const brw_builder ubld = brw_builder(&s, block, inst).exec_all();
+   const brw_builder ubld = brw_builder(inst).exec_all();
    const brw_reg tmp0 = ubld.vgrf(inst->src[0].type);
    const brw_reg tmp1 = ubld.vgrf(inst->src[0].type);
 
@@ -436,11 +436,11 @@ brw_lower_find_live_channel(brw_shader &s)
        * useless there.
        */
 
-      const brw_builder ibld(&s, block, inst);
+      const brw_builder ibld(inst);
       if (!inst->is_partial_write())
          ibld.emit_undef_for_dst(inst);
 
-      const brw_builder ubld = brw_builder(&s, block, inst).exec_all().group(1, 0);
+      const brw_builder ubld = brw_builder(inst).exec_all().group(1, 0);
 
       brw_reg exec_mask = ubld.vgrf(BRW_TYPE_UD);
       ubld.UNDEF(exec_mask);
@@ -532,7 +532,7 @@ brw_lower_sends_overlapping_payload(brw_shader &s)
          /* Sadly, we've lost all notion of channels and bit sizes at this
           * point.  Just WE_all it.
           */
-         const brw_builder ibld = brw_builder(&s, block, inst).exec_all().group(16, 0);
+         const brw_builder ibld = brw_builder(inst).exec_all().group(16, 0);
          brw_reg copy_src = retype(inst->src[arg], BRW_TYPE_UD);
          brw_reg copy_dst = tmp;
          for (unsigned i = 0; i < len; i += 2) {
@@ -610,7 +610,7 @@ brw_lower_alu_restrictions(brw_shader &s)
             assert(!inst->saturate);
             assert(!inst->src[0].abs);
             assert(!inst->src[0].negate);
-            const brw_builder ibld(&s, block, inst);
+            const brw_builder ibld(inst);
 
             enum brw_reg_type type = brw_type_with_size(inst->dst.type, 32);
 
@@ -634,7 +634,7 @@ brw_lower_alu_restrictions(brw_shader &s)
             assert(!inst->src[0].abs && !inst->src[0].negate);
             assert(!inst->src[1].abs && !inst->src[1].negate);
             assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
-            const brw_builder ibld(&s, block, inst);
+            const brw_builder ibld(inst);
 
             enum brw_reg_type type = brw_type_with_size(inst->dst.type, 32);
 
@@ -811,7 +811,7 @@ brw_lower_send_gather_inst(brw_shader &s, bblock_t *block, brw_inst *inst)
    /* Fill out ARF scalar register with the physical register numbers
     * and use SEND_GATHER.
     */
-   brw_builder ubld = brw_builder(&s, block, inst).group(1, 0).exec_all();
+   brw_builder ubld = brw_builder(inst).group(1, 0).exec_all();
    for (unsigned q = 0; q < DIV_ROUND_UP(count, 8); q++) {
       uint64_t v = 0;
       for (unsigned i = 0; i < 8; i++) {
@@ -857,7 +857,7 @@ brw_lower_load_subgroup_invocation(brw_shader &s)
          continue;
 
       const brw_builder abld =
-         brw_builder(&s, block, inst).annotate("SubgroupInvocation");
+         brw_builder(inst).annotate("SubgroupInvocation");
       const brw_builder ubld8 = abld.group(8, 0).exec_all();
       ubld8.UNDEF(inst->dst);
 
@@ -905,7 +905,7 @@ brw_lower_indirect_mov(brw_shader &s)
          assert(brw_type_size_bytes(inst->src[0].type) ==
                 brw_type_size_bytes(inst->dst.type));
 
-         const brw_builder ibld(&s, block, inst);
+         const brw_builder ibld(inst);
 
          /* Extract unaligned part */
          uint16_t extra_offset = inst->src[0].offset & 0x1;
diff --git a/src/intel/compiler/brw_lower_dpas.cpp b/src/intel/compiler/brw_lower_dpas.cpp
index 75f97934343..522772adf0c 100644
--- a/src/intel/compiler/brw_lower_dpas.cpp
+++ b/src/intel/compiler/brw_lower_dpas.cpp
@@ -278,7 +278,7 @@ brw_lower_dpas(brw_shader &v)
          continue;
 
       const unsigned exec_size = v.devinfo->ver >= 20 ? 16 : 8;
-      const brw_builder bld = brw_builder(&v, block, inst).group(exec_size, 0).exec_all();
+      const brw_builder bld = brw_builder(inst).group(exec_size, 0).exec_all();
 
       if (brw_type_is_float(inst->dst.type)) {
          f16_using_mac(bld, inst);
diff --git a/src/intel/compiler/brw_lower_integer_multiplication.cpp b/src/intel/compiler/brw_lower_integer_multiplication.cpp
index 493fe9c5252..95c94a54c29 100644
--- a/src/intel/compiler/brw_lower_integer_multiplication.cpp
+++ b/src/intel/compiler/brw_lower_integer_multiplication.cpp
@@ -140,7 +140,7 @@ static void
 brw_lower_mul_dword_inst(brw_shader &s, brw_inst *inst, bblock_t *block)
 {
    const intel_device_info *devinfo = s.devinfo;
-   const brw_builder ibld(&s, block, inst);
+   const brw_builder ibld(inst);
 
    /* It is correct to use inst->src[1].d in both end of the comparison.
     * Using .ud in the UINT16_MAX comparison would cause any negative value to
@@ -301,7 +301,7 @@ static void
 brw_lower_mul_qword_inst(brw_shader &s, brw_inst *inst, bblock_t *block)
 {
    const intel_device_info *devinfo = s.devinfo;
-   const brw_builder ibld(&s, block, inst);
+   const brw_builder ibld(inst);
 
    /* Considering two 64-bit integers ab and cd where each letter        ab
     * corresponds to 32 bits, we get a 128-bit result WXYZ. We         * cd
@@ -370,7 +370,7 @@ static void
 brw_lower_mulh_inst(brw_shader &s, brw_inst *inst, bblock_t *block)
 {
    const intel_device_info *devinfo = s.devinfo;
-   const brw_builder ibld(&s, block, inst);
+   const brw_builder ibld(inst);
 
    /* According to the BDW+ BSpec page for the "Multiply Accumulate
     * High" instruction:
diff --git a/src/intel/compiler/brw_lower_logical_sends.cpp b/src/intel/compiler/brw_lower_logical_sends.cpp
index 6c43b91d075..ccfa2b27858 100644
--- a/src/intel/compiler/brw_lower_logical_sends.cpp
+++ b/src/intel/compiler/brw_lower_logical_sends.cpp
@@ -2535,7 +2535,7 @@ brw_lower_logical_sends(brw_shader &s)
    bool progress = false;
 
    foreach_block_and_inst_safe(block, brw_inst, inst, s.cfg) {
-      const brw_builder ibld(&s, block, inst);
+      const brw_builder ibld(inst);
 
       switch (inst->opcode) {
       case FS_OPCODE_FB_WRITE_LOGICAL:
@@ -2683,8 +2683,7 @@ brw_lower_uniform_pull_constant_loads(brw_shader &s)
       assert(size_B.file == IMM);
 
       if (devinfo->has_lsc) {
-         const brw_builder ubld =
-            brw_builder(&s, block, inst).group(8, 0).exec_all();
+         const brw_builder ubld = brw_builder(inst).group(8, 0).exec_all();
 
          const brw_reg payload = ubld.vgrf(BRW_TYPE_UD);
          ubld.MOV(payload, offset_B);
@@ -2722,7 +2721,7 @@ brw_lower_uniform_pull_constant_loads(brw_shader &s)
          s.invalidate_analysis(BRW_DEPENDENCY_INSTRUCTIONS |
                                BRW_DEPENDENCY_VARIABLES);
       } else {
-         const brw_builder ubld = brw_builder(&s, block, inst).exec_all();
+         const brw_builder ubld = brw_builder(inst).exec_all();
          brw_reg header = brw_builder(&s, 8).exec_all().vgrf(BRW_TYPE_UD);
 
          ubld.group(8, 0).MOV(header,
@@ -2767,7 +2766,7 @@ brw_lower_send_descriptors(brw_shader &s)
           inst->opcode != SHADER_OPCODE_SEND_GATHER)
          continue;
 
-      const brw_builder ubld = brw_builder(&s, block, inst).exec_all().group(1, 0);
+      const brw_builder ubld = brw_builder(inst).exec_all().group(1, 0);
 
       /* Descriptor */
       const unsigned rlen = inst->dst.is_null() ? 0 : inst->size_written / REG_SIZE;
diff --git a/src/intel/compiler/brw_lower_pack.cpp b/src/intel/compiler/brw_lower_pack.cpp
index 9fd1a84e4e5..a6801ec3924 100644
--- a/src/intel/compiler/brw_lower_pack.cpp
+++ b/src/intel/compiler/brw_lower_pack.cpp
@@ -40,7 +40,7 @@ brw_lower_pack(brw_shader &s)
       assert(inst->saturate == false);
       brw_reg dst = inst->dst;
 
-      const brw_builder ibld(&s, block, inst);
+      const brw_builder ibld(inst);
       /* The lowering generates 2 instructions for what was previously 1. This
        * can trick the IR to believe we're doing partial writes, but the
        * register is actually fully written. Mark it as undef to help the IR
diff --git a/src/intel/compiler/brw_lower_regioning.cpp b/src/intel/compiler/brw_lower_regioning.cpp
index 6ccd2b9f266..2e76ffed5cb 100644
--- a/src/intel/compiler/brw_lower_regioning.cpp
+++ b/src/intel/compiler/brw_lower_regioning.cpp
@@ -475,7 +475,7 @@ brw_lower_src_modifiers(brw_shader &s, bblock_t *block, brw_inst *inst, unsigned
           MIN2(brw_type_size_bytes(inst->src[0].type), brw_type_size_bytes(inst->src[1].type)) >= 4 ||
           brw_type_size_bytes(inst->src[i].type) == get_exec_type_size(inst));
 
-   const brw_builder ibld(&s, block, inst);
+   const brw_builder ibld(inst);
    const brw_reg tmp = ibld.vgrf(get_exec_type(inst));
 
    lower_instruction(&s, block, ibld.MOV(tmp, inst->src[i]));
@@ -495,7 +495,7 @@ namespace {
    bool
    lower_dst_modifiers(brw_shader *v, bblock_t *block, brw_inst *inst)
    {
-      const brw_builder ibld(v, block, inst);
+      const brw_builder ibld(inst);
       const brw_reg_type type = get_exec_type(inst);
       /* Not strictly necessary, but if possible use a temporary with the same
        * channel alignment as the current destination in order to avoid
@@ -546,7 +546,7 @@ namespace {
    {
       assert(inst->components_read(i) == 1);
       const intel_device_info *devinfo = v->devinfo;
-      const brw_builder ibld(v, block, inst);
+      const brw_builder ibld(inst);
       const unsigned stride = required_src_byte_stride(devinfo, inst, i) /
                               brw_type_size_bytes(inst->src[i].type);
       assert(stride > 0);
@@ -614,7 +614,7 @@ namespace {
       assert(inst->opcode != BRW_OPCODE_MUL || !inst->dst.is_accumulator() ||
              brw_type_is_float(inst->dst.type));
 
-      const brw_builder ibld(v, block, inst);
+      const brw_builder ibld(inst);
       const unsigned stride = required_dst_byte_stride(inst) /
                               brw_type_size_bytes(inst->dst.type);
       assert(stride > 0);
@@ -685,7 +685,7 @@ namespace {
       const unsigned mask = has_invalid_exec_type(v->devinfo, inst);
       const brw_reg_type raw_type = required_exec_type(v->devinfo, inst);
       const unsigned n = get_exec_type_size(inst) / brw_type_size_bytes(raw_type);
-      const brw_builder ibld(v, block, inst);
+      const brw_builder ibld(inst);
 
       brw_reg tmp = ibld.vgrf(inst->dst.type, inst->dst.stride);
       ibld.UNDEF(tmp);
@@ -732,7 +732,7 @@ namespace {
    lower_src_conversion(brw_shader *v, bblock_t *block, brw_inst *inst)
    {
       const intel_device_info *devinfo = v->devinfo;
-      const brw_builder ibld = brw_builder(v, block, inst).scalar_group();
+      const brw_builder ibld = brw_builder(inst).scalar_group();
 
       /* We only handle scalar conversions from small types for now. */
       assert(is_uniform(inst->src[0]));
diff --git a/src/intel/compiler/brw_lower_scoreboard.cpp b/src/intel/compiler/brw_lower_scoreboard.cpp
index 04edd552906..ca5f7d8f48c 100644
--- a/src/intel/compiler/brw_lower_scoreboard.cpp
+++ b/src/intel/compiler/brw_lower_scoreboard.cpp
@@ -1321,8 +1321,7 @@ namespace {
                   /* Emit dependency into the SWSB of an extra SYNC
                    * instruction.
                    */
-                  const brw_builder ibld = brw_builder(shader, block, inst)
-                                           .exec_all().group(1, 0);
+                  const brw_builder ibld = brw_builder(inst).exec_all().group(1, 0);
                   brw_inst *sync = ibld.SYNC(TGL_SYNC_NOP);
                   sync->sched.sbid = dep.id;
                   sync->sched.mode = dep.unordered;
@@ -1344,7 +1343,7 @@ namespace {
                 * scenario with unordered dependencies should have been
                 * handled above.
                 */
-               const brw_builder ibld = brw_builder(shader, block, inst)
+               const brw_builder ibld = brw_builder(inst)
                                         .exec_all().group(1, 0);
                brw_inst *sync = ibld.SYNC(TGL_SYNC_NOP);
                sync->sched = ordered_dependency_swsb(deps[ip], jps[ip], true);
diff --git a/src/intel/compiler/brw_lower_subgroup_ops.cpp b/src/intel/compiler/brw_lower_subgroup_ops.cpp
index e8337f9d823..8a93dbc5ca5 100644
--- a/src/intel/compiler/brw_lower_subgroup_ops.cpp
+++ b/src/intel/compiler/brw_lower_subgroup_ops.cpp
@@ -251,7 +251,7 @@ brw_emit_scan(const brw_builder &bld, enum opcode opcode, const brw_reg &tmp,
 static bool
 brw_lower_reduce(brw_shader &s, bblock_t *block, brw_inst *inst)
 {
-   const brw_builder bld(&s, block, inst);
+   const brw_builder bld(inst);
 
    assert(inst->dst.type == inst->src[0].type);
    brw_reg dst = inst->dst;
@@ -303,7 +303,7 @@ brw_lower_reduce(brw_shader &s, bblock_t *block, brw_inst *inst)
 static bool
 brw_lower_scan(brw_shader &s, bblock_t *block, brw_inst *inst)
 {
-   const brw_builder bld(&s, block, inst);
+   const brw_builder bld(inst);
 
    assert(inst->dst.type == inst->src[0].type);
    brw_reg dst = inst->dst;
@@ -488,7 +488,7 @@ brw_lower_quad_vote_gfx20(const brw_builder &bld, enum opcode opcode, brw_reg ds
 static bool
 brw_lower_vote(brw_shader &s, bblock_t *block, brw_inst *inst)
 {
-   const brw_builder bld(&s, block, inst);
+   const brw_builder bld(inst);
 
    brw_reg dst = inst->dst;
    brw_reg src = inst->src[0];
@@ -518,7 +518,7 @@ brw_lower_vote(brw_shader &s, bblock_t *block, brw_inst *inst)
 static bool
 brw_lower_ballot(brw_shader &s, bblock_t *block, brw_inst *inst)
 {
-   const brw_builder bld(&s, block, inst);
+   const brw_builder bld(inst);
 
    brw_reg value = retype(inst->src[0], BRW_TYPE_UD);
    brw_reg dst = inst->dst;
@@ -548,7 +548,7 @@ brw_lower_ballot(brw_shader &s, bblock_t *block, brw_inst *inst)
 static bool
 brw_lower_quad_swap(brw_shader &s, bblock_t *block, brw_inst *inst)
 {
-   const brw_builder bld(&s, block, inst);
+   const brw_builder bld(inst);
 
    assert(inst->dst.type == inst->src[0].type);
    brw_reg dst = inst->dst;
@@ -604,7 +604,7 @@ brw_lower_quad_swap(brw_shader &s, bblock_t *block, brw_inst *inst)
 static bool
 brw_lower_read_from_live_channel(brw_shader &s, bblock_t *block, brw_inst *inst)
 {
-   const brw_builder bld(&s, block, inst);
+   const brw_builder bld(inst);
 
    assert(inst->sources == 1);
    assert(inst->dst.type == inst->src[0].type);
@@ -620,7 +620,7 @@ brw_lower_read_from_live_channel(brw_shader &s, bblock_t *block, brw_inst *inst)
 static bool
 brw_lower_read_from_channel(brw_shader &s, bblock_t *block, brw_inst *inst)
 {
-   const brw_builder bld(&s, block, inst);
+   const brw_builder bld(inst);
 
    assert(inst->sources == 2);
    assert(inst->dst.type == inst->src[0].type);
diff --git a/src/intel/compiler/brw_opt.cpp b/src/intel/compiler/brw_opt.cpp
index fd83d88aaf2..a09c4b2cc6a 100644
--- a/src/intel/compiler/brw_opt.cpp
+++ b/src/intel/compiler/brw_opt.cpp
@@ -351,7 +351,7 @@ brw_opt_split_sends(brw_shader &s)
       if (end <= mid)
          continue;
 
-      const brw_builder ibld(&s, block, lp);
+      const brw_builder ibld(lp);
       brw_inst *lp1 = ibld.LOAD_PAYLOAD(lp->dst, &lp->src[0], mid, lp->header_size);
       brw_inst *lp2 = ibld.LOAD_PAYLOAD(lp->dst, &lp->src[mid], end - mid, 0);
 
diff --git a/src/intel/compiler/brw_opt_txf_combiner.cpp b/src/intel/compiler/brw_opt_txf_combiner.cpp
index e0488520921..fab2c3e5e3e 100644
--- a/src/intel/compiler/brw_opt_txf_combiner.cpp
+++ b/src/intel/compiler/brw_opt_txf_combiner.cpp
@@ -209,7 +209,7 @@ brw_opt_combine_convergent_txf(brw_shader &s)
             if (!txf)
                break;
 
-            const brw_builder ibld = brw_builder(&s, block, txf);
+            const brw_builder ibld = brw_builder(txf);
 
             /* Replace each of the original TXFs with MOVs from our new one */
             const unsigned dest_comps = dest_comps_for_txf(s, txf);
diff --git a/src/intel/compiler/brw_opt_virtual_grfs.cpp b/src/intel/compiler/brw_opt_virtual_grfs.cpp
index 7c2931e97c7..942afc78232 100644
--- a/src/intel/compiler/brw_opt_virtual_grfs.cpp
+++ b/src/intel/compiler/brw_opt_virtual_grfs.cpp
@@ -143,7 +143,7 @@ brw_opt_split_virtual_grfs(brw_shader &s)
       if (inst->opcode == SHADER_OPCODE_UNDEF) {
          assert(inst->dst.file == VGRF);
          if (vgrf_has_split[inst->dst.nr]) {
-            const brw_builder ibld(&s, block, inst);
+            const brw_builder ibld(inst);
             assert(inst->size_written % REG_SIZE == 0);
             unsigned reg_offset = inst->dst.offset / REG_SIZE;
             unsigned size_written = 0;
diff --git a/src/intel/compiler/brw_reg_allocate.cpp b/src/intel/compiler/brw_reg_allocate.cpp
index 7fa00a068c2..7673b5219cf 100644
--- a/src/intel/compiler/brw_reg_allocate.cpp
+++ b/src/intel/compiler/brw_reg_allocate.cpp
@@ -1131,7 +1131,7 @@ brw_reg_alloc::spill_reg(unsigned spill_reg)
     */
    int ip = 0;
    foreach_block_and_inst (block, brw_inst, inst, fs->cfg) {
-      const brw_builder ibld = brw_builder(fs, block, inst);
+      const brw_builder ibld = brw_builder(inst);
       exec_node *before = inst->prev;
       exec_node *after = inst->next;
 
diff --git a/src/intel/compiler/brw_workaround.cpp b/src/intel/compiler/brw_workaround.cpp
index 98c98ed02ce..c3ef97c5026 100644
--- a/src/intel/compiler/brw_workaround.cpp
+++ b/src/intel/compiler/brw_workaround.cpp
@@ -28,8 +28,7 @@ brw_workaround_emit_dummy_mov_instruction(brw_shader &s)
       return false;
 
    /* Insert dummy mov as first instruction. */
-   const brw_builder ubld =
-      brw_builder(&s, s.cfg->first_block(), (brw_inst *)first_inst).exec_all().group(8, 0);
+   const brw_builder ubld = brw_builder(first_inst).exec_all().group(8, 0);
    ubld.MOV(ubld.null_reg_ud(), brw_imm_ud(0u));
 
    s.invalidate_analysis(BRW_DEPENDENCY_INSTRUCTIONS |
@@ -99,7 +98,7 @@ brw_workaround_memory_fence_before_eot(brw_shader &s)
       if (!has_ugm_write_or_atomic)
          break;
 
-      const brw_builder ibld(&s, block, inst);
+      const brw_builder ibld(inst);
       const brw_builder ubld = ibld.exec_all().group(1, 0);
 
       brw_reg dst = ubld.vgrf(BRW_TYPE_UD);
@@ -227,7 +226,7 @@ brw_workaround_nomask_control_flow(brw_shader &s)
                 * instruction), in order to avoid getting a right-shifted
                 * value.
                 */
-               const brw_builder ubld = brw_builder(&s, block, inst)
+               const brw_builder ubld = brw_builder(inst)
                                        .exec_all().group(s.dispatch_width, 0);
                const brw_reg flag = retype(brw_flag_reg(0, 0),
                                           BRW_TYPE_UD);
@@ -343,7 +342,7 @@ brw_workaround_source_arf_before_eot(brw_shader &s)
           */
          assert(++eot_count == 1);
 
-         const brw_builder ibld(&s, block, inst);
+         const brw_builder ibld(inst);
          const brw_builder ubld = ibld.exec_all().group(1, 0);
 
          if (flags_unread & 0x0f)