From 31ec1ecc12208aa6181c9f7e38b3b2e5488d5df1 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Thu, 5 May 2022 13:23:06 +0200 Subject: [PATCH] radv: update VRS registers on GFX11 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Samuel Pitoiset Reviewed-by: Timur Kristóf Part-of: --- src/amd/vulkan/radv_pipeline.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 2857b0ae5ed..40c1dbd1b07 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -6432,10 +6432,16 @@ gfx103_pipeline_generate_vrs_state(struct radeon_cmdbuf *ctx_cs, mode = ps->info.ps.can_discard ? V_028064_VRS_COMB_MODE_MIN : V_028064_VRS_COMB_MODE_PASSTHRU; } - radeon_set_context_reg(ctx_cs, R_028064_DB_VRS_OVERRIDE_CNTL, - S_028064_VRS_OVERRIDE_RATE_COMBINER_MODE(mode) | - S_028064_VRS_OVERRIDE_RATE_X(rate_x) | - S_028064_VRS_OVERRIDE_RATE_Y(rate_y)); + if (pipeline->device->physical_device->rad_info.gfx_level >= GFX11) { + radeon_set_context_reg(ctx_cs, R_0283D0_PA_SC_VRS_OVERRIDE_CNTL, + S_0283D0_VRS_OVERRIDE_RATE_COMBINER_MODE(mode) | + S_0283D0_VRS_RATE((rate_x << 2) | rate_y)); + } else { + radeon_set_context_reg(ctx_cs, R_028064_DB_VRS_OVERRIDE_CNTL, + S_028064_VRS_OVERRIDE_RATE_COMBINER_MODE(mode) | + S_028064_VRS_OVERRIDE_RATE_X(rate_x) | + S_028064_VRS_OVERRIDE_RATE_Y(rate_y)); + } } static void