From 31b9e509b0b1022951722901ce1a352fef3b4fc2 Mon Sep 17 00:00:00 2001 From: Patrick Lerda Date: Fri, 4 Jul 2025 14:52:59 +0200 Subject: [PATCH] r600: refactor step 3 - split r600_framebuffer Signed-off-by: Patrick Lerda Part-of: --- src/gallium/drivers/r600/evergreen_state.c | 58 ++++++++++---------- src/gallium/drivers/r600/r600_blit.c | 2 +- src/gallium/drivers/r600/r600_hw_context.c | 2 +- src/gallium/drivers/r600/r600_pipe.h | 6 +- src/gallium/drivers/r600/r600_state.c | 48 ++++++++-------- src/gallium/drivers/r600/r600_state_common.c | 32 +++++------ 6 files changed, 76 insertions(+), 72 deletions(-) diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c index cba26848dab..526ab00aa5f 100644 --- a/src/gallium/drivers/r600/evergreen_state.c +++ b/src/gallium/drivers/r600/evergreen_state.c @@ -1475,11 +1475,11 @@ static void evergreen_set_framebuffer_state(struct pipe_context *ctx, util_copy_framebuffer_state(&rctx->framebuffer.state, state); /* Colorbuffers. */ - rctx->framebuffer.export_16bpc = state->nr_cbufs != 0; - rctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0].texture && + rctx->cb_state.export_16bpc = state->nr_cbufs != 0; + rctx->cb_state.cb0_is_integer = state->nr_cbufs && state->cbufs[0].texture && util_format_is_pure_integer(state->cbufs[0].format); - rctx->framebuffer.compressed_cb_mask = 0; - rctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state); + rctx->cb_state.compressed_cb_mask = 0; + rctx->cb_state.nr_samples = util_framebuffer_get_num_samples(state); for (i = 0; i < state->nr_cbufs; i++) { surf = (struct r600_surface*)rctx->framebuffer.fb_cbufs[i]; @@ -1497,11 +1497,11 @@ static void evergreen_set_framebuffer_state(struct pipe_context *ctx, } if (!surf->export_16bpc) { - rctx->framebuffer.export_16bpc = false; + rctx->cb_state.export_16bpc = false; } if (rtex->fmask.size) { - rctx->framebuffer.compressed_cb_mask |= 1 << i; + rctx->cb_state.compressed_cb_mask |= 1 << i; } } @@ -1565,7 +1565,7 @@ static void evergreen_set_framebuffer_state(struct pipe_context *ctx, r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom); } - log_samples = util_logbase2(rctx->framebuffer.nr_samples); + log_samples = util_logbase2(rctx->cb_state.nr_samples); /* This is for Cayman to program SAMPLE_RATE, and for RV770 to fix a hw bug. */ if ((rctx->b.gfx_level == CAYMAN || rctx->b.family == CHIP_RV770) && @@ -1576,31 +1576,31 @@ static void evergreen_set_framebuffer_state(struct pipe_context *ctx, /* Calculate the CS size. */ - rctx->framebuffer.atom.num_dw = 4; /* SCISSOR */ + rctx->cb_state.atom.num_dw = 4; /* SCISSOR */ /* MSAA. */ if (rctx->b.gfx_level == EVERGREEN) - rctx->framebuffer.atom.num_dw += 17; /* Evergreen */ + rctx->cb_state.atom.num_dw += 17; /* Evergreen */ else - rctx->framebuffer.atom.num_dw += 28; /* Cayman */ + rctx->cb_state.atom.num_dw += 28; /* Cayman */ /* Colorbuffers. */ - rctx->framebuffer.atom.num_dw += state->nr_cbufs * 23; - rctx->framebuffer.atom.num_dw += state->nr_cbufs * 2; - rctx->framebuffer.atom.num_dw += (12 - state->nr_cbufs) * 3; + rctx->cb_state.atom.num_dw += state->nr_cbufs * 23; + rctx->cb_state.atom.num_dw += state->nr_cbufs * 2; + rctx->cb_state.atom.num_dw += (12 - state->nr_cbufs) * 3; /* ZS buffer. */ if (state->zsbuf.texture) { - rctx->framebuffer.atom.num_dw += 24; - rctx->framebuffer.atom.num_dw += 2; + rctx->cb_state.atom.num_dw += 24; + rctx->cb_state.atom.num_dw += 2; } else { - rctx->framebuffer.atom.num_dw += 4; + rctx->cb_state.atom.num_dw += 4; } - r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom); + r600_mark_atom_dirty(rctx, &rctx->cb_state.atom); r600_set_sample_locations_constant_buffer(rctx); - rctx->framebuffer.do_update_surf_dirtiness = true; + rctx->cb_state.do_update_surf_dirtiness = true; } static void evergreen_set_min_samples(struct pipe_context *ctx, unsigned min_samples) @@ -1611,8 +1611,8 @@ static void evergreen_set_min_samples(struct pipe_context *ctx, unsigned min_sam return; rctx->ps_iter_samples = min_samples; - if (rctx->framebuffer.nr_samples > 1) { - r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom); + if (rctx->cb_state.nr_samples > 1) { + r600_mark_atom_dirty(rctx, &rctx->cb_state.atom); } } @@ -2015,7 +2015,7 @@ static void evergreen_emit_framebuffer_state(struct r600_context *rctx, struct r radeon_emit(cs, reloc); } /* set CB_COLOR1_INFO for possible dual-src blending */ - if (rctx->framebuffer.dual_src_blend && i == 1 && state->cbufs[0].texture) { + if (rctx->cb_state.dual_src_blend && i == 1 && state->cbufs[0].texture) { radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C, cb->cb_color_info | tex->cb_color_info); i++; @@ -2075,9 +2075,9 @@ static void evergreen_emit_framebuffer_state(struct r600_context *rctx, struct r radeon_emit(cs, br); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */ if (rctx->b.gfx_level == EVERGREEN) { - evergreen_emit_msaa_state(rctx, rctx->framebuffer.nr_samples, rctx->ps_iter_samples); + evergreen_emit_msaa_state(rctx, rctx->cb_state.nr_samples, rctx->ps_iter_samples); } else { - cayman_emit_msaa_state(cs, rctx->framebuffer.nr_samples, + cayman_emit_msaa_state(cs, rctx->cb_state.nr_samples, rctx->ps_iter_samples, 0); } } @@ -3707,7 +3707,7 @@ void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader */ bool sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0; bool flatshade = rctx->rasterizer ? rctx->rasterizer->flatshade : 0; - bool msaa = rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0; + bool msaa = rctx->cb_state.nr_samples > 1 && rctx->ps_iter_samples > 0; if (!cb->buf) { r600_init_command_buffer(cb, 64); @@ -4099,14 +4099,14 @@ void evergreen_update_db_shader_control(struct r600_context * rctx) return; } - dual_export = rctx->framebuffer.export_16bpc && + dual_export = rctx->cb_state.export_16bpc && !rctx->ps_shader->current->ps_depth_export; db_shader_control = rctx->ps_shader->current->db_shader_control | S_02880C_DUAL_EXPORT_ENABLE(dual_export) | S_02880C_DB_SOURCE_FORMAT(dual_export ? V_02880C_EXPORT_DB_TWO : V_02880C_EXPORT_DB_FULL) | - S_02880C_ALPHA_TO_MASK_DISABLE(rctx->framebuffer.cb0_is_integer); + S_02880C_ALPHA_TO_MASK_DISABLE(rctx->cb_state.cb0_is_integer); /* When alpha test is enabled we can't trust the hw to make the proper * decision on the order in which ztest should be run related to fragment @@ -4515,7 +4515,7 @@ static void evergreen_set_shader_buffers(struct pipe_context *ctx, istate->atom.num_dw = util_bitcount(istate->enabled_mask) * 46; if (old_mask != istate->enabled_mask) - r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom); + r600_mark_atom_dirty(rctx, &rctx->cb_state.atom); /* construct the target mask */ if (rctx->cb_misc_state.buffer_rat_enabled_mask != istate->enabled_mask) { @@ -4730,7 +4730,7 @@ static void evergreen_set_shader_images(struct pipe_context *ctx, R600_CONTEXT_FLUSH_AND_INV_CB_META; if (old_mask != istate->enabled_mask) - r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom); + r600_mark_atom_dirty(rctx, &rctx->cb_state.atom); if (rctx->cb_misc_state.image_rat_enabled_mask != istate->enabled_mask) { rctx->cb_misc_state.image_rat_enabled_mask = istate->enabled_mask; @@ -4816,7 +4816,7 @@ void evergreen_init_state_functions(struct r600_context *rctx) r600_init_atom(rctx, &rctx->config_state.atom, id++, evergreen_emit_config_state, 11); rctx->config_state.dyn_gpr_enabled = true; } - r600_init_atom(rctx, &rctx->framebuffer.atom, id++, evergreen_emit_framebuffer_state, 0); + r600_init_atom(rctx, &rctx->cb_state.atom, id++, evergreen_emit_framebuffer_state, 0); r600_init_atom(rctx, &rctx->fragment_images.atom, id++, evergreen_emit_fragment_image_state, 0); r600_init_atom(rctx, &rctx->compute_images.atom, id++, evergreen_emit_compute_image_state, 0); r600_init_atom(rctx, &rctx->fragment_buffers.atom, id++, evergreen_emit_fragment_buffer_state, 0); diff --git a/src/gallium/drivers/r600/r600_blit.c b/src/gallium/drivers/r600/r600_blit.c index d715c584bbe..2c4374cd548 100644 --- a/src/gallium/drivers/r600/r600_blit.c +++ b/src/gallium/drivers/r600/r600_blit.c @@ -594,7 +594,7 @@ static void r600_clear(struct pipe_context *ctx, unsigned buffers, struct pipe_framebuffer_state *fb = &rctx->framebuffer.state; if (buffers & PIPE_CLEAR_COLOR && rctx->b.gfx_level >= EVERGREEN) { - evergreen_do_fast_color_clear(rctx, fb, &rctx->framebuffer.atom, + evergreen_do_fast_color_clear(rctx, fb, &rctx->cb_state.atom, &buffers, NULL, color); if (!buffers) return; /* all buffers have been fast cleared */ diff --git a/src/gallium/drivers/r600/r600_hw_context.c b/src/gallium/drivers/r600/r600_hw_context.c index ad22c98b729..d32f7f0cfc7 100644 --- a/src/gallium/drivers/r600/r600_hw_context.c +++ b/src/gallium/drivers/r600/r600_hw_context.c @@ -346,7 +346,7 @@ void r600_begin_new_cs(struct r600_context *ctx) r600_mark_atom_dirty(ctx, &ctx->clip_state.atom); r600_mark_atom_dirty(ctx, &ctx->db_misc_state.atom); r600_mark_atom_dirty(ctx, &ctx->db_state.atom); - r600_mark_atom_dirty(ctx, &ctx->framebuffer.atom); + r600_mark_atom_dirty(ctx, &ctx->cb_state.atom); if (ctx->b.gfx_level >= EVERGREEN) { r600_mark_atom_dirty(ctx, &ctx->fragment_images.atom); r600_mark_atom_dirty(ctx, &ctx->fragment_buffers.atom); diff --git a/src/gallium/drivers/r600/r600_pipe.h b/src/gallium/drivers/r600/r600_pipe.h index bfd58fc70d4..c0f6093199a 100644 --- a/src/gallium/drivers/r600/r600_pipe.h +++ b/src/gallium/drivers/r600/r600_pipe.h @@ -188,9 +188,12 @@ struct r600_cs_shader_state { }; struct r600_framebuffer { - struct r600_atom atom; PIPE_FB_SURFACES; //STOP USING THIS struct pipe_framebuffer_state state; +}; + +struct r600_cb_state { + struct r600_atom atom; unsigned compressed_cb_mask; unsigned nr_samples; bool export_16bpc; @@ -534,6 +537,7 @@ struct r600_context { struct r600_db_state db_state; struct r600_cso_state dsa_state; struct r600_framebuffer framebuffer; + struct r600_cb_state cb_state; struct r600_poly_offset_state poly_offset_state; struct r600_cso_state rasterizer_state; struct r600_sample_mask sample_mask; diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c index afc6f6022a1..c4bd3ea7f35 100644 --- a/src/gallium/drivers/r600/r600_state.c +++ b/src/gallium/drivers/r600/r600_state.c @@ -1098,21 +1098,21 @@ static void r600_set_framebuffer_state(struct pipe_context *ctx, util_framebuffer_init(ctx, state, rctx->framebuffer.fb_cbufs, &rctx->framebuffer.fb_zsbuf); util_copy_framebuffer_state(&rctx->framebuffer.state, state); - rctx->framebuffer.export_16bpc = state->nr_cbufs != 0; - rctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0].texture && + rctx->cb_state.export_16bpc = state->nr_cbufs != 0; + rctx->cb_state.cb0_is_integer = state->nr_cbufs && state->cbufs[0].texture && util_format_is_pure_integer(state->cbufs[0].format); - rctx->framebuffer.compressed_cb_mask = 0; - rctx->framebuffer.is_msaa_resolve = state->nr_cbufs == 2 && + rctx->cb_state.compressed_cb_mask = 0; + rctx->cb_state.is_msaa_resolve = state->nr_cbufs == 2 && state->cbufs[0].texture && state->cbufs[1].texture && state->cbufs[0].texture->nr_samples > 1 && state->cbufs[1].texture->nr_samples <= 1; - rctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state); + rctx->cb_state.nr_samples = util_framebuffer_get_num_samples(state); /* Colorbuffers. */ for (i = 0; i < state->nr_cbufs; i++) { /* The resolve buffer must have CMASK and FMASK to prevent hardlocks on R6xx. */ bool force_cmask_fmask = rctx->b.gfx_level == R600 && - rctx->framebuffer.is_msaa_resolve && + rctx->cb_state.is_msaa_resolve && i == 1; surf = (struct r600_surface*)rctx->framebuffer.fb_cbufs[i]; @@ -1133,11 +1133,11 @@ static void r600_set_framebuffer_state(struct pipe_context *ctx, } if (!surf->export_16bpc) { - rctx->framebuffer.export_16bpc = false; + rctx->cb_state.export_16bpc = false; } if (rtex->fmask.size) { - rctx->framebuffer.compressed_cb_mask |= 1 << i; + rctx->cb_state.compressed_cb_mask |= 1 << i; } } @@ -1196,26 +1196,26 @@ static void r600_set_framebuffer_state(struct pipe_context *ctx, } /* Calculate the CS size. */ - rctx->framebuffer.atom.num_dw = + rctx->cb_state.atom.num_dw = 10 /*COLOR_INFO*/ + 4 /*SCISSOR*/ + 3 /*SHADER_CONTROL*/ + 8 /*MSAA*/; if (rctx->framebuffer.state.nr_cbufs) { - rctx->framebuffer.atom.num_dw += 15 * rctx->framebuffer.state.nr_cbufs; - rctx->framebuffer.atom.num_dw += 3 * (2 + rctx->framebuffer.state.nr_cbufs); + rctx->cb_state.atom.num_dw += 15 * rctx->framebuffer.state.nr_cbufs; + rctx->cb_state.atom.num_dw += 3 * (2 + rctx->framebuffer.state.nr_cbufs); } if (rctx->framebuffer.state.zsbuf.texture) { - rctx->framebuffer.atom.num_dw += 16; + rctx->cb_state.atom.num_dw += 16; } else { - rctx->framebuffer.atom.num_dw += 3; + rctx->cb_state.atom.num_dw += 3; } if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770) { - rctx->framebuffer.atom.num_dw += 2; + rctx->cb_state.atom.num_dw += 2; } - r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom); + r600_mark_atom_dirty(rctx, &rctx->cb_state.atom); r600_set_sample_locations_constant_buffer(rctx); - rctx->framebuffer.do_update_surf_dirtiness = true; + rctx->cb_state.do_update_surf_dirtiness = true; } static const uint32_t sample_locs_2x[] = { @@ -1355,7 +1355,7 @@ static void r600_emit_framebuffer_state(struct r600_context *rctx, struct r600_a radeon_emit(cs, cb[i] ? cb[i]->cb_color_info : 0); } /* set CB_COLOR1_INFO for possible dual-src blending */ - if (rctx->framebuffer.dual_src_blend && i == 1 && cb[0]) { + if (rctx->cb_state.dual_src_blend && i == 1 && cb[0]) { radeon_emit(cs, cb[0]->cb_color_info); i++; } @@ -1477,7 +1477,7 @@ static void r600_emit_framebuffer_state(struct r600_context *rctx, struct r600_a radeon_emit(cs, S_028244_BR_X(state->width) | S_028244_BR_Y(state->height)); /* R_028208_PA_SC_WINDOW_SCISSOR_BR */ - if (rctx->framebuffer.is_msaa_resolve) { + if (rctx->cb_state.is_msaa_resolve) { radeon_set_context_reg(cs, R_0287A0_CB_SHADER_CONTROL, 1); } else { /* Always enable the first colorbuffer in CB_SHADER_CONTROL. This @@ -1487,7 +1487,7 @@ static void r600_emit_framebuffer_state(struct r600_context *rctx, struct r600_a (1ull << MAX2(nr_cbufs, 1)) - 1); } - r600_emit_msaa_state(rctx, rctx->framebuffer.nr_samples); + r600_emit_msaa_state(rctx, rctx->cb_state.nr_samples); } static void r600_set_min_samples(struct pipe_context *ctx, unsigned min_samples) @@ -1498,7 +1498,7 @@ static void r600_set_min_samples(struct pipe_context *ctx, unsigned min_samples) return; rctx->ps_iter_samples = min_samples; - if (rctx->framebuffer.nr_samples > 1) { + if (rctx->cb_state.nr_samples > 1) { r600_mark_atom_dirty(rctx, &rctx->rasterizer_state.atom); if (rctx->b.gfx_level == R600) r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom); @@ -1603,7 +1603,7 @@ static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom } else { db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE); } - if (rctx->b.gfx_level == R600 && rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0) { + if (rctx->b.gfx_level == R600 && rctx->cb_state.nr_samples > 1 && rctx->ps_iter_samples > 0) { /* sample shading and hyperz causes lockups on R6xx chips */ db_render_override |= S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE); } @@ -2462,7 +2462,7 @@ void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *sha */ bool sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0; bool flatshade = rctx->rasterizer ? rctx->rasterizer->flatshade : 0; - bool msaa = rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0; + bool msaa = rctx->cb_state.nr_samples > 1 && rctx->ps_iter_samples > 0; if (!cb->buf) { r600_init_command_buffer(cb, 64); @@ -2820,7 +2820,7 @@ void r600_update_db_shader_control(struct r600_context * rctx) return; } - dual_export = rctx->framebuffer.export_16bpc && + dual_export = rctx->cb_state.export_16bpc && !rctx->ps_shader->current->ps_depth_export; db_shader_control = rctx->ps_shader->current->db_shader_control | @@ -3069,7 +3069,7 @@ void r600_init_state_functions(struct r600_context *rctx) * !!! */ - r600_init_atom(rctx, &rctx->framebuffer.atom, id++, r600_emit_framebuffer_state, 0); + r600_init_atom(rctx, &rctx->cb_state.atom, id++, r600_emit_framebuffer_state, 0); /* shader const */ r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, r600_emit_vs_constant_buffers, 0); diff --git a/src/gallium/drivers/r600/r600_state_common.c b/src/gallium/drivers/r600/r600_state_common.c index 1c01f160c24..760fb2e6d33 100644 --- a/src/gallium/drivers/r600/r600_state_common.c +++ b/src/gallium/drivers/r600/r600_state_common.c @@ -113,7 +113,7 @@ static void r600_texture_barrier(struct pipe_context *ctx, unsigned flags) R600_CONTEXT_FLUSH_AND_INV_CB | R600_CONTEXT_FLUSH_AND_INV | R600_CONTEXT_WAIT_3D_IDLE; - rctx->framebuffer.do_update_surf_dirtiness = true; + rctx->cb_state.do_update_surf_dirtiness = true; } static unsigned r600_conv_pipe_prim(unsigned prim) @@ -202,9 +202,9 @@ static void r600_bind_blend_state_internal(struct r600_context *rctx, if (update_cb) { r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom); } - if (rctx->framebuffer.dual_src_blend != blend->dual_src_blend) { - rctx->framebuffer.dual_src_blend = blend->dual_src_blend; - r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom); + if (rctx->cb_state.dual_src_blend != blend->dual_src_blend) { + rctx->cb_state.dual_src_blend = blend->dual_src_blend; + r600_mark_atom_dirty(rctx, &rctx->cb_state.atom); } } @@ -822,7 +822,7 @@ static inline void r600_shader_selector_key(const struct pipe_context *ctx, key->ps.color_two_side = rctx->rasterizer && rctx->rasterizer->two_side; key->ps.alpha_to_one = rctx->alpha_to_one && rctx->rasterizer && rctx->rasterizer->multisample_enable && - !rctx->framebuffer.cb0_is_integer; + !rctx->cb_state.cb0_is_integer; key->ps.nr_cbufs = rctx->framebuffer.state.nr_cbufs; key->ps.apply_sample_id_mask = (rctx->ps_iter_samples > 1) || !rctx->rasterizer->multisample_enable; /* Dual-source blending only makes sense with nr_cbufs == 1. */ @@ -1541,12 +1541,12 @@ void r600_set_sample_locations_constant_buffer(struct r600_context *rctx) { struct pipe_context *ctx = &rctx->b.b; - assert(rctx->framebuffer.nr_samples < R600_UCP_SIZE); - assert(rctx->framebuffer.nr_samples <= ARRAY_SIZE(rctx->sample_positions)/4); + assert(rctx->cb_state.nr_samples < R600_UCP_SIZE); + assert(rctx->cb_state.nr_samples <= ARRAY_SIZE(rctx->sample_positions)/4); memset(rctx->sample_positions, 0, 4 * 4 * 16); - for (unsigned i = 0; i < rctx->framebuffer.nr_samples; i++) { - ctx->get_sample_position(ctx, rctx->framebuffer.nr_samples, i, &rctx->sample_positions[4*i]); + for (unsigned i = 0; i < rctx->cb_state.nr_samples; i++) { + ctx->get_sample_position(ctx, rctx->cb_state.nr_samples, i, &rctx->sample_positions[4*i]); /* Also fill in center-zeroed positions used for interpolateAtSample */ rctx->sample_positions[4*i + 2] = rctx->sample_positions[4*i + 0] - 0.5f; rctx->sample_positions[4*i + 3] = rctx->sample_positions[4*i + 1] - 0.5f; @@ -1955,7 +1955,7 @@ static bool r600_update_derived_state(struct r600_context *rctx) rctx->rasterizer->sprite_coord_enable != rctx->ps_shader->current->sprite_coord_enable || rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade)) { - bool msaa = rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0; + bool msaa = rctx->cb_state.nr_samples > 1 && rctx->ps_iter_samples > 0; if (unlikely(rctx->ps_shader && ((rctx->rasterizer->sprite_coord_enable != rctx->ps_shader->current->sprite_coord_enable) || (rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade) || @@ -2565,8 +2565,8 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info dirty_tex_counter = p_atomic_read(&rctx->b.screen->dirty_tex_counter); if (unlikely(dirty_tex_counter != rctx->b.last_dirty_tex_counter)) { rctx->b.last_dirty_tex_counter = dirty_tex_counter; - r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom); - rctx->framebuffer.do_update_surf_dirtiness = true; + r600_mark_atom_dirty(rctx, &rctx->cb_state.atom); + rctx->cb_state.do_update_surf_dirtiness = true; } if (rctx->gs_shader) { @@ -2996,7 +2996,7 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info if (rctx->trace_buf) eg_trace_emit(rctx); - if (rctx->framebuffer.do_update_surf_dirtiness) { + if (rctx->cb_state.do_update_surf_dirtiness) { /* Set the depth buffer as dirty. */ if (rctx->framebuffer.state.zsbuf.texture) { struct pipe_surface *surf = &rctx->framebuffer.state.zsbuf; @@ -3007,10 +3007,10 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info if (rtex->surface.has_stencil) rtex->stencil_dirty_level_mask |= 1 << surf->level; } - if (rctx->framebuffer.compressed_cb_mask) { + if (rctx->cb_state.compressed_cb_mask) { struct pipe_surface *surf; struct r600_texture *rtex; - unsigned mask = rctx->framebuffer.compressed_cb_mask; + unsigned mask = rctx->cb_state.compressed_cb_mask; do { unsigned i = u_bit_scan(&mask); @@ -3021,7 +3021,7 @@ static void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info } while (mask); } - rctx->framebuffer.do_update_surf_dirtiness = false; + rctx->cb_state.do_update_surf_dirtiness = false; } if (index_size && indexbuf != info->index.resource)