From 30e32c9c78c45e3f39f43bc0b3d8a235f10369f1 Mon Sep 17 00:00:00 2001
From: Rob Clark <rob.clark@oss.qualcomm.com>
Date: Thu, 18 Sep 2025 14:28:49 -0700
Subject: [PATCH] freedreno/registers: Rename some unknowns

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37727>
---
 src/freedreno/common/freedreno_dev_info.h     |  2 +-
 src/freedreno/common/freedreno_devices.py     | 66 +++++++++----------
 src/freedreno/registers/adreno/a6xx.xml       | 25 +++++--
 src/freedreno/tests/reference/crash.log       |  6 +-
 .../tests/reference/crash_prefetch.log        | 12 ++--
 ...exed.indirect_draw_count.triangle_list.log |  6 +-
 src/freedreno/tests/reference/fd-clouds.log   |  6 +-
 .../tests/reference/prefetch-test.log         |  8 +--
 src/freedreno/vulkan/tu_cmd_buffer.cc         |  4 +-
 .../drivers/freedreno/a6xx/fd6_emit.cc        |  2 +-
 10 files changed, 77 insertions(+), 60 deletions(-)

diff --git a/src/freedreno/common/freedreno_dev_info.h b/src/freedreno/common/freedreno_dev_info.h
index d168d1825e2..9c14c7bdd36 100644
--- a/src/freedreno/common/freedreno_dev_info.h
+++ b/src/freedreno/common/freedreno_dev_info.h
@@ -237,7 +237,7 @@ struct fd_dev_info {
          uint32_t RB_DBG_ECO_CNTL;
          uint32_t RB_DBG_ECO_CNTL_blit;
          uint32_t HLSQ_DBG_ECO_CNTL;
-         uint32_t RB_UNKNOWN_8E01;
+         uint32_t RB_RBP_CNTL;
          uint32_t VPC_DBG_ECO_CNTL;
          uint32_t UCHE_UNKNOWN_0E12;
 
diff --git a/src/freedreno/common/freedreno_devices.py b/src/freedreno/common/freedreno_devices.py
index a467ca9ee35..b7a8573db36 100644
--- a/src/freedreno/common/freedreno_devices.py
+++ b/src/freedreno/common/freedreno_devices.py
@@ -473,7 +473,7 @@ add_gpus([
             RB_DBG_ECO_CNTL = 0x04100000,
             RB_DBG_ECO_CNTL_blit = 0x04100000,
             HLSQ_DBG_ECO_CNTL = 0,
-            RB_UNKNOWN_8E01 = 0x00000001,
+            RB_RBP_CNTL = 0x00000001,
             VPC_DBG_ECO_CNTL = 0x0,
             UCHE_UNKNOWN_0E12 = 0x10000000,
         ),
@@ -507,7 +507,7 @@ add_gpus([
             RB_DBG_ECO_CNTL = 0x04100000,
             RB_DBG_ECO_CNTL_blit = 0x04100000,
             HLSQ_DBG_ECO_CNTL = 0x00080000,
-            RB_UNKNOWN_8E01 = 0x00000001,
+            RB_RBP_CNTL = 0x00000001,
             VPC_DBG_ECO_CNTL = 0x0,
             UCHE_UNKNOWN_0E12 = 0x00000001
         )
@@ -536,7 +536,7 @@ add_gpus([
             RB_DBG_ECO_CNTL = 0x04100000,
             RB_DBG_ECO_CNTL_blit = 0x04100000,
             HLSQ_DBG_ECO_CNTL = 0x0,
-            RB_UNKNOWN_8E01 = 0x0,
+            RB_RBP_CNTL = 0x0,
             VPC_DBG_ECO_CNTL = 0x02000000,
             UCHE_UNKNOWN_0E12 = 0x00000001
         )
@@ -567,7 +567,7 @@ add_gpus([
             RB_DBG_ECO_CNTL = 0x04100000,
             RB_DBG_ECO_CNTL_blit = 0x04100000,
             HLSQ_DBG_ECO_CNTL = 0x0,
-            RB_UNKNOWN_8E01 = 0x0,
+            RB_RBP_CNTL = 0x0,
             VPC_DBG_ECO_CNTL = 0x02000000,
             UCHE_UNKNOWN_0E12 = 0x00000001
         )
@@ -598,7 +598,7 @@ add_gpus([
             RB_DBG_ECO_CNTL = 0x04100000,
             RB_DBG_ECO_CNTL_blit = 0x05100000,
             HLSQ_DBG_ECO_CNTL = 0x00080000,
-            RB_UNKNOWN_8E01 = 0x00000001,
+            RB_RBP_CNTL = 0x00000001,
             VPC_DBG_ECO_CNTL = 0x0,
             UCHE_UNKNOWN_0E12 = 0x10000001
         )
@@ -629,7 +629,7 @@ add_gpus([
             RB_DBG_ECO_CNTL = 0x04100000,
             RB_DBG_ECO_CNTL_blit = 0x04100000,
             HLSQ_DBG_ECO_CNTL = 0x0,
-            RB_UNKNOWN_8E01 = 0x00000001,
+            RB_RBP_CNTL = 0x00000001,
             VPC_DBG_ECO_CNTL = 0x02000000,
             UCHE_UNKNOWN_0E12 = 0x00000001
         )
@@ -660,7 +660,7 @@ add_gpus([
             RB_DBG_ECO_CNTL = 0x04100000,
             RB_DBG_ECO_CNTL_blit = 0x04100000,
             HLSQ_DBG_ECO_CNTL = 0x0,
-            RB_UNKNOWN_8E01 = 0x00000001,
+            RB_RBP_CNTL = 0x00000001,
             VPC_DBG_ECO_CNTL = 0x02000000,
             UCHE_UNKNOWN_0E12 = 0x00000001
         )
@@ -691,7 +691,7 @@ add_gpus([
             RB_DBG_ECO_CNTL = 0x04100000,
             RB_DBG_ECO_CNTL_blit = 0x04100000,
             HLSQ_DBG_ECO_CNTL = 0x0,
-            RB_UNKNOWN_8E01 = 0x0,
+            RB_RBP_CNTL = 0x0,
             VPC_DBG_ECO_CNTL = 0x02000000,
             UCHE_UNKNOWN_0E12 = 0x00000001
         )
@@ -727,7 +727,7 @@ add_gpus([
             RB_DBG_ECO_CNTL = 0x04100000,
             RB_DBG_ECO_CNTL_blit = 0x04100000,
             HLSQ_DBG_ECO_CNTL = 0x0,
-            RB_UNKNOWN_8E01 = 0x0,
+            RB_RBP_CNTL = 0x0,
             VPC_DBG_ECO_CNTL = 0x02000000,
             UCHE_UNKNOWN_0E12 = 0x00000001
         )
@@ -757,7 +757,7 @@ add_gpus([
             RB_DBG_ECO_CNTL = 0x04100000,
             RB_DBG_ECO_CNTL_blit = 0x04100000,
             HLSQ_DBG_ECO_CNTL = 0x0,
-            RB_UNKNOWN_8E01 = 0x0,
+            RB_RBP_CNTL = 0x0,
             VPC_DBG_ECO_CNTL = 0x02000000,
             UCHE_UNKNOWN_0E12 = 0x00000001
         )
@@ -787,7 +787,7 @@ add_gpus([
             RB_DBG_ECO_CNTL = 0x04100000,
             RB_DBG_ECO_CNTL_blit = 0x04100000,
             HLSQ_DBG_ECO_CNTL = 0x0,
-            RB_UNKNOWN_8E01 = 0x0,
+            RB_RBP_CNTL = 0x0,
             VPC_DBG_ECO_CNTL = 0x02000000,
             UCHE_UNKNOWN_0E12 = 0x00000001
         )
@@ -818,7 +818,7 @@ add_gpus([
             RB_DBG_ECO_CNTL = 0x100000,
             RB_DBG_ECO_CNTL_blit = 0x00100000,  # ???
             HLSQ_DBG_ECO_CNTL = 0x0,
-            RB_UNKNOWN_8E01 = 0x0,
+            RB_RBP_CNTL = 0x0,
             VPC_DBG_ECO_CNTL = 0x2000400,
             UCHE_UNKNOWN_0E12 = 0x00000001
         ),
@@ -866,7 +866,7 @@ add_gpus([
             RB_DBG_ECO_CNTL = 0x100000,
             RB_DBG_ECO_CNTL_blit = 0x100000,
             HLSQ_DBG_ECO_CNTL = 0x02000000,
-            RB_UNKNOWN_8E01 = 0x1,
+            RB_RBP_CNTL = 0x1,
             VPC_DBG_ECO_CNTL = 0x0,
             UCHE_UNKNOWN_0E12 = 0x1,
         ),
@@ -984,7 +984,7 @@ a730_magic_regs = dict(
         SP_DBG_ECO_CNTL = 0x10000000,
         RB_DBG_ECO_CNTL = 0x00000000,
         RB_DBG_ECO_CNTL_blit = 0x00000000,  # is it even needed?
-        RB_UNKNOWN_8E01 = 0x0,
+        RB_RBP_CNTL = 0x0,
         VPC_DBG_ECO_CNTL = 0x02000000,
         UCHE_UNKNOWN_0E12 = 0x3200000,
 
@@ -1004,10 +1004,10 @@ a730_raw_magic_regs = [
         [A6XXRegs.REG_A6XX_PC_DBG_ECO_CNTL, 0x20080000],
         [A6XXRegs.REG_A7XX_PC_UNKNOWN_9E24, 0x21fc7f00],
         [A6XXRegs.REG_A7XX_VFD_DBG_ECO_CNTL, 0x00000000],
-        [A6XXRegs.REG_A7XX_SP_UNKNOWN_AE06, 0x00000000],
+        [A6XXRegs.REG_A7XX_SP_ISDB_CNTL, 0x00000000],
         [A6XXRegs.REG_A7XX_SP_UNKNOWN_AE6A, 0x00000000],
-        [A6XXRegs.REG_A7XX_SP_UNKNOWN_AE6B, 0x00000080],
-        [A6XXRegs.REG_A7XX_SP_UNKNOWN_AE73, 0x00000000],
+        [A6XXRegs.REG_A7XX_SP_HLSQ_TIMEOUT_THRESHOLD_DP, 0x00000080],
+        [A6XXRegs.REG_A7XX_SP_HLSQ_DBG_ECO_CNTL_1, 0x00000000],
         [A6XXRegs.REG_A7XX_SP_UNKNOWN_AB02, 0x00000000],
         [A6XXRegs.REG_A7XX_SP_UNKNOWN_AB01, 0x00000000],
         [A6XXRegs.REG_A7XX_SP_UNKNOWN_AB22, 0x00000000],
@@ -1039,7 +1039,7 @@ a740_magic_regs = dict(
         RB_DBG_ECO_CNTL = 0x00000000,
         RB_DBG_ECO_CNTL_blit = 0x00000000,  # is it even needed?
         # HLSQ_DBG_ECO_CNTL = 0x0,
-        RB_UNKNOWN_8E01 = 0x0,
+        RB_RBP_CNTL = 0x0,
         VPC_DBG_ECO_CNTL = 0x02000000,
         UCHE_UNKNOWN_0E12 = 0x00000000,
 
@@ -1059,10 +1059,10 @@ a740_raw_magic_regs = [
         [A6XXRegs.REG_A6XX_PC_DBG_ECO_CNTL, 0x00100000],
         [A6XXRegs.REG_A7XX_PC_UNKNOWN_9E24, 0x21585600],
         [A6XXRegs.REG_A7XX_VFD_DBG_ECO_CNTL, 0x00008000],
-        [A6XXRegs.REG_A7XX_SP_UNKNOWN_AE06, 0x00000000],
+        [A6XXRegs.REG_A7XX_SP_ISDB_CNTL, 0x00000000],
         [A6XXRegs.REG_A7XX_SP_UNKNOWN_AE6A, 0x00000000],
-        [A6XXRegs.REG_A7XX_SP_UNKNOWN_AE6B, 0x00000080],
-        [A6XXRegs.REG_A7XX_SP_UNKNOWN_AE73, 0x00000000],
+        [A6XXRegs.REG_A7XX_SP_HLSQ_TIMEOUT_THRESHOLD_DP, 0x00000080],
+        [A6XXRegs.REG_A7XX_SP_HLSQ_DBG_ECO_CNTL_1, 0x00000000],
         [A6XXRegs.REG_A7XX_SP_UNKNOWN_AB02, 0x00000000],
         [A6XXRegs.REG_A7XX_SP_UNKNOWN_AB01, 0x00000000],
         [A6XXRegs.REG_A7XX_SP_UNKNOWN_AB22, 0x00000000],
@@ -1141,7 +1141,7 @@ add_gpus([
             SP_DBG_ECO_CNTL = 0x10000000,
             RB_DBG_ECO_CNTL = 0x00000001,
             RB_DBG_ECO_CNTL_blit = 0x00000001,  # is it even needed?
-            RB_UNKNOWN_8E01 = 0x0,
+            RB_RBP_CNTL = 0x0,
             VPC_DBG_ECO_CNTL = 0x02000000,
             UCHE_UNKNOWN_0E12 = 0x00000000,
 
@@ -1160,10 +1160,10 @@ add_gpus([
             [A6XXRegs.REG_A6XX_PC_DBG_ECO_CNTL, 0x00100000],
             [A6XXRegs.REG_A7XX_PC_UNKNOWN_9E24, 0x01585600],
             [A6XXRegs.REG_A7XX_VFD_DBG_ECO_CNTL, 0x00008000],
-            [A6XXRegs.REG_A7XX_SP_UNKNOWN_AE06, 0x00000000],
+            [A6XXRegs.REG_A7XX_SP_ISDB_CNTL, 0x00000000],
             [A6XXRegs.REG_A7XX_SP_UNKNOWN_AE6A, 0x00000000],
-            [A6XXRegs.REG_A7XX_SP_UNKNOWN_AE6B, 0x00000080],
-            [A6XXRegs.REG_A7XX_SP_UNKNOWN_AE73, 0x00000000],
+            [A6XXRegs.REG_A7XX_SP_HLSQ_TIMEOUT_THRESHOLD_DP, 0x00000080],
+            [A6XXRegs.REG_A7XX_SP_HLSQ_DBG_ECO_CNTL_1, 0x00000000],
             [A6XXRegs.REG_A7XX_SP_UNKNOWN_AB02, 0x00000000],
             [A6XXRegs.REG_A7XX_SP_UNKNOWN_AB01, 0x00000000],
             [A6XXRegs.REG_A7XX_SP_UNKNOWN_AB22, 0x00000000],
@@ -1232,10 +1232,10 @@ add_gpus([
             [A6XXRegs.REG_A6XX_PC_DBG_ECO_CNTL, 0x00100000],
             [A6XXRegs.REG_A7XX_PC_UNKNOWN_9E24, 0x21585600],
             [A6XXRegs.REG_A7XX_VFD_DBG_ECO_CNTL, 0x00008000],
-            [A6XXRegs.REG_A7XX_SP_UNKNOWN_AE06, 0x00000000],
+            [A6XXRegs.REG_A7XX_SP_ISDB_CNTL, 0x00000000],
             [A6XXRegs.REG_A7XX_SP_UNKNOWN_AE6A, 0x00000000],
-            [A6XXRegs.REG_A7XX_SP_UNKNOWN_AE6B, 0x00000080],
-            [A6XXRegs.REG_A7XX_SP_UNKNOWN_AE73, 0x00000000],
+            [A6XXRegs.REG_A7XX_SP_HLSQ_TIMEOUT_THRESHOLD_DP, 0x00000080],
+            [A6XXRegs.REG_A7XX_SP_HLSQ_DBG_ECO_CNTL_1, 0x00000000],
             [A6XXRegs.REG_A7XX_SP_UNKNOWN_AB02, 0x00000000],
             [A6XXRegs.REG_A7XX_SP_UNKNOWN_AB01, 0x00000000],
             [A6XXRegs.REG_A7XX_SP_UNKNOWN_AB22, 0x00000000],
@@ -1281,7 +1281,7 @@ add_gpus([
             RB_DBG_ECO_CNTL = 0x00000001,
             RB_DBG_ECO_CNTL_blit = 0x00000000,  # is it even needed?
             # HLSQ_DBG_ECO_CNTL = 0x0,
-            RB_UNKNOWN_8E01 = 0x0,
+            RB_RBP_CNTL = 0x0,
             VPC_DBG_ECO_CNTL = 0x02000000,
             UCHE_UNKNOWN_0E12 = 0x00000000,
 
@@ -1312,7 +1312,7 @@ add_gpus([
             SP_DBG_ECO_CNTL = 0x10000000,
             RB_DBG_ECO_CNTL = 0x00000001,
             RB_DBG_ECO_CNTL_blit = 0x00000001,
-            RB_UNKNOWN_8E01 = 0x0,
+            RB_RBP_CNTL = 0x0,
             VPC_DBG_ECO_CNTL = 0x02000000,
             UCHE_UNKNOWN_0E12 = 0x40000000,
 
@@ -1329,10 +1329,10 @@ add_gpus([
             [A6XXRegs.REG_A6XX_PC_DBG_ECO_CNTL, 0x00100000],
             [A6XXRegs.REG_A7XX_PC_UNKNOWN_9E24, 0x01585600],
             [A6XXRegs.REG_A7XX_VFD_DBG_ECO_CNTL, 0x00008000],
-            [A6XXRegs.REG_A7XX_SP_UNKNOWN_AE06, 0x00000000],
+            [A6XXRegs.REG_A7XX_SP_ISDB_CNTL, 0x00000000],
             [A6XXRegs.REG_A7XX_SP_UNKNOWN_AE6A, 0x00000000],
-            [A6XXRegs.REG_A7XX_SP_UNKNOWN_AE6B, 0x00000080],
-            [A6XXRegs.REG_A7XX_SP_UNKNOWN_AE73, 0x00000000],
+            [A6XXRegs.REG_A7XX_SP_HLSQ_TIMEOUT_THRESHOLD_DP, 0x00000080],
+            [A6XXRegs.REG_A7XX_SP_HLSQ_DBG_ECO_CNTL_1, 0x00000000],
             [A6XXRegs.REG_A7XX_SP_UNKNOWN_AB02, 0x00000000],
             [A6XXRegs.REG_A7XX_SP_UNKNOWN_AB01, 0x00000000],
             [A6XXRegs.REG_A7XX_SP_UNKNOWN_AB22, 0x00000000],
diff --git a/src/freedreno/registers/adreno/a6xx.xml b/src/freedreno/registers/adreno/a6xx.xml
index 4e212ab08e9..7ff207319be 100644
--- a/src/freedreno/registers/adreno/a6xx.xml
+++ b/src/freedreno/registers/adreno/a6xx.xml
@@ -1928,7 +1928,7 @@ by a particular renderpass/blit.
 	<!-- 0x8c35-0x8dff invalid -->
 
 	<!-- always 0x1 ? either doesn't exist for a650 or write-only: -->
-	<reg32 offset="0x8e01" name="RB_UNKNOWN_8E01" usage="cmd"/>
+	<reg32 offset="0x8e01" name="RB_RBP_CNTL" usage="cmd"/>
 	<!-- 0x8e00-0x8e03 invalid -->
 	<reg32 offset="0x8e04" name="RB_DBG_ECO_CNTL" usage="cmd"/> <!-- TODO: valid mask 0xfffffeff -->
 	<reg32 offset="0x8e05" name="RB_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode"/>
@@ -2437,6 +2437,8 @@ by a particular renderpass/blit.
 	<reg64 offset="0x9e12" name="PC_PVIS_STREAM_BIN_BASE" type="waddress" align="32" variants="A6XX-A7XX"/>
 	<reg64 offset="0x9e14" name="PC_DVIS_STREAM_BIN_BASE" type="waddress" align="32" variants="A6XX-A7XX"/>
 
+	<reg32 offset="0x9e0a" name="PC_AUTO_VERTEX_STRIDE"/>
+
 	<bitset name="a6xx_pc_drawcall_cntl_override" inline="yes">
 		<doc>Written by CP_SET_VISIBILITY_OVERRIDE handler</doc>
 		<bitfield name="OVERRIDE" pos="0" type="boolean"/>
@@ -3251,10 +3253,12 @@ by a particular renderpass/blit.
 		<bitfield name="F16_NO_INF" pos="3" type="boolean"/>
 	</reg32>
 
-	<reg32 offset="0xae06" name="SP_UNKNOWN_AE06" variants="A7XX-" usage="init"/>
+	<reg32 offset="0xae06" name="SP_ISDB_CNTL" variants="A7XX-" usage="init"/>
+	<reg32 offset="0xae07" name="SP_PERFCTR_CNTL"/>
 	<reg32 offset="0xae08" name="SP_CHICKEN_BITS_1" variants="A7XX-" usage="init"/>
 	<reg32 offset="0xae09" name="SP_CHICKEN_BITS_2" variants="A7XX-" usage="init"/>
 	<reg32 offset="0xae0a" name="SP_CHICKEN_BITS_3" variants="A7XX-" usage="init"/>
+	<reg32 offset="0xae0c" name="SP_STATUS"/>
 
 	<reg32 offset="0xae0f" name="SP_PERFCTR_SHADER_MASK" usage="init">
 		<!-- some perfcntrs are affected by a per-stage enable bit
@@ -3270,7 +3274,7 @@ by a particular renderpass/blit.
 	<array offset="0xae10" name="SP_PERFCTR_SP_SEL" stride="1" length="24"/>
 	<array offset="0xae60" name="SP_PERFCTR_HLSQ_SEL" stride="1" length="6" variants="A7XX-"/>
 	<reg32 offset="0xae6a" name="SP_UNKNOWN_AE6A" variants="A7XX-" usage="init"/>
-	<reg32 offset="0xae6b" name="SP_UNKNOWN_AE6B" variants="A7XX-" usage="init"/>
+	<reg32 offset="0xae6b" name="SP_HLSQ_TIMEOUT_THRESHOLD_DP" variants="A7XX-" usage="init"/>
 	<reg32 offset="0xae6c" name="SP_HLSQ_DBG_ECO_CNTL" variants="A7XX-" usage="init"/>
 	<reg32 offset="0xae6d" name="SP_READ_SEL" variants="A7XX-">
 		<bitfield name="LOCATION" low="18" high="20" type="a7xx_state_location"/>
@@ -3280,12 +3284,25 @@ by a particular renderpass/blit.
 		<bitfield name="SPTP" low="0" high="3"/>
 	</reg32>
 	<reg32 offset="0xae71" name="SP_DBG_CNTL" variants="A7XX-"/>
-	<reg32 offset="0xae73" name="SP_UNKNOWN_AE73" variants="A7XX-" usage="init"/>
+	<reg32 offset="0xae73" name="SP_HLSQ_DBG_ECO_CNTL_1" variants="A7XX-"/>
+	<reg32 offset="0xae74" name="SP_HLSQ_DBG_ECO_CNTL_2" variants="A7XX-"/>
 	<array offset="0xae80" name="SP_PERFCTR_SP_SEL" stride="1" length="36" variants="A7XX-"/>
 	<!-- TODO: there are 4 more percntr select registers (0xae28-0xae2b) -->
 	<!-- TODO: there are a few unknown registers in the 0xae30-0xae52 range -->
 	<reg32 offset="0xae52" name="SP_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE"/>
 
+	<reg32 offset="0xae30" name="SP_ISDB_BATCH_COUNT" variants="A7XX-"/>
+	<reg32 offset="0xae31" name="SP_ISDB_BATCH_COUNT_INCR_EN" variants="A7XX-"/>
+	<reg32 offset="0xae32" name="SP_ISDB_BATCH_COUNT_SHADERS" variants="A7XX-"/>
+	<reg32 offset="0xae35" name="SP_ISDB_DEBUG_CONFIG" variants="A7XX-"/>
+
+	<reg32 offset="0xae3a" name="SP_SELF_THROTTLE_CONTROL" variants="A7XX-"/>
+	<reg32 offset="0xae3b" name="SP_DISPATCH_CNTL" variants="A7XX-"/>
+	<reg64 offset="0xae3c" name="SP_SW_DEBUG_ADDR" variants="A7XX-"/>
+	<reg64 offset="0xae3e" name="SP_ISDB_DEBUG_ADDR" variants="A7XX-"/>
+
+	<array offset="0xaec0" name="SP_PERFCTR_HLSQ_SEL_2_0" stride="1" length="6" variants="A7XX-"/>
+
 	<!--
 	The downstream kernel calls the debug cluster of registers
 	"a6xx_sp_ps_tp_cluster" but this actually specifies the border
diff --git a/src/freedreno/tests/reference/crash.log b/src/freedreno/tests/reference/crash.log
index 41c04f88dcc..4bd64582e84 100644
--- a/src/freedreno/tests/reference/crash.log
+++ b/src/freedreno/tests/reference/crash.log
@@ -1095,7 +1095,7 @@ registers:
 	00000000	PC_DMA_OFFSET: 0
 	00000000	PC_DMA_SIZE: 0
 	00000000	PC_TESS_BASE: 0
-	00000001	0x9e0a: 00000001
+	00000001	PC_AUTO_VERTEX_STRIDE: 0x1
 	00004080	PC_DRAWCALL_CNTL: { PRIM_TYPE = DI_PT_NONE | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = IGNORE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_8_BIT | PATCH_TYPE = TESS_QUADS | 0x4000 }
 	00000000	PC_DRAWCALL_INSTANCE_NUM: 0
 	00000003	PC_DRAWCALL_SIZE: 3
@@ -1546,7 +1546,7 @@ registers:
 	00000000	RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE: FALSE
 	0006d000	RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ADDR: 0x6d000
 	00000000	0x8e52: 00000000
-	00000000	RB_UNKNOWN_8E01: 0
+	00000000	RB_RBP_CNTL: 0
 	00000300	0x8e0c: 00000300
 	00000000	RB_RB_SUB_BLOCK_SEL_CNTL_HOST: 0
 	00000000	0x8e3c: 00000000
@@ -1594,7 +1594,7 @@ registers:
 	deadbeef	SP_NC_MODE_CNTL: 0xdeadbeef
 	deadbeef	SP_CHICKEN_BITS: 0xdeadbeef
 	00000004	SP_NC_MODE_CNTL_2: { 0x4 }
-	deadbeef	0xae0c: deadbeef
+	deadbeef	SP_STATUS: 0xdeadbeef
 	deadbeef	SP_PERFCTR_SHADER_MASK: { VS | HS | DS | GS | CS | 0xdeadbec0 }
 	00000000	SP_PERFCTR_SP_SEL[0]+0: 00000000
 	00000000	SP_PERFCTR_SP_SEL[0x1]+0: 00000000
diff --git a/src/freedreno/tests/reference/crash_prefetch.log b/src/freedreno/tests/reference/crash_prefetch.log
index 213e827455f..d125ae4685b 100644
--- a/src/freedreno/tests/reference/crash_prefetch.log
+++ b/src/freedreno/tests/reference/crash_prefetch.log
@@ -1310,7 +1310,7 @@ registers:
 	00000000	PC_DMA_OFFSET: 0
 	00000000	PC_DMA_SIZE: 0
 	00000000	PC_TESS_BASE: 0
-	00000001	0x9e0a: 00000001
+	00000001	PC_AUTO_VERTEX_STRIDE: 0x1
 	00000d84	PC_DRAWCALL_CNTL: { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = USE_VISIBILITY | INDEX_SIZE = 0x3 | PATCH_TYPE = TESS_QUADS }
 	00000001	PC_DRAWCALL_INSTANCE_NUM: 1
 	00000006	PC_DRAWCALL_SIZE: 6
@@ -1761,7 +1761,7 @@ registers:
 	00000000	RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE: FALSE
 	00000000	RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ADDR: 0
 	00000000	0x8e52: 00000000
-	00000001	RB_UNKNOWN_8E01: 0x1
+	00000001	RB_RBP_CNTL: 0x1
 	00010101	0x8e0c: 00010101
 	00000000	RB_RB_SUB_BLOCK_SEL_CNTL_HOST: 0
 	00000000	0x8e3c: 00000000
@@ -1807,7 +1807,7 @@ registers:
 	deadbeef	SP_NC_MODE_CNTL: 0xdeadbeef
 	deadbeef	SP_CHICKEN_BITS: 0xdeadbeef
 	00000002	SP_NC_MODE_CNTL_2: { 0x2 }
-	deadbeef	0xae0c: deadbeef
+	deadbeef	SP_STATUS: 0xdeadbeef
 	deadbeef	SP_PERFCTR_SHADER_MASK: { VS | HS | DS | GS | CS | 0xdeadbec0 }
 	00000000	SP_PERFCTR_SP_SEL[0]+0: 00000000
 	00000000	SP_PERFCTR_SP_SEL[0x1]+0: 00000000
@@ -1961,7 +1961,7 @@ got cmdszdw=38
 !+	3f800000			RB_A2D_CLEAR_COLOR_DW1: 0x3f800000
 !+	3f800000			RB_A2D_CLEAR_COLOR_DW2: 0x3f800000
  +	00000000			RB_A2D_CLEAR_COLOR_DW3: 0
-!+	00000001			RB_UNKNOWN_8E01: 0x1
+!+	00000001			RB_RBP_CNTL: 0x1
 !+	00100000			RB_DBG_ECO_CNTL: 0x100000
 !+	08000000			RB_CCU_CNTL: { DEPTH_OFFSET_HI = 0 | COLOR_OFFSET_HI = 0 | DEPTH_CACHE_SIZE = CCU_CACHE_SIZE_FULL | DEPTH_OFFSET = 0 | COLOR_CACHE_SIZE = CCU_CACHE_SIZE_FULL | COLOR_OFFSET = 0x10000 }
  +	00000000			VPC_UNKNOWN_9210: 0
@@ -2270,7 +2270,7 @@ got cmdszdw=38
 !+	00004001				RB_RESOLVE_SYSTEM_FLAG_BUFFER_PITCH: { PITCH = 64 | ARRAY_PITCH = 1024 }
 !+	00000003				RB_RESOLVE_OPERATION: { TYPE = BLIT_EVENT_LOAD | CLEAR_MASK = 0 | LAST = 0 | BUFFER_ID = 0 }
  +	00000000				RB_UNKNOWN_88F0: 0
- +	00000001				RB_UNKNOWN_8E01: 0x1
+ +	00000001				RB_RBP_CNTL: 0x1
  +	00100000				RB_DBG_ECO_CNTL: 0x100000
  +	08000000				RB_CCU_CNTL: { DEPTH_OFFSET_HI = 0 | COLOR_OFFSET_HI = 0 | DEPTH_CACHE_SIZE = CCU_CACHE_SIZE_FULL | DEPTH_OFFSET = 0 | COLOR_CACHE_SIZE = CCU_CACHE_SIZE_FULL | COLOR_OFFSET = 0x10000 }
  +	00000000				VPC_UNKNOWN_9210: 0
@@ -5028,7 +5028,7 @@ ESTIMATED CRASH LOCATION!
 !+	00000060			RB_A2D_DEST_BUFFER_INFO: { COLOR_FORMAT = FMT6_16_16_16_16_UNORM | TILE_MODE = TILE6_LINEAR | COLOR_SWAP = WZYX | SAMPLES = MSAA_ONE }
 !+	10008c000			RB_A2D_DEST_BUFFER_BASE: 0x10008c000
 !+	00000000			RB_A2D_DEST_BUFFER_PITCH: 0
- +	00000001			RB_UNKNOWN_8E01: 0x1
+ +	00000001			RB_RBP_CNTL: 0x1
  +	00100000			RB_DBG_ECO_CNTL: 0x100000
  +	08000000			RB_CCU_CNTL: { DEPTH_OFFSET_HI = 0 | COLOR_OFFSET_HI = 0 | DEPTH_CACHE_SIZE = CCU_CACHE_SIZE_FULL | DEPTH_OFFSET = 0 | COLOR_CACHE_SIZE = CCU_CACHE_SIZE_FULL | COLOR_OFFSET = 0x10000 }
  +	00000000			VPC_UNKNOWN_9210: 0
diff --git a/src/freedreno/tests/reference/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log b/src/freedreno/tests/reference/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log
index d788f669167..606dbd3676a 100644
--- a/src/freedreno/tests/reference/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log
+++ b/src/freedreno/tests/reference/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log
@@ -65,8 +65,8 @@ cmdstream[0]: 265 dwords
 		write UCHE_CLIENT_PF (0e19)
 			UCHE_CLIENT_PF: { PERFSEL = 0x4 }
 000000000105809c:		0000: 480e1901 00000004
-		write RB_UNKNOWN_8E01 (8e01)
-			RB_UNKNOWN_8E01: 0
+		write RB_RBP_CNTL (8e01)
+			RB_RBP_CNTL: 0
 00000000010580a4:		0000: 408e0101 00000000
 		write SP_PS_PROGRAM_COUNTER_OFFSET (a982)
 			SP_PS_PROGRAM_COUNTER_OFFSET: 0
@@ -306,7 +306,7 @@ cmdstream[0]: 265 dwords
  +	00000000		RB_A2D_CLEAR_COLOR_DW1: 0
  +	00000000		RB_A2D_CLEAR_COLOR_DW2: 0
 !+	000000ff		RB_A2D_CLEAR_COLOR_DW3: 0xff
- +	00000000		RB_UNKNOWN_8E01: 0
+ +	00000000		RB_RBP_CNTL: 0
 !+	00100000		RB_DBG_ECO_CNTL: 0x100000
 !+	10000000		RB_CCU_CNTL: { DEPTH_OFFSET_HI = 0 | COLOR_OFFSET_HI = 0 | DEPTH_CACHE_SIZE = CCU_CACHE_SIZE_FULL | DEPTH_OFFSET = 0 | COLOR_CACHE_SIZE = CCU_CACHE_SIZE_FULL | COLOR_OFFSET = 0x20000 }
  +	00000000		VPC_UNKNOWN_9107: { 0 }
diff --git a/src/freedreno/tests/reference/fd-clouds.log b/src/freedreno/tests/reference/fd-clouds.log
index eee20254633..b98bdaa3abd 100644
--- a/src/freedreno/tests/reference/fd-clouds.log
+++ b/src/freedreno/tests/reference/fd-clouds.log
@@ -62,8 +62,8 @@ cmdstream[0]: 1023 dwords
 		write UCHE_CLIENT_PF (0e19)
 			UCHE_CLIENT_PF: { PERFSEL = 0x4 }
 0000000001d91094:		0000: 480e1901 00000004
-		write RB_UNKNOWN_8E01 (8e01)
-			RB_UNKNOWN_8E01: 0x1
+		write RB_RBP_CNTL (8e01)
+			RB_RBP_CNTL: 0x1
 0000000001d9109c:		0000: 408e0101 00000001
 		write SP_MODE_CNTL (ab00)
 			SP_MODE_CNTL: { CONSTANT_DEMOTION_ENABLE | ISAMMODE = ISAMMODE_GL }
@@ -993,7 +993,7 @@ cmdstream[0]: 1023 dwords
  +	00000000			RB_UNKNOWN_88F0: 0
  +	00000000			RB_COLOR_FLAG_BUFFER[0].ADDR: 0
  +	00000000			RB_COLOR_FLAG_BUFFER[0].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 }
-!+	00000001			RB_UNKNOWN_8E01: 0x1
+!+	00000001			RB_RBP_CNTL: 0x1
  +	00000000			RB_DBG_ECO_CNTL: 0
 !+	7c400004			RB_CCU_CNTL: { CONCURRENT_RESOLVE | DEPTH_OFFSET_HI = 0 | COLOR_OFFSET_HI = 0 | DEPTH_CACHE_SIZE = CCU_CACHE_SIZE_FULL | DEPTH_OFFSET = 0 | COLOR_CACHE_SIZE = CCU_CACHE_SIZE_QUARTER | COLOR_OFFSET = 0xf8000 }
 !+	00ffff00			VPC_VS_CLIP_CULL_CNTL: { CLIP_MASK = 0 | CLIP_DIST_03_LOC = 255 | CLIP_DIST_47_LOC = 255 }
diff --git a/src/freedreno/tests/reference/prefetch-test.log b/src/freedreno/tests/reference/prefetch-test.log
index a7b5f5c0582..8dd73a45f43 100644
--- a/src/freedreno/tests/reference/prefetch-test.log
+++ b/src/freedreno/tests/reference/prefetch-test.log
@@ -1889,7 +1889,7 @@ registers:
 	00000000	PC_DMA_OFFSET: 0
 	00000006	PC_DMA_SIZE: 6
 	00000000	PC_TESS_BASE: 0
-	00000001	0x9e0a: 00000001
+	00000001	PC_AUTO_VERTEX_STRIDE: 0x1
 	00000504	PC_DRAWCALL_CNTL: { PRIM_TYPE = DI_PT_TRILIST | SOURCE_SELECT = DI_SRC_SEL_DMA | VIS_CULL = USE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_16_BIT | PATCH_TYPE = TESS_QUADS }
 	00000001	PC_DRAWCALL_INSTANCE_NUM: 1
 	00000006	PC_DRAWCALL_SIZE: 6
@@ -2340,7 +2340,7 @@ registers:
 	00000000	RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE: FALSE
 	00000000	RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ADDR: 0
 	00000000	0x8e52: 00000000
-	00000001	RB_UNKNOWN_8E01: 0x1
+	00000001	RB_RBP_CNTL: 0x1
 	00000101	0x8e0c: 00000101
 	00000000	RB_RB_SUB_BLOCK_SEL_CNTL_HOST: 0
 	00000000	0x8e3c: 00000000
@@ -2386,7 +2386,7 @@ registers:
 	deadbeef	SP_NC_MODE_CNTL: 0xdeadbeef
 	deadbeef	SP_CHICKEN_BITS: 0xdeadbeef
 	00000002	SP_NC_MODE_CNTL_2: { 0x2 }
-	deadbeef	0xae0c: deadbeef
+	deadbeef	SP_STATUS: 0xdeadbeef
 	deadbeef	SP_PERFCTR_SHADER_MASK: { VS | HS | DS | GS | CS | 0xdeadbec0 }
 	00000000	SP_PERFCTR_SP_SEL[0]+0: 00000000
 	00000000	SP_PERFCTR_SP_SEL[0x1]+0: 00000000
@@ -2547,7 +2547,7 @@ got cmdszdw=416
  +	00000000			RB_A2D_CLEAR_COLOR_DW1: 0
  +	00000000			RB_A2D_CLEAR_COLOR_DW2: 0
 !+	000000ff			RB_A2D_CLEAR_COLOR_DW3: 0xff
-!+	00000001			RB_UNKNOWN_8E01: 0x1
+!+	00000001			RB_RBP_CNTL: 0x1
 !+	04100000			RB_DBG_ECO_CNTL: 0x4100000
  +	00000000			VPC_UNKNOWN_9210: 0
  +	00000000			VPC_UNKNOWN_9211: 0
diff --git a/src/freedreno/vulkan/tu_cmd_buffer.cc b/src/freedreno/vulkan/tu_cmd_buffer.cc
index f1366b036f5..126cfe1169e 100644
--- a/src/freedreno/vulkan/tu_cmd_buffer.cc
+++ b/src/freedreno/vulkan/tu_cmd_buffer.cc
@@ -1753,8 +1753,8 @@ tu6_init_static_regs(struct tu_device *dev, struct tu_cs *cs)
                         phys_dev->info->a6xx.magic.UCHE_UNKNOWN_0E12);
    tu_cs_emit_write_reg(cs, REG_A6XX_UCHE_CLIENT_PF,
                         phys_dev->info->a6xx.magic.UCHE_CLIENT_PF);
-   tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8E01,
-                        phys_dev->info->a6xx.magic.RB_UNKNOWN_8E01);
+   tu_cs_emit_write_reg(cs, REG_A6XX_RB_RBP_CNTL,
+                        phys_dev->info->a6xx.magic.RB_RBP_CNTL);
    tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_A9A8, 0);
    tu_cs_emit_regs(cs, A6XX_SP_MODE_CNTL(.constant_demotion_enable = true,
                                             .isammode = ISAMMODE_GL,
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_emit.cc b/src/gallium/drivers/freedreno/a6xx/fd6_emit.cc
index f95fe3b84ce..c64ad9a18d3 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_emit.cc
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_emit.cc
@@ -930,7 +930,7 @@ fd6_emit_static_context_regs(struct fd_context *ctx, fd_cs &cs)
    crb.add(SP_GFX_USIZE(CHIP));
    crb.add(A6XX_SP_UNKNOWN_B182());
 
-   crb.add(A6XX_RB_UNKNOWN_8E01(.dword = screen->info->a6xx.magic.RB_UNKNOWN_8E01));
+   crb.add(A6XX_RB_RBP_CNTL(.dword = screen->info->a6xx.magic.RB_RBP_CNTL));
    crb.add(A6XX_SP_UNKNOWN_A9A8());
 
    crb.add(A6XX_SP_MODE_CNTL(