diff --git a/docs/relnotes/new_features.txt b/docs/relnotes/new_features.txt
index 801a2154307..2a705e811be 100644
--- a/docs/relnotes/new_features.txt
+++ b/docs/relnotes/new_features.txt
@@ -9,3 +9,4 @@ primitiveUnderestimation on RADV/GFX9+
 VK_KHR_fragment_shading_rate on RADV/GFX11
 VK_EXT_mesh_shader on RADV/GFX11
 RGP support on RADV/GFX11
+GL_NV_alpha_to_coverage_dither_control on r600/evergreen+
diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index b8a2ae768d3..7a6b98a7b58 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -324,6 +324,7 @@ static void *evergreen_create_blend_state_mode(struct pipe_context *ctx,
 					       const struct pipe_blend_state *state, int mode)
 {
 	uint32_t color_control = 0, target_mask = 0;
+	uint32_t alpha_to_mask = 0;
 	struct r600_blend_state *blend = CALLOC_STRUCT(r600_blend_state);
 
 	if (!blend) {
@@ -359,14 +360,27 @@ static void *evergreen_create_blend_state_mode(struct pipe_context *ctx,
 	else
 		color_control |= S_028808_MODE(V_028808_CB_DISABLE);
 
-
 	r600_store_context_reg(&blend->buffer, R_028808_CB_COLOR_CONTROL, color_control);
-	r600_store_context_reg(&blend->buffer, R_028B70_DB_ALPHA_TO_MASK,
-			       S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
-			       S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
-			       S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
-			       S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
-			       S_028B70_ALPHA_TO_MASK_OFFSET3(2));
+
+	if (state->alpha_to_coverage) {
+		if (state->alpha_to_coverage_dither) {
+			alpha_to_mask = S_028B70_ALPHA_TO_MASK_ENABLE(1) |
+			                S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
+			                S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
+			                S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
+			                S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
+			                S_028B70_OFFSET_ROUND(1);
+		} else {
+			alpha_to_mask = S_028B70_ALPHA_TO_MASK_ENABLE(1) |
+			                S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
+			                S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
+			                S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
+			                S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
+			                S_028B70_OFFSET_ROUND(0);
+		}
+	}
+	r600_store_context_reg(&blend->buffer, R_028B70_DB_ALPHA_TO_MASK, alpha_to_mask);
+
 	r600_store_context_reg_seq(&blend->buffer, R_028780_CB_BLEND0_CONTROL, 8);
 
 	/* Copy over the dwords set so far into buffer_no_blend.
diff --git a/src/gallium/drivers/r600/r600_pipe.c b/src/gallium/drivers/r600/r600_pipe.c
index 404232488e2..a7ba6f74644 100644
--- a/src/gallium/drivers/r600/r600_pipe.c
+++ b/src/gallium/drivers/r600/r600_pipe.c
@@ -383,6 +383,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 	case PIPE_CAP_SHADER_ARRAY_COMPONENTS:
 	case PIPE_CAP_QUERY_BUFFER_OBJECT:
 	case PIPE_CAP_IMAGE_STORE_FORMATTED:
+	case PIPE_CAP_ALPHA_TO_COVERAGE_DITHER_CONTROL:
 		return family >= CHIP_CEDAR ? 1 : 0;
 	case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 		return family >= CHIP_CEDAR ? 4 : 0;