From 301a3bacce82c4489af4f0f854f21b1de3bfab99 Mon Sep 17 00:00:00 2001 From: Patrick Lerda Date: Thu, 6 Jun 2024 18:13:12 +0200 Subject: [PATCH] radeonsi: fix assert triggered on gfx6 after the tessellation update MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This change updates the affected calls to the proper function which is radeon_set_config_reg(). For instance, this issue is triggered with "piglit/bin/textureSize tes isampler2DMSArray -auto -fbo": vertex-program-two-side: ../src/gallium/drivers/radeonsi/si_state_shaders.cpp:4981: void si_emit_spi_ge_ring_state(si_context*, unsigned int): Assertion `(0x008988) >= CIK_UCONFIG_REG_OFFSET && (0x008988) < CIK_UCONFIG_REG_END' failed. Fixes: bd71d62b8fc ("radeonsi: program tessellation rings right before draws") Signed-off-by: Patrick Lerda Reviewed-by: Marek Olšák Part-of: --- src/gallium/drivers/radeonsi/si_state_shaders.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.cpp b/src/gallium/drivers/radeonsi/si_state_shaders.cpp index df03fd292d4..e42c11a27f1 100644 --- a/src/gallium/drivers/radeonsi/si_state_shaders.cpp +++ b/src/gallium/drivers/radeonsi/si_state_shaders.cpp @@ -4978,9 +4978,9 @@ static void si_emit_spi_ge_ring_state(struct si_context *sctx, unsigned index) else if (sctx->gfx_level == GFX9) radeon_set_uconfig_reg(R_030944_VGT_TF_MEMORY_BASE_HI, S_030944_BASE_HI(factor_va >> 40)); } else { - radeon_set_uconfig_reg(R_008988_VGT_TF_RING_SIZE, S_008988_SIZE(tf_ring_size_field)); - radeon_set_uconfig_reg(R_0089B8_VGT_TF_MEMORY_BASE, factor_va >> 8); - radeon_set_uconfig_reg(R_0089B0_VGT_HS_OFFCHIP_PARAM, sscreen->hs.hs_offchip_param); + radeon_set_config_reg(R_008988_VGT_TF_RING_SIZE, S_008988_SIZE(tf_ring_size_field)); + radeon_set_config_reg(R_0089B8_VGT_TF_MEMORY_BASE, factor_va >> 8); + radeon_set_config_reg(R_0089B0_VGT_HS_OFFCHIP_PARAM, sscreen->hs.hs_offchip_param); } radeon_end(); }