From 2f49284cfa9da5c64ccf5bd1466d6de9536edd51 Mon Sep 17 00:00:00 2001 From: M Henning Date: Sat, 13 Jul 2024 16:24:32 -0400 Subject: [PATCH] nak: Rename num_barriers to num_control_barriers Hopefully this is a little more clear. Part-of: --- src/nouveau/compiler/nak.h | 10 ++++++++-- src/nouveau/compiler/nak/api.rs | 2 +- src/nouveau/compiler/nak/from_nir.rs | 4 ++-- src/nouveau/compiler/nak/ir.rs | 2 +- src/nouveau/compiler/nak/qmd.rs | 2 +- src/nouveau/vulkan/nvk_codegen.c | 2 +- 6 files changed, 14 insertions(+), 8 deletions(-) diff --git a/src/nouveau/compiler/nak.h b/src/nouveau/compiler/nak.h index 58302d0f1d3..d02b0e38226 100644 --- a/src/nouveau/compiler/nak.h +++ b/src/nouveau/compiler/nak.h @@ -98,8 +98,14 @@ struct nak_shader_info { /** Number of GPRs used */ uint8_t num_gprs; - /** Number of barriers used */ - uint8_t num_barriers; + /** + * Number of control barriers used + * + * These are barriers in the sense of glsl barrier(), not reconvergence + * barriers. In CUDA, these barriers have an index, but we currently + * only use index zero for vulkan, which means this will be at most 1. + */ + uint8_t num_control_barriers; uint8_t _pad0; diff --git a/src/nouveau/compiler/nak/api.rs b/src/nouveau/compiler/nak/api.rs index 0e6721cc678..18168f8264c 100644 --- a/src/nouveau/compiler/nak/api.rs +++ b/src/nouveau/compiler/nak/api.rs @@ -315,7 +315,7 @@ pub extern "C" fn nak_compile_shader( } else { max(4, s.info.num_gprs) }, - num_barriers: s.info.num_barriers, + num_control_barriers: s.info.num_control_barriers, _pad0: Default::default(), num_instrs: s.info.num_instrs, slm_size: s.info.slm_size, diff --git a/src/nouveau/compiler/nak/from_nir.rs b/src/nouveau/compiler/nak/from_nir.rs index 88bdc34a1c1..ccebad90496 100644 --- a/src/nouveau/compiler/nak/from_nir.rs +++ b/src/nouveau/compiler/nak/from_nir.rs @@ -22,7 +22,7 @@ fn init_info_from_nir(nir: &nir_shader) -> ShaderInfo { ShaderInfo { num_gprs: 0, num_instrs: 0, - num_barriers: 0, + num_control_barriers: 0, slm_size: nir.scratch_size, uses_global_mem: false, writes_global_mem: false, @@ -2761,7 +2761,7 @@ impl<'a> ShaderFromNir<'a> { self.nir.info.stage() == MESA_SHADER_COMPUTE || self.nir.info.stage() == MESA_SHADER_KERNEL ); - self.info.num_barriers = 1; + self.info.num_control_barriers = 1; b.push_op(OpBar {}); } _ => panic!("Unhandled execution scope"), diff --git a/src/nouveau/compiler/nak/ir.rs b/src/nouveau/compiler/nak/ir.rs index 992db18401f..e1aa87f7dd7 100644 --- a/src/nouveau/compiler/nak/ir.rs +++ b/src/nouveau/compiler/nak/ir.rs @@ -6353,7 +6353,7 @@ pub enum ShaderIoInfo { #[derive(Debug)] pub struct ShaderInfo { pub num_gprs: u8, - pub num_barriers: u8, + pub num_control_barriers: u8, pub num_instrs: u32, pub slm_size: u32, pub uses_global_mem: bool, diff --git a/src/nouveau/compiler/nak/qmd.rs b/src/nouveau/compiler/nak/qmd.rs index 03e9a241d24..9f7887eaf9d 100644 --- a/src/nouveau/compiler/nak/qmd.rs +++ b/src/nouveau/compiler/nak/qmd.rs @@ -324,7 +324,7 @@ fn fill_qmd(info: &nak_shader_info, qmd_info: &nak_qmd_info) -> Q { let mut qmd = Q::new(); - qmd.set_barrier_count(info.num_barriers); + qmd.set_barrier_count(info.num_control_barriers); qmd.set_global_size( qmd_info.global_size[0], qmd_info.global_size[1], diff --git a/src/nouveau/vulkan/nvk_codegen.c b/src/nouveau/vulkan/nvk_codegen.c index 514370222f0..99a1258d442 100644 --- a/src/nouveau/vulkan/nvk_codegen.c +++ b/src/nouveau/vulkan/nvk_codegen.c @@ -843,7 +843,7 @@ nvk_cg_compile_nir(struct nvk_physical_device *pdev, nir_shader *nir, shader->info.num_gprs = MAX2(4, info_out.bin.maxGPR + 3); else shader->info.num_gprs = MAX2(4, info_out.bin.maxGPR + 1); - shader->info.num_barriers = info_out.numBarriers; + shader->info.num_control_barriers = info_out.numBarriers; if (info_out.bin.tlsSpace) { assert(info_out.bin.tlsSpace < (1 << 24));