From 2f3dc31876d56340124e994c3bad7a76e35d4a15 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?= Date: Wed, 27 Mar 2024 09:21:03 -0700 Subject: [PATCH] anv: Set STATE_COMPUTE_MODE mask bit when zeroing compute mode MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Justing setting all zeroes to STATE_COMPUTE_MODE will do nothing, the mask of each register must be set for it to change. Signed-off-by: José Roberto de Souza Reviewed-by: Lionel Landwerlin Part-of: --- src/intel/genxml/gen125.xml | 9 +++++---- src/intel/vulkan/genX_init_state.c | 4 +++- 2 files changed, 8 insertions(+), 5 deletions(-) diff --git a/src/intel/genxml/gen125.xml b/src/intel/genxml/gen125.xml index 9b3695b449d..5bd36ac0f9d 100644 --- a/src/intel/genxml/gen125.xml +++ b/src/intel/genxml/gen125.xml @@ -1910,6 +1910,7 @@ + @@ -2129,10 +2130,10 @@ - - - - + + + + diff --git a/src/intel/vulkan/genX_init_state.c b/src/intel/vulkan/genX_init_state.c index d31e26901e2..b5e03212fa7 100644 --- a/src/intel/vulkan/genX_init_state.c +++ b/src/intel/vulkan/genX_init_state.c @@ -591,7 +591,9 @@ init_render_queue_state(struct anv_queue *queue, bool is_companion_rcs_batch) #endif #if GFX_VERx10 >= 125 - anv_batch_emit(&batch, GENX(STATE_COMPUTE_MODE), zero); + anv_batch_emit(&batch, GENX(STATE_COMPUTE_MODE), cm) { + cm.Mask1 = 0xffff; + } anv_batch_emit(&batch, GENX(3DSTATE_MESH_CONTROL), zero); anv_batch_emit(&batch, GENX(3DSTATE_TASK_CONTROL), zero);