From 2c9bc313a0e983721e11b06e56f5d039816d5922 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Tapani=20P=C3=A4lli?= Date: Mon, 4 Aug 2025 10:16:23 +0300 Subject: [PATCH] intel/genxml: update CACHE_MODE_0 register for gfx200 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Field that we currently utilize does not change place, however there are some new fields so let's update contents to match spec. Signed-off-by: Tapani Pälli Reviewed-by: José Roberto de Souza Part-of: --- src/intel/genxml/gen200.xml | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/src/intel/genxml/gen200.xml b/src/intel/genxml/gen200.xml index 004db8a0e9e..4d32bd19dd8 100644 --- a/src/intel/genxml/gen200.xml +++ b/src/intel/genxml/gen200.xml @@ -1921,6 +1921,24 @@ + + + + + + + + + + + + + + + + + +