From 2beb5b015ab911f7f757cac5e3e78bdf69e94b5b Mon Sep 17 00:00:00 2001
From: Rob Clark <robdclark@chromium.org>
Date: Thu, 27 May 2021 14:37:59 -0700
Subject: [PATCH] freedreno/ci: Add real packet-table loading for afuc test

When we start running the bootstrap code thru the emulator we will need
the packet-table loading to actually happen.  So add this.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10944>
---
 .../.gitlab-ci/reference/afuc_test.asm        |  26 +++++++++++++-
 .../.gitlab-ci/reference/afuc_test.fw         | Bin 900 -> 996 bytes
 src/freedreno/.gitlab-ci/traces/afuc_test.asm |  32 ++++++++++++++++++
 3 files changed, 57 insertions(+), 1 deletion(-)

diff --git a/src/freedreno/.gitlab-ci/reference/afuc_test.asm b/src/freedreno/.gitlab-ci/reference/afuc_test.asm
index aa0f370cd66..c68460477bb 100644
--- a/src/freedreno/.gitlab-ci/reference/afuc_test.asm
+++ b/src/freedreno/.gitlab-ci/reference/afuc_test.asm
@@ -3,7 +3,31 @@
 ; Version: 01000001
 
         [01000001]  ; nop
-        [01000060]  ; nop
+        [01000078]  ; nop
+        mov $01, 0x0830	; CP_SQE_INSTR_BASE
+        mov $02, 0x0002
+        cwrite $01, [$00 + @REG_READ_ADDR], 0x0
+        cwrite $02, [$00 + @REG_READ_DWORDS], 0x0
+        mov $01, $regdata
+        mov $02, $regdata
+        add $01, $01, 0x0004
+        addhi $02, $02, 0x0000
+        mov $03, 0x0001
+        cwrite $01, [$00 + @MEM_READ_ADDR], 0x0
+        cwrite $02, [$00 + @MEM_READ_ADDR+0x1], 0x0
+        cwrite $03, [$00 + @MEM_READ_DWORDS], 0x0
+        rot $04, $memdata, 0x0008
+        ushr $04, $04, 0x0006
+        sub $04, $04, 0x0004
+        add $01, $01, $04
+        addhi $02, $02, 0x0000
+        mov $rem, 0x0080
+        cwrite $01, [$00 + @MEM_READ_ADDR], 0x0
+        cwrite $02, [$00 + @MEM_READ_ADDR+0x1], 0x0
+        cwrite $02, [$00 + @LOAD_STORE_HI], 0x0
+        cwrite $rem, [$00 + @MEM_READ_DWORDS], 0x0
+        cwrite $00, [$00 + @PACKET_TABLE_WRITE_ADDR], 0x0
+        (rep)cwrite $memdata, [$00 + @PACKET_TABLE_WRITE], 0x0
         mov $02, 0x0883	; CP_SCRATCH[0].REG
         mov $03, 0xbeef
         mov $04, 0xdead << 16
diff --git a/src/freedreno/.gitlab-ci/reference/afuc_test.fw b/src/freedreno/.gitlab-ci/reference/afuc_test.fw
index 149e84deb3dbc5262b1d2bb123fe02548ef5db91..e48cb0bde0bf2dcfbea20990a6efc4855922677a 100644
GIT binary patch
literal 996
zcmb`CJ4*vW6ot?1uES`2Y+<oVl2!3lSOg2PGbV+tjgZE-oxNCzFK~%}U<!*MDYj6s
zv=R}E6e&b3tRz1`&{BNGGtre`A^3p(m^pLLz2`0f2!5+1r9@!C3I-s;epsPYNiE%^
zcF?VWj4NOV9%~(}b;1r6ii;B4lMc2$p?bCPtRw#E$<=)Ea1IFPkvP~=R&aM>2ZuLK
zUV2Nqm-Rl*;R@GM`PyVh_W}~T4z+lk)y{q*FJJw=s8%)a>DhxwOV?*MZb^yoci!i@
zU0E%$UbeAOdZ})fZErz8RZ+6ttnptM?*RNTgR_|BCAIC&=n>$`@z!($?*f?=8C9;O
z8>yQ}j5L#0(neZHJL~e^*Yd$Kb8G)%c9I_HB7-DFaC)AD9XjcWqZ}H-XYS&pcM4ID
z$6Y#z>CKt5;_FVt>7On}9wDq_h4E8rF$`49Sw}6K`tswgrdKF_%km$3>odpxX-@sj
e@9up+$m{vy9r~ib%lS(!^^2T^kDjR?^u7UlDykj;

literal 900
zcmb`Cy-EW?6ov23Y=$*4x<!gHm~09qmMLw7H7NvJn=~dOK8N^IxWpHj!Xk*p778h?
zB#6ZpDMT!+Bo82HDgLcz)+{V30!f7Zn0sc<z2`0wk%4aq99ztLz2V-~v)K}IPc0Gi
zmx=qZJPFHDjF=bKZ7Q6a(8fnondgO;_;JqSw@}}^&C6H|+fk@rKmZW;H_tBBl%Rti
zr^DboJnC_|t3E>txLwo!d+jZg<5%f6!(>r$yP=9ikEYyLDbxm4D`3^KnVNx4gAAAj
zb6_51K@RWY%~9f=>ABIr=$(WFC9nc2fVy{e;=bu_bn2Ayzp#txp0wj0iCq?e?yc*y
z@2EU2!oPhHdklkJTeRMVHu6M$eI|&qp&tf!k#0at%GMOU$;|RU%}LH2RcFV@OAmQ-
TLwZ!sG;eZ(oXtVc+8DjRL%NHr

diff --git a/src/freedreno/.gitlab-ci/traces/afuc_test.asm b/src/freedreno/.gitlab-ci/traces/afuc_test.asm
index 57bec845565..68a3061f1cf 100644
--- a/src/freedreno/.gitlab-ci/traces/afuc_test.asm
+++ b/src/freedreno/.gitlab-ci/traces/afuc_test.asm
@@ -29,6 +29,38 @@
 [01000001]
 [01000000]
 loc02:
+; packet table loading:
+mov $01, 0x0830 ; CP_SQE_INSTR_BASE
+mov $02, 0x0002
+cwrite $01, [$00 + @REG_READ_ADDR], 0x0
+cwrite $02, [$00 + @REG_READ_DWORDS], 0x0
+; move hi/lo of SQE fw addrs to registers:
+mov $01, $regdata
+mov $02, $regdata
+; skip first dword
+add $01, $01, 0x0004
+addhi $02, $02, 0x0000
+mov $03, 0x0001
+cwrite $01, [$00 + @MEM_READ_ADDR], 0x0
+cwrite $02, [$00 + @MEM_READ_ADDR+0x1], 0x0
+cwrite $03, [$00 + @MEM_READ_DWORDS], 0x0
+; read 2nd dword of fw, and add offset (minus 4 because we skipped first dword)
+; to base address of sqe fw
+rot $04, $memdata, 0x0008
+ushr $04, $04, 0x0006
+sub $04, $04, 0x0004
+add $01, $01, $04
+addhi $02, $02, 0x0000
+
+; load packet table:
+mov $rem, 0x0080
+cwrite $01, [$00 + @MEM_READ_ADDR], 0x0
+cwrite $02, [$00 + @MEM_READ_ADDR+0x1], 0x0
+cwrite $02, [$00 + @LOAD_STORE_HI], 0x0
+cwrite $rem, [$00 + @MEM_READ_DWORDS], 0x0
+cwrite $00, [$00 + @PACKET_TABLE_WRITE_ADDR], 0x0
+(rep)cwrite $memdata, [$00 + @PACKET_TABLE_WRITE], 0x0
+
 mov $02, 0x883
 mov $03, 0xbeef
 mov $04, 0xdead << 16