From 2bd1beac4cb28158a18a9f8c81a5cd165c8a9030 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Wed, 8 Oct 2025 18:27:49 +0200 Subject: [PATCH] radv: Remove qf argument from radv_cs_emit_cache_flush Part-of: --- src/amd/vulkan/radv_cmd_buffer.c | 11 ++++------- src/amd/vulkan/radv_cs.c | 31 +++++++++++++++---------------- src/amd/vulkan/radv_cs.h | 5 ++--- src/amd/vulkan/radv_queue.c | 4 ++-- src/amd/vulkan/radv_sqtt.c | 3 +-- 5 files changed, 24 insertions(+), 30 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 88e8dd3781e..b83385e2284 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -1475,8 +1475,7 @@ radv_gang_cache_flush(struct radv_cmd_buffer *cmd_buffer) const uint32_t flush_bits = cmd_buffer->gang.flush_bits; enum rgp_flush_bits sqtt_flush_bits = 0; - radv_cs_emit_cache_flush(device->ws, ace_cs, pdev->info.gfx_level, NULL, 0, RADV_QUEUE_COMPUTE, flush_bits, - &sqtt_flush_bits, 0); + radv_cs_emit_cache_flush(device->ws, ace_cs, pdev->info.gfx_level, NULL, 0, flush_bits, &sqtt_flush_bits, 0); cmd_buffer->gang.flush_bits = 0; } @@ -1649,12 +1648,11 @@ radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer, enum radv_cmd_flu /* Force wait for graphics or compute engines to be idle. */ radv_cs_emit_cache_flush(device->ws, cs, pdev->info.gfx_level, &cmd_buffer->gfx9_fence_idx, - cmd_buffer->gfx9_fence_va, cmd_buffer->qf, flags, &sqtt_flush_bits, - cmd_buffer->gfx9_eop_bug_va); + cmd_buffer->gfx9_fence_va, flags, &sqtt_flush_bits, cmd_buffer->gfx9_eop_bug_va); if ((flags & RADV_CMD_FLAG_PS_PARTIAL_FLUSH) && radv_cmdbuf_has_stage(cmd_buffer, MESA_SHADER_TASK)) { /* Force wait for compute engines to be idle on the internal cmdbuf. */ - radv_cs_emit_cache_flush(device->ws, cmd_buffer->gang.cs, pdev->info.gfx_level, NULL, 0, RADV_QUEUE_COMPUTE, + radv_cs_emit_cache_flush(device->ws, cmd_buffer->gang.cs, pdev->info.gfx_level, NULL, 0, RADV_CMD_FLAG_CS_PARTIAL_FLUSH, &sqtt_flush_bits, 0); } } @@ -14226,8 +14224,7 @@ radv_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer) } radv_cs_emit_cache_flush(device->ws, cs, pdev->info.gfx_level, &cmd_buffer->gfx9_fence_idx, - cmd_buffer->gfx9_fence_va, cmd_buffer->qf, - cmd_buffer->state.flush_bits, &cmd_buffer->state.sqtt_flush_bits, + cmd_buffer->gfx9_fence_va, cmd_buffer->state.flush_bits, &cmd_buffer->state.sqtt_flush_bits, cmd_buffer->gfx9_eop_bug_va); if (radv_device_fault_detection_enabled(device)) diff --git a/src/amd/vulkan/radv_cs.c b/src/amd/vulkan/radv_cs.c index 75714f1703b..ecec3bb7285 100644 --- a/src/amd/vulkan/radv_cs.c +++ b/src/amd/vulkan/radv_cs.c @@ -131,10 +131,10 @@ radv_emit_acquire_mem(struct radv_cmd_stream *cs, bool is_mec, bool is_gfx9, uns static void gfx10_cs_emit_cache_flush(struct radv_cmd_stream *cs, enum amd_gfx_level gfx_level, uint32_t *flush_cnt, - uint64_t flush_va, enum radv_queue_family qf, enum radv_cmd_flush_bits flush_bits, - enum rgp_flush_bits *sqtt_flush_bits, uint64_t gfx9_eop_bug_va) + uint64_t flush_va, enum radv_cmd_flush_bits flush_bits, enum rgp_flush_bits *sqtt_flush_bits, + uint64_t gfx9_eop_bug_va) { - const bool is_mec = qf == RADV_QUEUE_COMPUTE; + const bool is_mec = cs->hw_ip == AMD_IP_COMPUTE; uint32_t gcr_cntl = 0; unsigned cb_db_event = 0; @@ -357,15 +357,15 @@ gfx10_cs_emit_cache_flush(struct radv_cmd_stream *cs, enum amd_gfx_level gfx_lev } if (flush_bits & RADV_CMD_FLAG_START_PIPELINE_STATS) { - if (qf == RADV_QUEUE_GENERAL) { + if (!is_mec) { radeon_event_write(V_028A90_PIPELINESTAT_START); - } else if (qf == RADV_QUEUE_COMPUTE) { + } else { radeon_set_sh_reg(R_00B828_COMPUTE_PIPELINESTAT_ENABLE, S_00B828_PIPELINESTAT_ENABLE(1)); } } else if (flush_bits & RADV_CMD_FLAG_STOP_PIPELINE_STATS) { - if (qf == RADV_QUEUE_GENERAL) { + if (!is_mec) { radeon_event_write(V_028A90_PIPELINESTAT_STOP); - } else if (qf == RADV_QUEUE_COMPUTE) { + } else { radeon_set_sh_reg(R_00B828_COMPUTE_PIPELINESTAT_ENABLE, S_00B828_PIPELINESTAT_ENABLE(0)); } } @@ -375,9 +375,8 @@ gfx10_cs_emit_cache_flush(struct radv_cmd_stream *cs, enum amd_gfx_level gfx_lev void radv_cs_emit_cache_flush(struct radeon_winsys *ws, struct radv_cmd_stream *cs, enum amd_gfx_level gfx_level, - uint32_t *flush_cnt, uint64_t flush_va, enum radv_queue_family qf, - enum radv_cmd_flush_bits flush_bits, enum rgp_flush_bits *sqtt_flush_bits, - uint64_t gfx9_eop_bug_va) + uint32_t *flush_cnt, uint64_t flush_va, enum radv_cmd_flush_bits flush_bits, + enum rgp_flush_bits *sqtt_flush_bits, uint64_t gfx9_eop_bug_va) { unsigned cp_coher_cntl = 0; uint32_t flush_cb_db = flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_DB); @@ -386,11 +385,11 @@ radv_cs_emit_cache_flush(struct radeon_winsys *ws, struct radv_cmd_stream *cs, e if (gfx_level >= GFX10) { /* GFX10 cache flush handling is quite different. */ - gfx10_cs_emit_cache_flush(cs, gfx_level, flush_cnt, flush_va, qf, flush_bits, sqtt_flush_bits, gfx9_eop_bug_va); + gfx10_cs_emit_cache_flush(cs, gfx_level, flush_cnt, flush_va, flush_bits, sqtt_flush_bits, gfx9_eop_bug_va); return; } - const bool is_mec = qf == RADV_QUEUE_COMPUTE && gfx_level >= GFX7; + const bool is_mec = cs->hw_ip == AMD_IP_COMPUTE && gfx_level >= GFX7; if (flush_bits & RADV_CMD_FLAG_INV_ICACHE) { cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1); @@ -568,15 +567,15 @@ radv_cs_emit_cache_flush(struct radeon_winsys *ws, struct radv_cmd_stream *cs, e radeon_begin(cs); if (flush_bits & RADV_CMD_FLAG_START_PIPELINE_STATS) { - if (qf == RADV_QUEUE_GENERAL) { + if (!is_mec) { radeon_event_write(V_028A90_PIPELINESTAT_START); - } else if (qf == RADV_QUEUE_COMPUTE) { + } else { radeon_set_sh_reg(R_00B828_COMPUTE_PIPELINESTAT_ENABLE, S_00B828_PIPELINESTAT_ENABLE(1)); } } else if (flush_bits & RADV_CMD_FLAG_STOP_PIPELINE_STATS) { - if (qf == RADV_QUEUE_GENERAL) { + if (!is_mec) { radeon_event_write(V_028A90_PIPELINESTAT_STOP); - } else if (qf == RADV_QUEUE_COMPUTE) { + } else { radeon_set_sh_reg(R_00B828_COMPUTE_PIPELINESTAT_ENABLE, S_00B828_PIPELINESTAT_ENABLE(0)); } } diff --git a/src/amd/vulkan/radv_cs.h b/src/amd/vulkan/radv_cs.h index 22e11c0916f..5626894a1d6 100644 --- a/src/amd/vulkan/radv_cs.h +++ b/src/amd/vulkan/radv_cs.h @@ -401,9 +401,8 @@ void radv_cs_emit_write_event_eop(struct radv_cmd_stream *cs, enum amd_gfx_level uint32_t new_fence, uint64_t gfx9_eop_bug_va); void radv_cs_emit_cache_flush(struct radeon_winsys *ws, struct radv_cmd_stream *cs, enum amd_gfx_level gfx_level, - uint32_t *flush_cnt, uint64_t flush_va, enum radv_queue_family qf, - enum radv_cmd_flush_bits flush_bits, enum rgp_flush_bits *sqtt_flush_bits, - uint64_t gfx9_eop_bug_va); + uint32_t *flush_cnt, uint64_t flush_va, enum radv_cmd_flush_bits flush_bits, + enum rgp_flush_bits *sqtt_flush_bits, uint64_t gfx9_eop_bug_va); void radv_emit_cond_exec(const struct radv_device *device, struct radv_cmd_stream *cs, uint64_t va, uint32_t count); diff --git a/src/amd/vulkan/radv_queue.c b/src/amd/vulkan/radv_queue.c index 3c1c756c5bc..bb3c6a67910 100644 --- a/src/amd/vulkan/radv_queue.c +++ b/src/amd/vulkan/radv_queue.c @@ -1192,7 +1192,7 @@ radv_update_preamble_cs(struct radv_queue_state *queue, struct radv_device *devi flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH; } - radv_cs_emit_cache_flush(ws, cs, gfx_level, NULL, 0, queue->qf, flush_bits, &sqtt_flush_bits, 0); + radv_cs_emit_cache_flush(ws, cs, gfx_level, NULL, 0, flush_bits, &sqtt_flush_bits, 0); } result = radv_finalize_cmd_stream(device, cs); @@ -1408,7 +1408,7 @@ radv_create_flush_postamble(struct radv_queue *queue) } enum rgp_flush_bits sqtt_flush_bits = 0; - radv_cs_emit_cache_flush(ws, cs, gfx_level, NULL, 0, queue->state.qf, flush_bits, &sqtt_flush_bits, 0); + radv_cs_emit_cache_flush(ws, cs, gfx_level, NULL, 0, flush_bits, &sqtt_flush_bits, 0); result = radv_finalize_cmd_stream(device, cs); if (result != VK_SUCCESS) { diff --git a/src/amd/vulkan/radv_sqtt.c b/src/amd/vulkan/radv_sqtt.c index 8b4bba571da..c8f28a93566 100644 --- a/src/amd/vulkan/radv_sqtt.c +++ b/src/amd/vulkan/radv_sqtt.c @@ -51,10 +51,9 @@ static void radv_emit_wait_for_idle(const struct radv_device *device, struct radv_cmd_stream *cs, int family) { const struct radv_physical_device *pdev = radv_device_physical(device); - const enum radv_queue_family qf = radv_ip_to_queue_family(family); enum rgp_flush_bits sqtt_flush_bits = 0; radv_cs_emit_cache_flush( - device->ws, cs, pdev->info.gfx_level, NULL, 0, qf, + device->ws, cs, pdev->info.gfx_level, NULL, 0, (family == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) | RADV_CMD_FLAG_INV_ICACHE | RADV_CMD_FLAG_INV_SCACHE | RADV_CMD_FLAG_INV_VCACHE | RADV_CMD_FLAG_INV_L2,