From 2bb102f020b3a5834d219ab474c6bcdd02f88d09 Mon Sep 17 00:00:00 2001 From: Gert Wollny Date: Sat, 20 Apr 2024 23:54:57 +0200 Subject: [PATCH] r600/sfn: Don't put b2f64 conversion into ALU group There is no need to pin the ops into channels because these are 32 bit ops that can be executed independent from each other. Fixes: 79ca456b4837b3bc21cf9ef3c03c505c4b4909f6 r600/sfn: rewrite NIR backend v2: grammar fixes (lorn10) Signed-off-by: Gert Wollny Part-of: --- src/gallium/drivers/r600/sfn/sfn_instr_alu.cpp | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/src/gallium/drivers/r600/sfn/sfn_instr_alu.cpp b/src/gallium/drivers/r600/sfn/sfn_instr_alu.cpp index d658a7f8cbf..b5091c64361 100644 --- a/src/gallium/drivers/r600/sfn/sfn_instr_alu.cpp +++ b/src/gallium/drivers/r600/sfn/sfn_instr_alu.cpp @@ -2210,27 +2210,22 @@ static bool emit_alu_b2f64(const nir_alu_instr& alu, Shader& shader) { auto& value_factory = shader.value_factory(); - auto group = new AluGroup(); - AluInstr *ir = nullptr; for (unsigned i = 0; i < alu.def.num_components; ++i) { - ir = new AluInstr(op2_and_int, + auto ir = new AluInstr(op2_and_int, value_factory.dest(alu.def, 2 * i, pin_group), value_factory.src(alu.src[0], i), value_factory.zero(), {alu_write}); - group->add_instruction(ir); + shader.emit_instruction(ir); ir = new AluInstr(op2_and_int, value_factory.dest(alu.def, 2 * i + 1, pin_group), value_factory.src(alu.src[0], i), value_factory.literal(0x3ff00000), {alu_write}); - group->add_instruction(ir); + shader.emit_instruction(ir); } - if (ir) - ir->set_alu_flag(alu_last_instr); - shader.emit_instruction(group); return true; }