From 2b99906e5bd809f3502668ae096f9a9c8e729c9d Mon Sep 17 00:00:00 2001 From: Josh Simmons Date: Tue, 16 Jul 2024 06:48:14 +0200 Subject: [PATCH] radv: Fix shader mask for SQ_WGP SPM counters Signed-off-by: Josh Simmons Part-of: --- src/amd/vulkan/radv_perfcounter.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/amd/vulkan/radv_perfcounter.c b/src/amd/vulkan/radv_perfcounter.c index 6b42a4df565..9ee82caac51 100644 --- a/src/amd/vulkan/radv_perfcounter.c +++ b/src/amd/vulkan/radv_perfcounter.c @@ -19,10 +19,10 @@ radv_perfcounter_emit_shaders(struct radv_device *device, struct radeon_cmdbuf * { const struct radv_physical_device *pdev = radv_device_physical(device); - if (pdev->info.gfx_level >= GFX11) { - radeon_set_uconfig_reg(cs, R_036760_SQG_PERFCOUNTER_CTRL, shaders & 0x7f); - } else if (pdev->info.gfx_level >= GFX10) { + if (pdev->info.gfx_level >= GFX10) { radeon_set_uconfig_reg(cs, R_036780_SQ_PERFCOUNTER_CTRL, shaders & 0x7f); + if (pdev->info.gfx_level >= GFX11) + radeon_set_uconfig_reg(cs, R_036760_SQG_PERFCOUNTER_CTRL, shaders & 0x7f); } else { radeon_set_uconfig_reg_seq(cs, R_036780_SQ_PERFCOUNTER_CTRL, 2); radeon_emit(cs, shaders & 0x7f);