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freedreno/ir3: Add encode/decode support for a5xx's LDIB.

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Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12704>
This commit is contained in:
Emma Anholt
2021-09-02 12:56:24 -07:00
committed by Marge Bot
parent 127e845d1d
commit 2b6729883a
3 changed files with 28 additions and 11 deletions
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src/freedreno/ir3/ir3_parser.y
+2 -3
View File
@@ -1034,15 +1034,13 @@ cat6_load: T_OP_LDG { new_instr(OPC_LDG); } cat6_type dst_reg ',' 'g
new_src(0, IR3_REG_IMMED)->iim_val = $8;
} ',' immediate
// TODO some of the cat6 instructions have different syntax for a6xx..
//| T_OP_LDIB { new_instr(OPC_LDIB); } cat6_type dst_reg cat6_offset ',' reg ',' cat6_immed
cat6_store: T_OP_STG { new_instr(OPC_STG); dummy_dst(); } cat6_type 'g' '[' src cat6_imm_offset ']' ',' src ',' immediate
| T_OP_STG_A { new_instr(OPC_STG_A); dummy_dst(); } cat6_type 'g' '[' src cat6_stg_ldg_a6xx_offset ']' ',' src ',' immediate
| T_OP_STP { new_instr(OPC_STP); dummy_dst(); } cat6_type 'p' '[' src cat6_dst_offset ']' ',' src ',' immediate
| T_OP_STL { new_instr(OPC_STL); dummy_dst(); } cat6_type 'l' '[' src cat6_dst_offset ']' ',' src ',' immediate
| T_OP_STLW { new_instr(OPC_STLW); dummy_dst(); } cat6_type 'l' '[' src cat6_dst_offset ']' ',' src ',' immediate
cat6_loadib: T_OP_LDIB { new_instr(OPC_LDIB); } cat6_typed cat6_dim cat6_type '.' cat6_immed dst_reg ',' 'g' '[' immediate ']' ',' src ',' src
cat6_storeib: T_OP_STIB { new_instr(OPC_STIB); dummy_dst(); } cat6_typed cat6_dim cat6_type '.' cat6_immed'g' '[' immediate ']' ',' src ',' src ',' src
cat6_prefetch: T_OP_PREFETCH { new_instr(OPC_PREFETCH); new_dst(0,0); /* dummy dst */ } 'g' '[' src cat6_offset ']' ',' cat6_immed
@@ -1128,6 +1126,7 @@ cat6_todo: T_OP_G2L { new_instr(OPC_G2L); }
| T_OP_RESFMT { new_instr(OPC_RESFMT); }
cat6_instr: cat6_load
| cat6_loadib
| cat6_store
| cat6_storeib
| cat6_prefetch
src/freedreno/ir3/tests/disasm.c
+14 -3
View File
@@ -153,9 +153,18 @@ static const struct test {
/* cat6 */
INSTR_5XX(c6e60000_00010600, "ldgb.untyped.4d.u32.1 r0.x, g[0], r1.x, r0.x"),
INSTR_5XX(d7660204_02000a01, "(sy)stib.typed.2d.u32.1 g[1], r0.x, r0.z, r1.x"),
INSTR_6XX(c0240402_00674100, "stib.b.untyped.1d.u16.1.imm.base0 r0.z, r0.x, 2"),
INSTR_5XX(c6e60000_00010600, "ldgb.untyped.4d.u32.1 r0.x, g[0], r1.x, r0.x"), /* ldgb.a.untyped.1dtype.u32.1 r0.x, g[r1.x], r0.x, 0 */
INSTR_5XX(d7660204_02000a01, "(sy)stib.typed.2d.u32.1 g[1], r0.x, r0.z, r1.x"), /* (sy)stib.a.u32.2d.1 g[r1.x], r0.x, r0.z, 1. r1.x is offset in ibo, r0.x is value*/
/* dEQP-VK.image.load_store.1d_array.r8g8b8a8_unorm */
INSTR_5XX(c1a20006_0600ba01, "ldib.typed.2d.f32.4 r1.z, g[0], r0.z, r1.z"), /* ldib.a.f32.2d.4 r1.z, g[r0.z], r1.z, 0. r0.z is offset in ibo as src. r1.z */
/* dEQP-VK.image.load_store.3d.r32g32b32a32_sint */
INSTR_5XX(c1aa0003_0500fc01, "ldib.typed.3d.s32.4 r0.w, g[0], r0.w, r1.y"), /* ldib.a.s32.3d.4 r0.w, g[r0.w], r1.y, 0. r0.w is offset in ibo as src, and dst */
/* dEQP-VK.binding_model.shader_access.primary_cmd_buf.storage_image.vertex.descriptor_array.3d */
INSTR_5XX(c1a20204_0401fc01, "ldib.typed.3d.f32.4 r1.x, g[1], r1.w, r1.x"), /* ldib.a.f32.3d.4 r1.x, g[r1.w], r1.x, 1 */
/* dEQP-VK.binding_model.shader_access.secondary_cmd_buf.with_push.storage_texel_buffer.vertex_fragment.single_descriptor.offset_zero */
INSTR_5XX(c1a20005_0501be01, "ldib.typed.4d.f32.4 r1.y, g[0], r1.z, r1.y"), /* ldib.a.f32.1dtype.4 r1.y, g[r1.z], r1.y, 0 */
/* dEQP-VK.texture.filtering.cube.formats.r8g8b8a8_snorm_nearest */
INSTR_5XX(c1a60200_0000ba01, "ldib.typed.2d.u32.4 r0.x, g[1], r0.z, r0.x"), /* ldib.a.u32.2d.4 r0.x, g[r0.z], r0.x, 1 */
// TODO is this a real instruction? Or float -6.0 ?
// INSTR_6XX(c0c00000_00000000, "stg.f16 g[hr0.x], hr0.x, hr0.x", .parse_fail=true),
@@ -194,6 +203,8 @@ static const struct test {
/* dEQP-VK.image.image_size.cube_array.readonly_writeonly_1x1x12 */
INSTR_6XX(c0260200_03676100, "stib.b.untyped.1d.u32.3.imm.base0 r0.x, r0.w, 1"), /* stib.untyped.u32.1d.3.mode4.base0 r0.x, r0.w, 1 */
INSTR_6XX(c0240402_00674100, "stib.b.untyped.1d.u16.1.imm.base0 r0.z, r0.x, 2"),
#if 0
/* TODO blob sometimes/frequently sets b0, although there does not seem
* to be an obvious pattern and our encoding never sets it. AFAICT it
src/freedreno/isa/ir3-cat6.xml
+12 -5
View File
@@ -400,14 +400,12 @@ SOFTWARE.
</encode>
</bitset>
<!-- ldgb.untyped.4d.f32.4 r0.x, g[0], r0.x, r1.z -->
<bitset name="ldgb" extends="#instruction-cat6-a3xx-ibo">
<bitset name="#instruction-cat6-a3xx-ibo-load" extends="#instruction-cat6-a3xx-ibo">
<display>
{SY}{JP}{NAME}.{TYPED}.{D}d.{TYPE}.{TYPE_SIZE} {DST}, g[{SSBO}], {SRC1}, {SRC2}
</display>
<gen max="599"/>
<pattern pos="0" >x</pattern> <!-- .a -->
<pattern low="1" high="8" >xxxxxxxx</pattern> <!-- SRC3 -->
<field low="14" high="21" name="SRC1" type="#cat6-src">
<param name="SRC1_IM" as="SRC_IM"/>
@@ -418,8 +416,7 @@ SOFTWARE.
<param name="SRC2_IM" as="SRC_IM"/>
</field>
<field low="32" high="39" name="DST" type="#reg-gpr"/>
<pattern pos="40" >0</pattern> <!-- .rck -->
<pattern low="54" high="58">11011</pattern> <!-- OPC -->
<pattern pos="40" >x</pattern> <!-- .rck -->
<encode>
<map name="SRC1">src->srcs[1]</map>
<map name="SRC1_IM">!!(src->srcs[1]->flags &amp; IR3_REG_IMMED)</map>
@@ -428,6 +425,16 @@ SOFTWARE.
</encode>
</bitset>
<bitset name="ldgb" extends="#instruction-cat6-a3xx-ibo-load">
<pattern low="54" high="58">11011</pattern> <!-- OPC -->
<pattern pos="0" >x</pattern> <!-- .a -->
</bitset>
<bitset name="ldib" extends="#instruction-cat6-a3xx-ibo-load">
<pattern low="54" high="58">00110</pattern> <!-- OPC -->
<pattern pos="0" >1</pattern> <!-- .a -->
</bitset>
<bitset name="#instruction-cat6-a3xx-ibo-store" extends="#instruction-cat6-a3xx-ibo">
<display>
{SY}{JP}{NAME}.{TYPED}.{D}d.{TYPE}.{TYPE_SIZE} g[{SSBO}], {SRC1}, {SRC2}, {SRC3}