AlexIndustrial/mesa
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

radv: drop EXT or KHR suffixes for stuff promoted in Vulkan 1.3

Browse Source 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15663>
This commit is contained in:
Samuel Pitoiset
2022-03-30 10:28:56 +02:00
committed by Marge Bot
parent e8a63cf61e
commit 2b18234e61
28 changed files with 487 additions and 489 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/amd/vulkan/layers/radv_sqtt_layer.c
+24 -24
View File
@@ -496,9 +496,9 @@ sqtt_CmdDispatchIndirect(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDevic
}
VKAPI_ATTR void VKAPI_CALL
sqtt_CmdCopyBuffer2KHR(VkCommandBuffer commandBuffer, const VkCopyBufferInfo2KHR *pCopyBufferInfo)
sqtt_CmdCopyBuffer2(VkCommandBuffer commandBuffer, const VkCopyBufferInfo2 *pCopyBufferInfo)
{
EVENT_MARKER_ALIAS(CopyBuffer2KHR, CopyBuffer, commandBuffer, pCopyBufferInfo);
EVENT_MARKER_ALIAS(CopyBuffer2, CopyBuffer, commandBuffer, pCopyBufferInfo);
}
VKAPI_ATTR void VKAPI_CALL
@@ -516,31 +516,31 @@ sqtt_CmdUpdateBuffer(VkCommandBuffer commandBuffer, VkBuffer dstBuffer, VkDevice
}
VKAPI_ATTR void VKAPI_CALL
sqtt_CmdCopyImage2KHR(VkCommandBuffer commandBuffer, const VkCopyImageInfo2KHR *pCopyImageInfo)
sqtt_CmdCopyImage2(VkCommandBuffer commandBuffer, const VkCopyImageInfo2 *pCopyImageInfo)
{
EVENT_MARKER_ALIAS(CopyImage2KHR, CopyImage, commandBuffer, pCopyImageInfo);
EVENT_MARKER_ALIAS(CopyImage2, CopyImage, commandBuffer, pCopyImageInfo);
}
VKAPI_ATTR void VKAPI_CALL
sqtt_CmdCopyBufferToImage2KHR(VkCommandBuffer commandBuffer,
const VkCopyBufferToImageInfo2KHR *pCopyBufferToImageInfo)
sqtt_CmdCopyBufferToImage2(VkCommandBuffer commandBuffer,
const VkCopyBufferToImageInfo2 *pCopyBufferToImageInfo)
{
EVENT_MARKER_ALIAS(CopyBufferToImage2KHR, CopyBufferToImage, commandBuffer,
EVENT_MARKER_ALIAS(CopyBufferToImage2, CopyBufferToImage, commandBuffer,
pCopyBufferToImageInfo);
}
VKAPI_ATTR void VKAPI_CALL
sqtt_CmdCopyImageToBuffer2KHR(VkCommandBuffer commandBuffer,
const VkCopyImageToBufferInfo2KHR *pCopyImageToBufferInfo)
sqtt_CmdCopyImageToBuffer2(VkCommandBuffer commandBuffer,
const VkCopyImageToBufferInfo2 *pCopyImageToBufferInfo)
{
EVENT_MARKER_ALIAS(CopyImageToBuffer2KHR, CopyImageToBuffer, commandBuffer,
EVENT_MARKER_ALIAS(CopyImageToBuffer2, CopyImageToBuffer, commandBuffer,
pCopyImageToBufferInfo);
}
VKAPI_ATTR void VKAPI_CALL
sqtt_CmdBlitImage2KHR(VkCommandBuffer commandBuffer, const VkBlitImageInfo2KHR *pBlitImageInfo)
sqtt_CmdBlitImage2(VkCommandBuffer commandBuffer, const VkBlitImageInfo2 *pBlitImageInfo)
{
EVENT_MARKER_ALIAS(BlitImage2KHR, BlitImage, commandBuffer, pBlitImageInfo);
EVENT_MARKER_ALIAS(BlitImage2, BlitImage, commandBuffer, pBlitImageInfo);
}
VKAPI_ATTR void VKAPI_CALL
@@ -570,25 +570,25 @@ sqtt_CmdClearAttachments(VkCommandBuffer commandBuffer, uint32_t attachmentCount
}
VKAPI_ATTR void VKAPI_CALL
sqtt_CmdResolveImage2KHR(VkCommandBuffer commandBuffer,
const VkResolveImageInfo2KHR *pResolveImageInfo)
sqtt_CmdResolveImage2(VkCommandBuffer commandBuffer,
const VkResolveImageInfo2 *pResolveImageInfo)
{
EVENT_MARKER_ALIAS(ResolveImage2KHR, ResolveImage, commandBuffer, pResolveImageInfo);
EVENT_MARKER_ALIAS(ResolveImage2, ResolveImage, commandBuffer, pResolveImageInfo);
}
VKAPI_ATTR void VKAPI_CALL
sqtt_CmdWaitEvents2KHR(VkCommandBuffer commandBuffer, uint32_t eventCount, const VkEvent* pEvents,
const VkDependencyInfoKHR* pDependencyInfos)
sqtt_CmdWaitEvents2(VkCommandBuffer commandBuffer, uint32_t eventCount, const VkEvent* pEvents,
const VkDependencyInfo* pDependencyInfos)
{
EVENT_MARKER_ALIAS(WaitEvents2KHR, WaitEvents, commandBuffer, eventCount, pEvents,
EVENT_MARKER_ALIAS(WaitEvents2, WaitEvents, commandBuffer, eventCount, pEvents,
pDependencyInfos);
}
VKAPI_ATTR void VKAPI_CALL
sqtt_CmdPipelineBarrier2KHR(VkCommandBuffer commandBuffer,
const VkDependencyInfoKHR* pDependencyInfo)
sqtt_CmdPipelineBarrier2(VkCommandBuffer commandBuffer,
const VkDependencyInfo* pDependencyInfo)
{
EVENT_MARKER_ALIAS(PipelineBarrier2KHR, PipelineBarrier, commandBuffer, pDependencyInfo);
EVENT_MARKER_ALIAS(PipelineBarrier2, PipelineBarrier, commandBuffer, pDependencyInfo);
}
VKAPI_ATTR void VKAPI_CALL
@@ -666,10 +666,10 @@ sqtt_CmdEndQuery(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t
}
VKAPI_ATTR void VKAPI_CALL
sqtt_CmdWriteTimestamp2KHR(VkCommandBuffer commandBuffer, VkPipelineStageFlags2KHR stage,
VkQueryPool queryPool, uint32_t query)
sqtt_CmdWriteTimestamp2(VkCommandBuffer commandBuffer, VkPipelineStageFlags2 stage,
VkQueryPool queryPool, uint32_t query)
{
API_MARKER_ALIAS(WriteTimestamp2KHR, WriteTimestamp, commandBuffer, stage, queryPool, query);
API_MARKER_ALIAS(WriteTimestamp2, WriteTimestamp, commandBuffer, stage, queryPool, query);
}
VKAPI_ATTR void VKAPI_CALL
src/amd/vulkan/radv_acceleration_structure.c
+4 -4
View File
@@ -1817,9 +1817,9 @@ radv_CmdBuildAccelerationStructuresKHR(
if (!progress) {
cmd_buffer->state.flush_bits |=
RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
radv_src_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_WRITE_BIT_KHR, NULL) |
radv_src_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_WRITE_BIT, NULL) |
radv_dst_access_flush(cmd_buffer,
VK_ACCESS_2_SHADER_READ_BIT_KHR | VK_ACCESS_2_SHADER_WRITE_BIT_KHR, NULL);
VK_ACCESS_2_SHADER_READ_BIT | VK_ACCESS_2_SHADER_WRITE_BIT, NULL);
}
progress = true;
uint32_t dst_node_count = MAX2(1, DIV_ROUND_UP(bvh_states[i].node_count, 4));
@@ -1907,7 +1907,7 @@ radv_CmdCopyAccelerationStructureKHR(VkCommandBuffer commandBuffer,
VK_SHADER_STAGE_COMPUTE_BIT, 0, sizeof(consts), &consts);
cmd_buffer->state.flush_bits |=
radv_dst_access_flush(cmd_buffer, VK_ACCESS_2_INDIRECT_COMMAND_READ_BIT_KHR, NULL);
radv_dst_access_flush(cmd_buffer, VK_ACCESS_2_INDIRECT_COMMAND_READ_BIT, NULL);
radv_indirect_dispatch(cmd_buffer, src->bo,
src_addr + offsetof(struct radv_accel_struct_header, copy_dispatch_size));
@@ -2056,7 +2056,7 @@ radv_CmdCopyAccelerationStructureToMemoryKHR(
VK_SHADER_STAGE_COMPUTE_BIT, 0, sizeof(consts), &consts);
cmd_buffer->state.flush_bits |=
radv_dst_access_flush(cmd_buffer, VK_ACCESS_2_INDIRECT_COMMAND_READ_BIT_KHR, NULL);
radv_dst_access_flush(cmd_buffer, VK_ACCESS_2_INDIRECT_COMMAND_READ_BIT, NULL);
radv_indirect_dispatch(cmd_buffer, src->bo,
src_addr + offsetof(struct radv_accel_struct_header, copy_dispatch_size));
src/amd/vulkan/radv_cmd_buffer.c
+127 -129
View File
@@ -3825,39 +3825,39 @@ radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, const struct radv_d
}
static void
radv_stage_flush(struct radv_cmd_buffer *cmd_buffer, VkPipelineStageFlags2KHR src_stage_mask)
radv_stage_flush(struct radv_cmd_buffer *cmd_buffer, VkPipelineStageFlags2 src_stage_mask)
{
if (src_stage_mask & (VK_PIPELINE_STAGE_2_COPY_BIT_KHR |
VK_PIPELINE_STAGE_2_RESOLVE_BIT_KHR |
VK_PIPELINE_STAGE_2_BLIT_BIT_KHR |
VK_PIPELINE_STAGE_2_CLEAR_BIT_KHR)) {
if (src_stage_mask & (VK_PIPELINE_STAGE_2_COPY_BIT |
VK_PIPELINE_STAGE_2_RESOLVE_BIT |
VK_PIPELINE_STAGE_2_BLIT_BIT |
VK_PIPELINE_STAGE_2_CLEAR_BIT)) {
/* Be conservative for now. */
src_stage_mask |= VK_PIPELINE_STAGE_2_TRANSFER_BIT_KHR;
src_stage_mask |= VK_PIPELINE_STAGE_2_TRANSFER_BIT;
}
if (src_stage_mask &
(VK_PIPELINE_STAGE_2_COMPUTE_SHADER_BIT_KHR | VK_PIPELINE_STAGE_2_TRANSFER_BIT_KHR |
(VK_PIPELINE_STAGE_2_COMPUTE_SHADER_BIT | VK_PIPELINE_STAGE_2_TRANSFER_BIT |
VK_PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR |
VK_PIPELINE_STAGE_2_RAY_TRACING_SHADER_BIT_KHR | VK_PIPELINE_STAGE_2_BOTTOM_OF_PIPE_BIT_KHR |
VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR)) {
VK_PIPELINE_STAGE_2_RAY_TRACING_SHADER_BIT_KHR | VK_PIPELINE_STAGE_2_BOTTOM_OF_PIPE_BIT |
VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT)) {
cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
}
if (src_stage_mask &
(VK_PIPELINE_STAGE_2_FRAGMENT_SHADER_BIT_KHR | VK_PIPELINE_STAGE_2_EARLY_FRAGMENT_TESTS_BIT_KHR |
VK_PIPELINE_STAGE_2_LATE_FRAGMENT_TESTS_BIT_KHR | VK_PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT_KHR |
VK_PIPELINE_STAGE_2_TRANSFER_BIT_KHR | VK_PIPELINE_STAGE_2_BOTTOM_OF_PIPE_BIT_KHR |
VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT_KHR | VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT_KHR)) {
(VK_PIPELINE_STAGE_2_FRAGMENT_SHADER_BIT | VK_PIPELINE_STAGE_2_EARLY_FRAGMENT_TESTS_BIT |
VK_PIPELINE_STAGE_2_LATE_FRAGMENT_TESTS_BIT | VK_PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT |
VK_PIPELINE_STAGE_2_TRANSFER_BIT | VK_PIPELINE_STAGE_2_BOTTOM_OF_PIPE_BIT |
VK_PIPELINE_STAGE_2_ALL_GRAPHICS_BIT | VK_PIPELINE_STAGE_2_ALL_COMMANDS_BIT)) {
cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
} else if (src_stage_mask &
(VK_PIPELINE_STAGE_2_DRAW_INDIRECT_BIT_KHR | VK_PIPELINE_STAGE_2_VERTEX_INPUT_BIT_KHR |
VK_PIPELINE_STAGE_2_VERTEX_SHADER_BIT_KHR |
VK_PIPELINE_STAGE_2_TESSELLATION_CONTROL_SHADER_BIT_KHR |
VK_PIPELINE_STAGE_2_TESSELLATION_EVALUATION_SHADER_BIT_KHR |
VK_PIPELINE_STAGE_2_GEOMETRY_SHADER_BIT_KHR |
(VK_PIPELINE_STAGE_2_DRAW_INDIRECT_BIT | VK_PIPELINE_STAGE_2_VERTEX_INPUT_BIT |
VK_PIPELINE_STAGE_2_VERTEX_SHADER_BIT |
VK_PIPELINE_STAGE_2_TESSELLATION_CONTROL_SHADER_BIT |
VK_PIPELINE_STAGE_2_TESSELLATION_EVALUATION_SHADER_BIT |
VK_PIPELINE_STAGE_2_GEOMETRY_SHADER_BIT |
VK_PIPELINE_STAGE_2_MESH_SHADER_BIT_NV |
VK_PIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT |
VK_PIPELINE_STAGE_2_PRE_RASTERIZATION_SHADERS_BIT_KHR)) {
VK_PIPELINE_STAGE_2_PRE_RASTERIZATION_SHADERS_BIT)) {
cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
}
}
@@ -3900,7 +3900,7 @@ can_skip_buffer_l2_flushes(struct radv_device *device)
*/
enum radv_cmd_flush_bits
radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer, VkAccessFlags2KHR src_flags,
radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer, VkAccessFlags2 src_flags,
const struct radv_image *image)
{
bool has_CB_meta = true, has_DB_meta = true;
@@ -3916,9 +3916,9 @@ radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer, VkAccessFlags2KHR src_
u_foreach_bit64(b, src_flags)
{
switch ((VkAccessFlags2KHR)(1 << b)) {
case VK_ACCESS_2_SHADER_WRITE_BIT_KHR:
case VK_ACCESS_2_SHADER_STORAGE_WRITE_BIT_KHR:
switch ((VkAccessFlags2)(1 << b)) {
case VK_ACCESS_2_SHADER_WRITE_BIT:
case VK_ACCESS_2_SHADER_STORAGE_WRITE_BIT:
/* since the STORAGE bit isn't set we know that this is a meta operation.
* on the dst flush side we skip CB/DB flushes without the STORAGE bit, so
* set it here. */
@@ -3942,17 +3942,17 @@ radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer, VkAccessFlags2KHR src_
if (!image_is_coherent)
flush_bits |= RADV_CMD_FLAG_WB_L2;
break;
case VK_ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT_KHR:
case VK_ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT:
flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
if (has_CB_meta)
flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
break;
case VK_ACCESS_2_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT_KHR:
case VK_ACCESS_2_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
if (has_DB_meta)
flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
break;
case VK_ACCESS_2_TRANSFER_WRITE_BIT_KHR:
case VK_ACCESS_2_TRANSFER_WRITE_BIT:
flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_DB;
if (!image_is_coherent)
@@ -3962,7 +3962,7 @@ radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer, VkAccessFlags2KHR src_
if (has_DB_meta)
flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
break;
case VK_ACCESS_2_MEMORY_WRITE_BIT_KHR:
case VK_ACCESS_2_MEMORY_WRITE_BIT:
flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_DB;
if (!image_is_coherent)
@@ -3980,7 +3980,7 @@ radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer, VkAccessFlags2KHR src_
}
enum radv_cmd_flush_bits
radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer, VkAccessFlags2KHR dst_flags,
radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer, VkAccessFlags2 dst_flags,
const struct radv_image *image)
{
bool has_CB_meta = true, has_DB_meta = true;
@@ -4007,22 +4007,22 @@ radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer, VkAccessFlags2KHR dst_
u_foreach_bit64(b, dst_flags)
{
switch ((VkAccessFlags2KHR)(1 << b)) {
case VK_ACCESS_2_INDIRECT_COMMAND_READ_BIT_KHR:
switch ((VkAccessFlags2)(1 << b)) {
case VK_ACCESS_2_INDIRECT_COMMAND_READ_BIT:
/* SMEM loads are used to read compute dispatch size in shaders */
if (!cmd_buffer->device->load_grid_size_from_user_sgpr)
flush_bits |= RADV_CMD_FLAG_INV_SCACHE;
break;
case VK_ACCESS_2_INDEX_READ_BIT_KHR:
case VK_ACCESS_2_INDEX_READ_BIT:
case VK_ACCESS_2_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
break;
case VK_ACCESS_2_UNIFORM_READ_BIT_KHR:
case VK_ACCESS_2_UNIFORM_READ_BIT:
flush_bits |= RADV_CMD_FLAG_INV_VCACHE | RADV_CMD_FLAG_INV_SCACHE;
break;
case VK_ACCESS_2_VERTEX_ATTRIBUTE_READ_BIT_KHR:
case VK_ACCESS_2_INPUT_ATTACHMENT_READ_BIT_KHR:
case VK_ACCESS_2_TRANSFER_READ_BIT_KHR:
case VK_ACCESS_2_TRANSFER_WRITE_BIT_KHR:
case VK_ACCESS_2_VERTEX_ATTRIBUTE_READ_BIT:
case VK_ACCESS_2_INPUT_ATTACHMENT_READ_BIT:
case VK_ACCESS_2_TRANSFER_READ_BIT:
case VK_ACCESS_2_TRANSFER_WRITE_BIT:
flush_bits |= RADV_CMD_FLAG_INV_VCACHE;
if (has_CB_meta || has_DB_meta)
@@ -4030,8 +4030,8 @@ radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer, VkAccessFlags2KHR dst_
if (!image_is_coherent)
flush_bits |= RADV_CMD_FLAG_INV_L2;
break;
case VK_ACCESS_2_SHADER_READ_BIT_KHR:
case VK_ACCESS_2_SHADER_STORAGE_READ_BIT_KHR:
case VK_ACCESS_2_SHADER_READ_BIT:
case VK_ACCESS_2_SHADER_STORAGE_READ_BIT:
flush_bits |= RADV_CMD_FLAG_INV_VCACHE;
/* Unlike LLVM, ACO uses SMEM for SSBOs and we have to
* invalidate the scalar cache. */
@@ -4048,26 +4048,26 @@ radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer, VkAccessFlags2KHR dst_
if (cmd_buffer->device->physical_device->rad_info.chip_class < GFX9)
flush_bits |= RADV_CMD_FLAG_INV_L2;
break;
case VK_ACCESS_2_SHADER_WRITE_BIT_KHR:
case VK_ACCESS_2_SHADER_STORAGE_WRITE_BIT_KHR:
case VK_ACCESS_2_SHADER_WRITE_BIT:
case VK_ACCESS_2_SHADER_STORAGE_WRITE_BIT:
case VK_ACCESS_2_ACCELERATION_STRUCTURE_WRITE_BIT_KHR:
break;
case VK_ACCESS_2_COLOR_ATTACHMENT_READ_BIT_KHR:
case VK_ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT_KHR:
case VK_ACCESS_2_COLOR_ATTACHMENT_READ_BIT:
case VK_ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT:
if (flush_CB)
flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
if (has_CB_meta)
flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
break;
case VK_ACCESS_2_DEPTH_STENCIL_ATTACHMENT_READ_BIT_KHR:
case VK_ACCESS_2_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT_KHR:
case VK_ACCESS_2_DEPTH_STENCIL_ATTACHMENT_READ_BIT:
case VK_ACCESS_2_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT:
if (flush_DB)
flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB;
if (has_DB_meta)
flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB_META;
break;
case VK_ACCESS_2_MEMORY_READ_BIT_KHR:
case VK_ACCESS_2_MEMORY_WRITE_BIT_KHR:
case VK_ACCESS_2_MEMORY_READ_BIT:
case VK_ACCESS_2_MEMORY_WRITE_BIT:
flush_bits |= RADV_CMD_FLAG_INV_VCACHE | RADV_CMD_FLAG_INV_SCACHE;
if (!image_is_coherent)
flush_bits |= RADV_CMD_FLAG_INV_L2;
@@ -4474,7 +4474,7 @@ radv_ResetCommandBuffer(VkCommandBuffer commandBuffer, VkCommandBufferResetFlags
static void
radv_inherit_dynamic_rendering(struct radv_cmd_buffer *cmd_buffer,
const VkCommandBufferInheritanceInfo *inherit_info,
const VkCommandBufferInheritanceRenderingInfoKHR *dyn_info)
const VkCommandBufferInheritanceRenderingInfo *dyn_info)
{
const VkAttachmentSampleCountInfoAMD *sample_info =
vk_find_struct_const(inherit_info->pNext, ATTACHMENT_SAMPLE_COUNT_INFO_AMD);
@@ -4615,9 +4615,9 @@ radv_BeginCommandBuffer(VkCommandBuffer commandBuffer, const VkCommandBufferBegi
assert(pBeginInfo->pInheritanceInfo->subpass < cmd_buffer->state.pass->subpass_count);
subpass = &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
} else {
const VkCommandBufferInheritanceRenderingInfoKHR *dyn_info =
const VkCommandBufferInheritanceRenderingInfo *dyn_info =
vk_find_struct_const(pBeginInfo->pInheritanceInfo->pNext,
COMMAND_BUFFER_INHERITANCE_RENDERING_INFO_KHR);
COMMAND_BUFFER_INHERITANCE_RENDERING_INFO);
if (dyn_info) {
radv_inherit_dynamic_rendering(cmd_buffer, pBeginInfo->pInheritanceInfo, dyn_info);
subpass = &cmd_buffer->state.pass->subpasses[0];
@@ -4655,15 +4655,15 @@ radv_CmdBindVertexBuffers(VkCommandBuffer commandBuffer, uint32_t firstBinding,
uint32_t bindingCount, const VkBuffer *pBuffers,
const VkDeviceSize *pOffsets)
{
radv_CmdBindVertexBuffers2EXT(commandBuffer, firstBinding, bindingCount, pBuffers, pOffsets,
NULL, NULL);
radv_CmdBindVertexBuffers2(commandBuffer, firstBinding, bindingCount, pBuffers, pOffsets,
NULL, NULL);
}
VKAPI_ATTR void VKAPI_CALL
radv_CmdBindVertexBuffers2EXT(VkCommandBuffer commandBuffer, uint32_t firstBinding,
uint32_t bindingCount, const VkBuffer *pBuffers,
const VkDeviceSize *pOffsets, const VkDeviceSize *pSizes,
const VkDeviceSize *pStrides)
radv_CmdBindVertexBuffers2(VkCommandBuffer commandBuffer, uint32_t firstBinding,
uint32_t bindingCount, const VkBuffer *pBuffers,
const VkDeviceSize *pOffsets, const VkDeviceSize *pSizes,
const VkDeviceSize *pStrides)
{
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;
@@ -4934,7 +4934,7 @@ radv_CmdPushDescriptorSetKHR(VkCommandBuffer commandBuffer, VkPipelineBindPoint
*/
for (int i = 0; i < descriptorWriteCount; i++) {
ASSERTED const VkWriteDescriptorSet *writeset = &pDescriptorWrites[i];
assert(writeset->descriptorType != VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT);
assert(writeset->descriptorType != VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK);
}
radv_cmd_update_descriptor_sets(cmd_buffer->device, cmd_buffer,
@@ -5004,8 +5004,8 @@ radv_EndCommandBuffer(VkCommandBuffer commandBuffer)
if (cmd_buffer->state.rb_noncoherent_dirty && can_skip_buffer_l2_flushes(cmd_buffer->device))
cmd_buffer->state.flush_bits |= radv_src_access_flush(
cmd_buffer,
VK_ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT_KHR |
VK_ACCESS_2_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT_KHR,
VK_ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT |
VK_ACCESS_2_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT,
NULL);
/* Since NGG streamout uses GDS, we need to make GDS idle when
@@ -5346,7 +5346,7 @@ radv_CmdSetLineStippleEXT(VkCommandBuffer commandBuffer, uint32_t lineStippleFac
}
VKAPI_ATTR void VKAPI_CALL
radv_CmdSetCullModeEXT(VkCommandBuffer commandBuffer, VkCullModeFlags cullMode)
radv_CmdSetCullMode(VkCommandBuffer commandBuffer, VkCullModeFlags cullMode)
{
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
struct radv_cmd_state *state = &cmd_buffer->state;
@@ -5357,7 +5357,7 @@ radv_CmdSetCullModeEXT(VkCommandBuffer commandBuffer, VkCullModeFlags cullMode)
}
VKAPI_ATTR void VKAPI_CALL
radv_CmdSetFrontFaceEXT(VkCommandBuffer commandBuffer, VkFrontFace frontFace)
radv_CmdSetFrontFace(VkCommandBuffer commandBuffer, VkFrontFace frontFace)
{
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
struct radv_cmd_state *state = &cmd_buffer->state;
@@ -5368,8 +5368,7 @@ radv_CmdSetFrontFaceEXT(VkCommandBuffer commandBuffer, VkFrontFace frontFace)
}
VKAPI_ATTR void VKAPI_CALL
radv_CmdSetPrimitiveTopologyEXT(VkCommandBuffer commandBuffer,
VkPrimitiveTopology primitiveTopology)
radv_CmdSetPrimitiveTopology(VkCommandBuffer commandBuffer, VkPrimitiveTopology primitiveTopology)
{
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
struct radv_cmd_state *state = &cmd_buffer->state;
@@ -5381,21 +5380,21 @@ radv_CmdSetPrimitiveTopologyEXT(VkCommandBuffer commandBuffer,
}
VKAPI_ATTR void VKAPI_CALL
radv_CmdSetViewportWithCountEXT(VkCommandBuffer commandBuffer, uint32_t viewportCount,
const VkViewport *pViewports)
radv_CmdSetViewportWithCount(VkCommandBuffer commandBuffer, uint32_t viewportCount,
const VkViewport *pViewports)
{
radv_CmdSetViewport(commandBuffer, 0, viewportCount, pViewports);
}
VKAPI_ATTR void VKAPI_CALL
radv_CmdSetScissorWithCountEXT(VkCommandBuffer commandBuffer, uint32_t scissorCount,
const VkRect2D *pScissors)
radv_CmdSetScissorWithCount(VkCommandBuffer commandBuffer, uint32_t scissorCount,
const VkRect2D *pScissors)
{
radv_CmdSetScissor(commandBuffer, 0, scissorCount, pScissors);
}
VKAPI_ATTR void VKAPI_CALL
radv_CmdSetDepthTestEnableEXT(VkCommandBuffer commandBuffer, VkBool32 depthTestEnable)
radv_CmdSetDepthTestEnable(VkCommandBuffer commandBuffer, VkBool32 depthTestEnable)
{
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
@@ -5407,7 +5406,7 @@ radv_CmdSetDepthTestEnableEXT(VkCommandBuffer commandBuffer, VkBool32 depthTestE
}
VKAPI_ATTR void VKAPI_CALL
radv_CmdSetDepthWriteEnableEXT(VkCommandBuffer commandBuffer, VkBool32 depthWriteEnable)
radv_CmdSetDepthWriteEnable(VkCommandBuffer commandBuffer, VkBool32 depthWriteEnable)
{
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
struct radv_cmd_state *state = &cmd_buffer->state;
@@ -5418,7 +5417,7 @@ radv_CmdSetDepthWriteEnableEXT(VkCommandBuffer commandBuffer, VkBool32 depthWrit
}
VKAPI_ATTR void VKAPI_CALL
radv_CmdSetDepthCompareOpEXT(VkCommandBuffer commandBuffer, VkCompareOp depthCompareOp)
radv_CmdSetDepthCompareOp(VkCommandBuffer commandBuffer, VkCompareOp depthCompareOp)
{
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
struct radv_cmd_state *state = &cmd_buffer->state;
@@ -5429,7 +5428,7 @@ radv_CmdSetDepthCompareOpEXT(VkCommandBuffer commandBuffer, VkCompareOp depthCom
}
VKAPI_ATTR void VKAPI_CALL
radv_CmdSetDepthBoundsTestEnableEXT(VkCommandBuffer commandBuffer, VkBool32 depthBoundsTestEnable)
radv_CmdSetDepthBoundsTestEnable(VkCommandBuffer commandBuffer, VkBool32 depthBoundsTestEnable)
{
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
struct radv_cmd_state *state = &cmd_buffer->state;
@@ -5440,7 +5439,7 @@ radv_CmdSetDepthBoundsTestEnableEXT(VkCommandBuffer commandBuffer, VkBool32 dept
}
VKAPI_ATTR void VKAPI_CALL
radv_CmdSetStencilTestEnableEXT(VkCommandBuffer commandBuffer, VkBool32 stencilTestEnable)
radv_CmdSetStencilTestEnable(VkCommandBuffer commandBuffer, VkBool32 stencilTestEnable)
{
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
struct radv_cmd_state *state = &cmd_buffer->state;
@@ -5451,9 +5450,9 @@ radv_CmdSetStencilTestEnableEXT(VkCommandBuffer commandBuffer, VkBool32 stencilT
}
VKAPI_ATTR void VKAPI_CALL
radv_CmdSetStencilOpEXT(VkCommandBuffer commandBuffer, VkStencilFaceFlags faceMask,
VkStencilOp failOp, VkStencilOp passOp, VkStencilOp depthFailOp,
VkCompareOp compareOp)
radv_CmdSetStencilOp(VkCommandBuffer commandBuffer, VkStencilFaceFlags faceMask,
VkStencilOp failOp, VkStencilOp passOp, VkStencilOp depthFailOp,
VkCompareOp compareOp)
{
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
struct radv_cmd_state *state = &cmd_buffer->state;
@@ -5490,7 +5489,7 @@ radv_CmdSetFragmentShadingRateKHR(VkCommandBuffer commandBuffer, const VkExtent2
}
VKAPI_ATTR void VKAPI_CALL
radv_CmdSetDepthBiasEnableEXT(VkCommandBuffer commandBuffer, VkBool32 depthBiasEnable)
radv_CmdSetDepthBiasEnable(VkCommandBuffer commandBuffer, VkBool32 depthBiasEnable)
{
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
struct radv_cmd_state *state = &cmd_buffer->state;
@@ -5501,7 +5500,7 @@ radv_CmdSetDepthBiasEnableEXT(VkCommandBuffer commandBuffer, VkBool32 depthBiasE
}
VKAPI_ATTR void VKAPI_CALL
radv_CmdSetPrimitiveRestartEnableEXT(VkCommandBuffer commandBuffer, VkBool32 primitiveRestartEnable)
radv_CmdSetPrimitiveRestartEnable(VkCommandBuffer commandBuffer, VkBool32 primitiveRestartEnable)
{
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
struct radv_cmd_state *state = &cmd_buffer->state;
@@ -5512,8 +5511,7 @@ radv_CmdSetPrimitiveRestartEnableEXT(VkCommandBuffer commandBuffer, VkBool32 pri
}
VKAPI_ATTR void VKAPI_CALL
radv_CmdSetRasterizerDiscardEnableEXT(VkCommandBuffer commandBuffer,
VkBool32 rasterizerDiscardEnable)
radv_CmdSetRasterizerDiscardEnable(VkCommandBuffer commandBuffer, VkBool32 rasterizerDiscardEnable)
{
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
struct radv_cmd_state *state = &cmd_buffer->state;
@@ -7684,7 +7682,7 @@ radv_CmdEndRenderPass2(VkCommandBuffer commandBuffer, const VkSubpassEndInfo *pS
}
VKAPI_ATTR void VKAPI_CALL
radv_CmdBeginRenderingKHR(VkCommandBuffer commandBuffer, const VkRenderingInfoKHR *pRenderingInfo)
radv_CmdBeginRendering(VkCommandBuffer commandBuffer, const VkRenderingInfo *pRenderingInfo)
{
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
const VkRenderingFragmentShadingRateAttachmentInfoKHR *vrs_info = vk_find_struct_const(
@@ -7724,7 +7722,7 @@ radv_CmdBeginRenderingKHR(VkCommandBuffer commandBuffer, const VkRenderingInfoKH
if (pRenderingInfo->pColorAttachments[i].imageView == VK_NULL_HANDLE)
continue;
const VkRenderingAttachmentInfoKHR *info = &pRenderingInfo->pColorAttachments[i];
const VkRenderingAttachmentInfo *info = &pRenderingInfo->pColorAttachments[i];
RADV_FROM_HANDLE(radv_image_view, iview, info->imageView);
color_refs[i] = (VkAttachmentReference2){.sType = VK_STRUCTURE_TYPE_ATTACHMENT_REFERENCE_2,
.attachment = att_count,
@@ -7744,14 +7742,14 @@ radv_CmdBeginRenderingKHR(VkCommandBuffer commandBuffer, const VkRenderingInfoKH
att->initialLayout = info->imageLayout;
att->finalLayout = info->imageLayout;
if (pRenderingInfo->flags & VK_RENDERING_RESUMING_BIT_KHR)
if (pRenderingInfo->flags & VK_RENDERING_RESUMING_BIT)
att->loadOp = VK_ATTACHMENT_LOAD_OP_LOAD;
if (pRenderingInfo->flags & VK_RENDERING_SUSPENDING_BIT_KHR)
if (pRenderingInfo->flags & VK_RENDERING_SUSPENDING_BIT)
att->storeOp = VK_ATTACHMENT_STORE_OP_STORE;
if (info->resolveMode != VK_RESOLVE_MODE_NONE &&
!(pRenderingInfo->flags & VK_RENDERING_SUSPENDING_BIT_KHR)) {
!(pRenderingInfo->flags & VK_RENDERING_SUSPENDING_BIT)) {
RADV_FROM_HANDLE(radv_image_view, resolve_iview, info->resolveImageView);
color_resolve_refs[i] =
(VkAttachmentReference2){.sType = VK_STRUCTURE_TYPE_ATTACHMENT_REFERENCE_2,
@@ -7774,7 +7772,7 @@ radv_CmdBeginRenderingKHR(VkCommandBuffer commandBuffer, const VkRenderingInfoKH
}
if (pRenderingInfo->pDepthAttachment || pRenderingInfo->pStencilAttachment) {
const VkRenderingAttachmentInfoKHR *common_info = pRenderingInfo->pDepthAttachment
const VkRenderingAttachmentInfo *common_info = pRenderingInfo->pDepthAttachment
? pRenderingInfo->pDepthAttachment
: pRenderingInfo->pStencilAttachment;
RADV_FROM_HANDLE(radv_image_view, iview, common_info->imageView);
@@ -7818,12 +7816,12 @@ radv_CmdBeginRenderingKHR(VkCommandBuffer commandBuffer, const VkRenderingInfoKH
att->stencilStoreOp = VK_ATTACHMENT_STORE_OP_STORE;
}
if (pRenderingInfo->flags & VK_RENDERING_RESUMING_BIT_KHR) {
if (pRenderingInfo->flags & VK_RENDERING_RESUMING_BIT) {
att->loadOp = VK_ATTACHMENT_LOAD_OP_LOAD;
att->stencilLoadOp = VK_ATTACHMENT_LOAD_OP_LOAD;
}
if (pRenderingInfo->flags & VK_RENDERING_SUSPENDING_BIT_KHR) {
if (pRenderingInfo->flags & VK_RENDERING_SUSPENDING_BIT) {
att->storeOp = VK_ATTACHMENT_STORE_OP_STORE;
att->stencilStoreOp = VK_ATTACHMENT_STORE_OP_STORE;
}
@@ -7849,7 +7847,7 @@ radv_CmdBeginRenderingKHR(VkCommandBuffer commandBuffer, const VkRenderingInfoKH
pRenderingInfo->pDepthAttachment->resolveMode != VK_RESOLVE_MODE_NONE) ||
(pRenderingInfo->pStencilAttachment &&
pRenderingInfo->pStencilAttachment->resolveMode != VK_RESOLVE_MODE_NONE)) &&
!(pRenderingInfo->flags & VK_RENDERING_SUSPENDING_BIT_KHR)) {
!(pRenderingInfo->flags & VK_RENDERING_SUSPENDING_BIT)) {
RADV_FROM_HANDLE(radv_image_view, resolve_iview, common_info->resolveImageView);
ds_resolve_ref =
(VkAttachmentReference2){.sType = VK_STRUCTURE_TYPE_ATTACHMENT_REFERENCE_2,
@@ -7987,7 +7985,7 @@ radv_CmdBeginRenderingKHR(VkCommandBuffer commandBuffer, const VkRenderingInfoKH
const VkSubpassBeginInfo pass_begin_info = {
.sType = VK_STRUCTURE_TYPE_SUBPASS_BEGIN_INFO,
.contents = (pRenderingInfo->flags & VK_RENDERING_CONTENTS_SECONDARY_COMMAND_BUFFERS_BIT_KHR)
.contents = (pRenderingInfo->flags & VK_RENDERING_CONTENTS_SECONDARY_COMMAND_BUFFERS_BIT)
? VK_SUBPASS_CONTENTS_SECONDARY_COMMAND_BUFFERS
: VK_SUBPASS_CONTENTS_INLINE,
};
@@ -7996,7 +7994,7 @@ radv_CmdBeginRenderingKHR(VkCommandBuffer commandBuffer, const VkRenderingInfoKH
}
VKAPI_ATTR void VKAPI_CALL
radv_CmdEndRenderingKHR(VkCommandBuffer commandBuffer)
radv_CmdEndRendering(VkCommandBuffer commandBuffer)
{
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
struct radv_render_pass *pass = cmd_buffer->state.pass;
@@ -8032,14 +8030,14 @@ radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer, struct radv_image *ima
/* Transitioning from LAYOUT_UNDEFINED layout not everyone is consistent
* in considering previous rendering work for WAW hazards. */
state->flush_bits |=
radv_src_access_flush(cmd_buffer, VK_ACCESS_2_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT_KHR, image);
radv_src_access_flush(cmd_buffer, VK_ACCESS_2_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT, image);
if (image->planes[0].surface.has_stencil &&
!(range->aspectMask == (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT))) {
/* Flush caches before performing a separate aspect initialization because it's a
* read-modify-write operation.
*/
state->flush_bits |= radv_dst_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_READ_BIT_KHR, image);
state->flush_bits |= radv_dst_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_READ_BIT, image);
}
state->flush_bits |= radv_clear_htile(cmd_buffer, image, range, htile_value);
@@ -8174,7 +8172,7 @@ radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer, struct radv_i
* consistent in considering previous rendering work for WAW hazards.
*/
cmd_buffer->state.flush_bits |=
radv_src_access_flush(cmd_buffer, VK_ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT_KHR, image);
radv_src_access_flush(cmd_buffer, VK_ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT, image);
if (radv_image_has_cmask(image)) {
uint32_t value;
@@ -8370,13 +8368,13 @@ radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer, struct radv_ima
}
static void
radv_barrier(struct radv_cmd_buffer *cmd_buffer, const VkDependencyInfoKHR *dep_info,
radv_barrier(struct radv_cmd_buffer *cmd_buffer, const VkDependencyInfo *dep_info,
enum rgp_barrier_reason reason)
{
enum radv_cmd_flush_bits src_flush_bits = 0;
enum radv_cmd_flush_bits dst_flush_bits = 0;
VkPipelineStageFlags2KHR src_stage_mask = 0;
VkPipelineStageFlags2KHR dst_stage_mask = 0;
VkPipelineStageFlags2 src_stage_mask = 0;
VkPipelineStageFlags2 dst_stage_mask = 0;
if (cmd_buffer->state.subpass)
radv_mark_noncoherent_rb(cmd_buffer);
@@ -8415,15 +8413,15 @@ radv_barrier(struct radv_cmd_buffer *cmd_buffer, const VkDependencyInfoKHR *dep_
/* The Vulkan spec 1.1.98 says:
*
* "An execution dependency with only
* VK_PIPELINE_STAGE_2_BOTTOM_OF_PIPE_BIT_KHR in the destination stage mask
* VK_PIPELINE_STAGE_2_BOTTOM_OF_PIPE_BIT in the destination stage mask
* will only prevent that stage from executing in subsequently
* submitted commands. As this stage does not perform any actual
* execution, this is not observable - in effect, it does not delay
* processing of subsequent commands. Similarly an execution dependency
* with only VK_PIPELINE_STAGE_2_TOP_OF_PIPE_BIT_KHR in the source stage mask
* with only VK_PIPELINE_STAGE_2_TOP_OF_PIPE_BIT in the source stage mask
* will effectively not wait for any prior commands to complete."
*/
if (dst_stage_mask != VK_PIPELINE_STAGE_2_BOTTOM_OF_PIPE_BIT_KHR)
if (dst_stage_mask != VK_PIPELINE_STAGE_2_BOTTOM_OF_PIPE_BIT)
radv_stage_flush(cmd_buffer, src_stage_mask);
cmd_buffer->state.flush_bits |= src_flush_bits;
@@ -8456,9 +8454,9 @@ radv_barrier(struct radv_cmd_buffer *cmd_buffer, const VkDependencyInfoKHR *dep_
/* Make sure CP DMA is idle because the driver might have performed a DMA operation for copying a
* buffer (or a MSAA image using FMASK) or updated a buffer which is a transfer operation.
*/
if (src_stage_mask & (VK_PIPELINE_STAGE_2_COPY_BIT_KHR |
VK_PIPELINE_STAGE_2_TRANSFER_BIT_KHR |
VK_PIPELINE_STAGE_2_BOTTOM_OF_PIPE_BIT_KHR))
if (src_stage_mask & (VK_PIPELINE_STAGE_2_COPY_BIT |
VK_PIPELINE_STAGE_2_TRANSFER_BIT |
VK_PIPELINE_STAGE_2_BOTTOM_OF_PIPE_BIT))
si_cp_dma_wait_for_idle(cmd_buffer);
cmd_buffer->state.flush_bits |= dst_flush_bits;
@@ -8467,8 +8465,8 @@ radv_barrier(struct radv_cmd_buffer *cmd_buffer, const VkDependencyInfoKHR *dep_
}
VKAPI_ATTR void VKAPI_CALL
radv_CmdPipelineBarrier2KHR(VkCommandBuffer commandBuffer,
const VkDependencyInfoKHR *pDependencyInfo)
radv_CmdPipelineBarrier2(VkCommandBuffer commandBuffer,
const VkDependencyInfo *pDependencyInfo)
{
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
@@ -8477,7 +8475,7 @@ radv_CmdPipelineBarrier2KHR(VkCommandBuffer commandBuffer,
static void
write_event(struct radv_cmd_buffer *cmd_buffer, struct radv_event *event,
VkPipelineStageFlags2KHR stageMask, unsigned value)
VkPipelineStageFlags2 stageMask, unsigned value)
{
struct radeon_cmdbuf *cs = cmd_buffer->cs;
uint64_t va = radv_buffer_get_va(event->bo);
@@ -8488,39 +8486,39 @@ write_event(struct radv_cmd_buffer *cmd_buffer, struct radv_event *event,
ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 28);
if (stageMask & (VK_PIPELINE_STAGE_2_COPY_BIT_KHR |
VK_PIPELINE_STAGE_2_RESOLVE_BIT_KHR |
VK_PIPELINE_STAGE_2_BLIT_BIT_KHR |
VK_PIPELINE_STAGE_2_CLEAR_BIT_KHR)) {
if (stageMask & (VK_PIPELINE_STAGE_2_COPY_BIT |
VK_PIPELINE_STAGE_2_RESOLVE_BIT |
VK_PIPELINE_STAGE_2_BLIT_BIT |
VK_PIPELINE_STAGE_2_CLEAR_BIT)) {
/* Be conservative for now. */
stageMask |= VK_PIPELINE_STAGE_2_TRANSFER_BIT_KHR;
stageMask |= VK_PIPELINE_STAGE_2_TRANSFER_BIT;
}
/* Flags that only require a top-of-pipe event. */
VkPipelineStageFlags2KHR top_of_pipe_flags = VK_PIPELINE_STAGE_2_TOP_OF_PIPE_BIT_KHR;
VkPipelineStageFlags2 top_of_pipe_flags = VK_PIPELINE_STAGE_2_TOP_OF_PIPE_BIT;
/* Flags that only require a post-index-fetch event. */
VkPipelineStageFlags2KHR post_index_fetch_flags =
top_of_pipe_flags | VK_PIPELINE_STAGE_2_DRAW_INDIRECT_BIT_KHR | VK_PIPELINE_STAGE_2_VERTEX_INPUT_BIT_KHR;
VkPipelineStageFlags2 post_index_fetch_flags =
top_of_pipe_flags | VK_PIPELINE_STAGE_2_DRAW_INDIRECT_BIT | VK_PIPELINE_STAGE_2_VERTEX_INPUT_BIT;
/* Flags that only require signaling post PS. */
VkPipelineStageFlags2KHR post_ps_flags =
post_index_fetch_flags | VK_PIPELINE_STAGE_2_VERTEX_SHADER_BIT_KHR |
VK_PIPELINE_STAGE_2_TESSELLATION_CONTROL_SHADER_BIT_KHR |
VK_PIPELINE_STAGE_2_TESSELLATION_EVALUATION_SHADER_BIT_KHR | VK_PIPELINE_STAGE_2_GEOMETRY_SHADER_BIT_KHR |
VkPipelineStageFlags2 post_ps_flags =
post_index_fetch_flags | VK_PIPELINE_STAGE_2_VERTEX_SHADER_BIT |
VK_PIPELINE_STAGE_2_TESSELLATION_CONTROL_SHADER_BIT |
VK_PIPELINE_STAGE_2_TESSELLATION_EVALUATION_SHADER_BIT | VK_PIPELINE_STAGE_2_GEOMETRY_SHADER_BIT |
VK_PIPELINE_STAGE_2_MESH_SHADER_BIT_NV |
VK_PIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT |
VK_PIPELINE_STAGE_2_PRE_RASTERIZATION_SHADERS_BIT_KHR |
VK_PIPELINE_STAGE_2_PRE_RASTERIZATION_SHADERS_BIT |
VK_PIPELINE_STAGE_2_FRAGMENT_SHADING_RATE_ATTACHMENT_BIT_KHR |
VK_PIPELINE_STAGE_2_EARLY_FRAGMENT_TESTS_BIT_KHR | VK_PIPELINE_STAGE_2_FRAGMENT_SHADER_BIT_KHR;
VK_PIPELINE_STAGE_2_EARLY_FRAGMENT_TESTS_BIT | VK_PIPELINE_STAGE_2_FRAGMENT_SHADER_BIT;
/* Flags that only require signaling post CS. */
VkPipelineStageFlags2KHR post_cs_flags = VK_PIPELINE_STAGE_2_COMPUTE_SHADER_BIT_KHR;
VkPipelineStageFlags2 post_cs_flags = VK_PIPELINE_STAGE_2_COMPUTE_SHADER_BIT;
/* Make sure CP DMA is idle because the driver might have performed a
* DMA operation for copying or filling buffers/images.
*/
if (stageMask & (VK_PIPELINE_STAGE_2_TRANSFER_BIT_KHR | VK_PIPELINE_STAGE_2_BOTTOM_OF_PIPE_BIT_KHR))
if (stageMask & (VK_PIPELINE_STAGE_2_TRANSFER_BIT | VK_PIPELINE_STAGE_2_BOTTOM_OF_PIPE_BIT))
si_cp_dma_wait_for_idle(cmd_buffer);
if (!(stageMask & ~top_of_pipe_flags)) {
@@ -8561,12 +8559,12 @@ write_event(struct radv_cmd_buffer *cmd_buffer, struct radv_event *event,
}
VKAPI_ATTR void VKAPI_CALL
radv_CmdSetEvent2KHR(VkCommandBuffer commandBuffer, VkEvent _event,
const VkDependencyInfoKHR* pDependencyInfo)
radv_CmdSetEvent2(VkCommandBuffer commandBuffer, VkEvent _event,
const VkDependencyInfo* pDependencyInfo)
{
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
RADV_FROM_HANDLE(radv_event, event, _event);
VkPipelineStageFlags2KHR src_stage_mask = 0;
VkPipelineStageFlags2 src_stage_mask = 0;
for (uint32_t i = 0; i < pDependencyInfo->memoryBarrierCount; i++)
src_stage_mask |= pDependencyInfo->pMemoryBarriers[i].srcStageMask;
@@ -8579,8 +8577,8 @@ radv_CmdSetEvent2KHR(VkCommandBuffer commandBuffer, VkEvent _event,
}
VKAPI_ATTR void VKAPI_CALL
radv_CmdResetEvent2KHR(VkCommandBuffer commandBuffer, VkEvent _event,
VkPipelineStageFlags2KHR stageMask)
radv_CmdResetEvent2(VkCommandBuffer commandBuffer, VkEvent _event,
VkPipelineStageFlags2 stageMask)
{
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
RADV_FROM_HANDLE(radv_event, event, _event);
@@ -8589,8 +8587,8 @@ radv_CmdResetEvent2KHR(VkCommandBuffer commandBuffer, VkEvent _event,
}
VKAPI_ATTR void VKAPI_CALL
radv_CmdWaitEvents2KHR(VkCommandBuffer commandBuffer, uint32_t eventCount, const VkEvent *pEvents,
const VkDependencyInfoKHR* pDependencyInfos)
radv_CmdWaitEvents2(VkCommandBuffer commandBuffer, uint32_t eventCount, const VkEvent *pEvents,
const VkDependencyInfo* pDependencyInfos)
{
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
struct radeon_cmdbuf *cs = cmd_buffer->cs;
@@ -9094,7 +9092,7 @@ radv_CmdDrawIndirectByteCountEXT(VkCommandBuffer commandBuffer, uint32_t instanc
/* VK_AMD_buffer_marker */
VKAPI_ATTR void VKAPI_CALL
radv_CmdWriteBufferMarker2AMD(VkCommandBuffer commandBuffer, VkPipelineStageFlags2KHR stage,
radv_CmdWriteBufferMarker2AMD(VkCommandBuffer commandBuffer, VkPipelineStageFlags2 stage,
VkBuffer dstBuffer, VkDeviceSize dstOffset, uint32_t marker)
{
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
@@ -9106,7 +9104,7 @@ radv_CmdWriteBufferMarker2AMD(VkCommandBuffer commandBuffer, VkPipelineStageFlag
ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 12);
if (!(stage & ~VK_PIPELINE_STAGE_2_TOP_OF_PIPE_BIT_KHR)) {
if (!(stage & ~VK_PIPELINE_STAGE_2_TOP_OF_PIPE_BIT)) {
radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_IMM) | COPY_DATA_DST_SEL(COPY_DATA_DST_MEM) |
COPY_DATA_WR_CONFIRM);
src/amd/vulkan/radv_descriptor_set.c
+10 -10
View File
@@ -267,7 +267,7 @@ radv_CreateDescriptorSetLayout(VkDevice _device, const VkDescriptorSetLayoutCrea
alignment = mutable_align;
break;
}
case VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT:
case VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK:
alignment = 16;
set_layout->binding[b].size = descriptor_count;
descriptor_count = 1;
@@ -427,7 +427,7 @@ radv_GetDescriptorSetLayoutSupport(VkDevice device,
descriptor_alignment = 16;
}
break;
case VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT:
case VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK:
descriptor_alignment = 16;
descriptor_size = descriptor_count;
descriptor_count = 1;
@@ -453,7 +453,7 @@ radv_GetDescriptorSetLayoutSupport(VkDevice device,
size = align_u64(size, descriptor_alignment);
uint64_t max_count = INT32_MAX;
if (binding->descriptorType == VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT)
if (binding->descriptorType == VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK)
max_count = INT32_MAX - size;
else if (descriptor_size)
max_count = (INT32_MAX - size) / descriptor_size;
@@ -568,7 +568,7 @@ radv_descriptor_set_create(struct radv_device *device, struct radv_descriptor_po
unsigned stride = 1;
if (layout->binding[layout->binding_count - 1].type == VK_DESCRIPTOR_TYPE_SAMPLER ||
layout->binding[layout->binding_count - 1].type ==
VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT)
VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK)
stride = 0;
buffer_count =
layout->binding[layout->binding_count - 1].buffer_offset + *variable_count * stride;
@@ -608,7 +608,7 @@ radv_descriptor_set_create(struct radv_device *device, struct radv_descriptor_po
if (variable_count) {
uint32_t stride = layout->binding[layout->binding_count - 1].size;
if (layout->binding[layout->binding_count - 1].type ==
VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT)
VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK)
stride = 1;
layout_size = layout->binding[layout->binding_count - 1].offset + *variable_count * stride;
@@ -800,7 +800,7 @@ radv_CreateDescriptorPool(VkDevice _device, const VkDescriptorPoolCreateInfo *pC
case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
bo_size += 96 * pCreateInfo->pPoolSizes[i].descriptorCount;
break;
case VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT:
case VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK:
bo_size += pCreateInfo->pPoolSizes[i].descriptorCount;
break;
default:
@@ -1172,7 +1172,7 @@ radv_update_descriptor_sets_impl(struct radv_device *device, struct radv_cmd_buf
ptr += binding_layout->offset / 4;
if (writeset->descriptorType == VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT) {
if (writeset->descriptorType == VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK) {
write_block_descriptor(device, cmd_buffer, (uint8_t *)ptr + writeset->dstArrayElement,
writeset);
continue;
@@ -1261,7 +1261,7 @@ radv_update_descriptor_sets_impl(struct radv_device *device, struct radv_cmd_buf
src_ptr += src_binding_layout->offset / 4;
dst_ptr += dst_binding_layout->offset / 4;
if (src_binding_layout->type == VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT) {
if (src_binding_layout->type == VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK) {
src_ptr += copyset->srcArrayElement / 4;
dst_ptr += copyset->dstArrayElement / 4;
@@ -1411,7 +1411,7 @@ radv_CreateDescriptorUpdateTemplate(VkDevice _device,
break;
}
dst_offset = binding_layout->offset / 4;
if (entry->descriptorType == VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT)
if (entry->descriptorType == VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK)
dst_offset += entry->dstArrayElement / 4;
else
dst_offset += binding_layout->size * entry->dstArrayElement / 4;
@@ -1468,7 +1468,7 @@ radv_update_descriptor_set_with_template_impl(struct radv_device *device,
const uint8_t *pSrc = ((const uint8_t *)pData) + templ->entry[i].src_offset;
uint32_t j;
if (templ->entry[i].descriptor_type == VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT) {
if (templ->entry[i].descriptor_type == VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK) {
memcpy((uint8_t *)pDst, pSrc, templ->entry[i].descriptor_count);
continue;
}
src/amd/vulkan/radv_device.c
+30 -30
View File
@@ -1665,9 +1665,9 @@ radv_GetPhysicalDeviceFeatures2(VkPhysicalDevice physicalDevice,
features->rayTraversalPrimitiveCulling = false;
break;
}
case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_4_FEATURES_KHR: {
VkPhysicalDeviceMaintenance4FeaturesKHR *features =
(VkPhysicalDeviceMaintenance4FeaturesKHR *)ext;
case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_4_FEATURES: {
VkPhysicalDeviceMaintenance4Features *features =
(VkPhysicalDeviceMaintenance4Features *)ext;
features->maintenance4 = true;
break;
}
@@ -1683,15 +1683,15 @@ radv_GetPhysicalDeviceFeatures2(VkPhysicalDevice physicalDevice,
features->minLod = true;
break;
}
case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SYNCHRONIZATION_2_FEATURES_KHR: {
VkPhysicalDeviceSynchronization2FeaturesKHR *features =
(VkPhysicalDeviceSynchronization2FeaturesKHR *)ext;
case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SYNCHRONIZATION_2_FEATURES: {
VkPhysicalDeviceSynchronization2Features *features =
(VkPhysicalDeviceSynchronization2Features *)ext;
features->synchronization2 = true;
break;
}
case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DYNAMIC_RENDERING_FEATURES_KHR: {
VkPhysicalDeviceDynamicRenderingFeaturesKHR *features =
(VkPhysicalDeviceDynamicRenderingFeaturesKHR *)ext;
case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DYNAMIC_RENDERING_FEATURES: {
VkPhysicalDeviceDynamicRenderingFeatures *features =
(VkPhysicalDeviceDynamicRenderingFeatures *)ext;
features->dynamicRendering = true;
break;
}
@@ -1974,11 +1974,11 @@ radv_get_physical_device_properties_1_2(struct radv_physical_device *pdevice,
* controlled by the same config register.
*/
if (pdevice->rad_info.has_packed_math_16bit) {
p->denormBehaviorIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR;
p->roundingModeIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR;
p->denormBehaviorIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY;
p->roundingModeIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY;
} else {
p->denormBehaviorIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_ALL_KHR;
p->roundingModeIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_ALL_KHR;
p->denormBehaviorIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_ALL;
p->roundingModeIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_ALL;
}
/* With LLVM, do not allow both preserving and flushing denorms because
@@ -2040,13 +2040,13 @@ radv_get_physical_device_properties_1_2(struct radv_physical_device *pdevice,
p->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
/* We support all of the depth resolve modes */
p->supportedDepthResolveModes = VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
VK_RESOLVE_MODE_AVERAGE_BIT_KHR | VK_RESOLVE_MODE_MIN_BIT_KHR |
VK_RESOLVE_MODE_MAX_BIT_KHR;
p->supportedDepthResolveModes = VK_RESOLVE_MODE_SAMPLE_ZERO_BIT |
VK_RESOLVE_MODE_AVERAGE_BIT | VK_RESOLVE_MODE_MIN_BIT |
VK_RESOLVE_MODE_MAX_BIT;
/* Average doesn't make sense for stencil so we don't support that */
p->supportedStencilResolveModes = VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
VK_RESOLVE_MODE_MIN_BIT_KHR | VK_RESOLVE_MODE_MAX_BIT_KHR;
p->supportedStencilResolveModes = VK_RESOLVE_MODE_SAMPLE_ZERO_BIT |
VK_RESOLVE_MODE_MIN_BIT | VK_RESOLVE_MODE_MAX_BIT;
p->independentResolveNone = true;
p->independentResolve = true;
@@ -2367,9 +2367,9 @@ radv_GetPhysicalDeviceProperties2(VkPhysicalDevice physicalDevice,
props->maxRayHitAttributeSize = RADV_MAX_HIT_ATTRIB_SIZE;
break;
}
case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_4_PROPERTIES_KHR: {
VkPhysicalDeviceMaintenance4PropertiesKHR *properties =
(VkPhysicalDeviceMaintenance4PropertiesKHR *)ext;
case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_4_PROPERTIES: {
VkPhysicalDeviceMaintenance4Properties *properties =
(VkPhysicalDeviceMaintenance4Properties *)ext;
properties->maxBufferSize = RADV_MAX_MEMORY_ALLOCATION_SIZE;
break;
}
@@ -4495,7 +4495,7 @@ struct radv_deferred_queue_submission {
uint32_t image_bind_count;
bool flush_caches;
VkPipelineStageFlags2KHR wait_dst_stage_mask;
VkPipelineStageFlags2 wait_dst_stage_mask;
struct radv_semaphore_part **wait_semaphores;
uint32_t wait_semaphore_count;
struct radv_semaphore_part **signal_semaphores;
@@ -5089,9 +5089,9 @@ radv_GetBufferMemoryRequirements2(VkDevice _device, const VkBufferMemoryRequirem
}
VKAPI_ATTR void VKAPI_CALL
radv_GetDeviceBufferMemoryRequirementsKHR(VkDevice _device,
const VkDeviceBufferMemoryRequirementsKHR *pInfo,
VkMemoryRequirements2 *pMemoryRequirements)
radv_GetDeviceBufferMemoryRequirements(VkDevice _device,
const VkDeviceBufferMemoryRequirements *pInfo,
VkMemoryRequirements2 *pMemoryRequirements)
{
RADV_FROM_HANDLE(radv_device, device, _device);
@@ -5129,9 +5129,9 @@ radv_GetImageMemoryRequirements2(VkDevice _device, const VkImageMemoryRequiremen
}
VKAPI_ATTR void VKAPI_CALL
radv_GetDeviceImageMemoryRequirementsKHR(VkDevice device,
const VkDeviceImageMemoryRequirementsKHR *pInfo,
VkMemoryRequirements2 *pMemoryRequirements)
radv_GetDeviceImageMemoryRequirements(VkDevice device,
const VkDeviceImageMemoryRequirements *pInfo,
VkMemoryRequirements2 *pMemoryRequirements)
{
UNUSED VkResult result;
VkImage image;
@@ -5254,7 +5254,7 @@ radv_CreateEvent(VkDevice _device, const VkEventCreateInfo *pCreateInfo,
vk_object_base_init(&device->vk, &event->base, VK_OBJECT_TYPE_EVENT);
if (pCreateInfo->flags & VK_EVENT_CREATE_DEVICE_ONLY_BIT_KHR) {
if (pCreateInfo->flags & VK_EVENT_CREATE_DEVICE_ONLY_BIT) {
bo_domain = RADEON_DOMAIN_VRAM;
bo_flags = RADEON_FLAG_NO_CPU_ACCESS;
} else {
@@ -5271,7 +5271,7 @@ radv_CreateEvent(VkDevice _device, const VkEventCreateInfo *pCreateInfo,
return vk_error(device, result);
}
if (!(pCreateInfo->flags & VK_EVENT_CREATE_DEVICE_ONLY_BIT_KHR)) {
if (!(pCreateInfo->flags & VK_EVENT_CREATE_DEVICE_ONLY_BIT)) {
event->map = (uint64_t *)device->ws->buffer_map(event->bo);
if (!event->map) {
radv_destroy_event(device, pAllocator, event);
src/amd/vulkan/radv_formats.c
+73 -73
View File
@@ -658,9 +658,9 @@ radv_is_filter_minmax_format_supported(VkFormat format)
/* From the Vulkan spec 1.1.71:
*
* "The following formats must support the
* VK_FORMAT_FEATURE_2_SAMPLED_IMAGE_FILTER_MINMAX_BIT_KHR feature with
* VK_FORMAT_FEATURE_2_SAMPLED_IMAGE_FILTER_MINMAX_BIT feature with
* VK_IMAGE_TILING_OPTIMAL, if they support
* VK_FORMAT_FEATURE_2_SAMPLED_IMAGE_BIT_KHR."
* VK_FORMAT_FEATURE_2_SAMPLED_IMAGE_BIT."
*/
/* TODO: enable more formats. */
switch (format) {
@@ -693,9 +693,9 @@ radv_device_supports_etc(struct radv_physical_device *physical_device)
static void
radv_physical_device_get_format_properties(struct radv_physical_device *physical_device,
VkFormat format, VkFormatProperties3KHR *out_properties)
VkFormat format, VkFormatProperties3 *out_properties)
{
VkFormatFeatureFlags2KHR linear = 0, tiled = 0, buffer = 0;
VkFormatFeatureFlags2 linear = 0, tiled = 0, buffer = 0;
const struct util_format_description *desc = vk_format_description(format);
bool blendable;
bool scaled = false;
@@ -717,15 +717,15 @@ radv_physical_device_get_format_properties(struct radv_physical_device *physical
}
if (vk_format_get_plane_count(format) > 1 || desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
uint64_t tiling = VK_FORMAT_FEATURE_2_TRANSFER_SRC_BIT_KHR |
VK_FORMAT_FEATURE_2_TRANSFER_DST_BIT_KHR |
VK_FORMAT_FEATURE_2_SAMPLED_IMAGE_BIT_KHR |
VK_FORMAT_FEATURE_2_COSITED_CHROMA_SAMPLES_BIT_KHR |
VK_FORMAT_FEATURE_2_MIDPOINT_CHROMA_SAMPLES_BIT_KHR;
uint64_t tiling = VK_FORMAT_FEATURE_2_TRANSFER_SRC_BIT |
VK_FORMAT_FEATURE_2_TRANSFER_DST_BIT |
VK_FORMAT_FEATURE_2_SAMPLED_IMAGE_BIT |
VK_FORMAT_FEATURE_2_COSITED_CHROMA_SAMPLES_BIT |
VK_FORMAT_FEATURE_2_MIDPOINT_CHROMA_SAMPLES_BIT;
/* The subsampled formats have no support for linear filters. */
if (desc->layout != UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
tiling |= VK_FORMAT_FEATURE_2_SAMPLED_IMAGE_YCBCR_CONVERSION_LINEAR_FILTER_BIT_KHR;
tiling |= VK_FORMAT_FEATURE_2_SAMPLED_IMAGE_YCBCR_CONVERSION_LINEAR_FILTER_BIT;
}
/* Fails for unknown reasons with linear tiling & subsampled formats. */
@@ -737,41 +737,41 @@ radv_physical_device_get_format_properties(struct radv_physical_device *physical
}
if (radv_is_storage_image_format_supported(physical_device, format)) {
tiled |= VK_FORMAT_FEATURE_2_STORAGE_IMAGE_BIT_KHR |
VK_FORMAT_FEATURE_2_STORAGE_READ_WITHOUT_FORMAT_BIT_KHR |
VK_FORMAT_FEATURE_2_STORAGE_WRITE_WITHOUT_FORMAT_BIT_KHR;
linear |= VK_FORMAT_FEATURE_2_STORAGE_IMAGE_BIT_KHR |
VK_FORMAT_FEATURE_2_STORAGE_READ_WITHOUT_FORMAT_BIT_KHR |
VK_FORMAT_FEATURE_2_STORAGE_WRITE_WITHOUT_FORMAT_BIT_KHR;
tiled |= VK_FORMAT_FEATURE_2_STORAGE_IMAGE_BIT |
VK_FORMAT_FEATURE_2_STORAGE_READ_WITHOUT_FORMAT_BIT |
VK_FORMAT_FEATURE_2_STORAGE_WRITE_WITHOUT_FORMAT_BIT;
linear |= VK_FORMAT_FEATURE_2_STORAGE_IMAGE_BIT |
VK_FORMAT_FEATURE_2_STORAGE_READ_WITHOUT_FORMAT_BIT |
VK_FORMAT_FEATURE_2_STORAGE_WRITE_WITHOUT_FORMAT_BIT;
}
if (radv_is_buffer_format_supported(format, &scaled)) {
if (format != VK_FORMAT_R64_UINT && format != VK_FORMAT_R64_SINT) {
buffer |= VK_FORMAT_FEATURE_2_VERTEX_BUFFER_BIT_KHR;
buffer |= VK_FORMAT_FEATURE_2_VERTEX_BUFFER_BIT;
if (!scaled)
buffer |= VK_FORMAT_FEATURE_2_UNIFORM_TEXEL_BUFFER_BIT_KHR;
buffer |= VK_FORMAT_FEATURE_2_UNIFORM_TEXEL_BUFFER_BIT;
}
buffer |= VK_FORMAT_FEATURE_2_STORAGE_TEXEL_BUFFER_BIT_KHR;
buffer |= VK_FORMAT_FEATURE_2_STORAGE_TEXEL_BUFFER_BIT;
}
if (vk_format_is_depth_or_stencil(format)) {
if (radv_is_zs_format_supported(format)) {
tiled |= VK_FORMAT_FEATURE_2_DEPTH_STENCIL_ATTACHMENT_BIT_KHR;
tiled |= VK_FORMAT_FEATURE_2_SAMPLED_IMAGE_BIT_KHR;
tiled |= VK_FORMAT_FEATURE_2_BLIT_SRC_BIT_KHR | VK_FORMAT_FEATURE_2_BLIT_DST_BIT_KHR;
tiled |= VK_FORMAT_FEATURE_2_TRANSFER_SRC_BIT_KHR | VK_FORMAT_FEATURE_2_TRANSFER_DST_BIT_KHR;
tiled |= VK_FORMAT_FEATURE_2_DEPTH_STENCIL_ATTACHMENT_BIT;
tiled |= VK_FORMAT_FEATURE_2_SAMPLED_IMAGE_BIT;
tiled |= VK_FORMAT_FEATURE_2_BLIT_SRC_BIT | VK_FORMAT_FEATURE_2_BLIT_DST_BIT;
tiled |= VK_FORMAT_FEATURE_2_TRANSFER_SRC_BIT | VK_FORMAT_FEATURE_2_TRANSFER_DST_BIT;
if (radv_is_filter_minmax_format_supported(format))
tiled |= VK_FORMAT_FEATURE_2_SAMPLED_IMAGE_FILTER_MINMAX_BIT_KHR;
tiled |= VK_FORMAT_FEATURE_2_SAMPLED_IMAGE_FILTER_MINMAX_BIT;
if (vk_format_has_depth(format)) {
tiled |= VK_FORMAT_FEATURE_2_SAMPLED_IMAGE_FILTER_LINEAR_BIT_KHR |
VK_FORMAT_FEATURE_2_SAMPLED_IMAGE_DEPTH_COMPARISON_BIT_KHR;
tiled |= VK_FORMAT_FEATURE_2_SAMPLED_IMAGE_FILTER_LINEAR_BIT |
VK_FORMAT_FEATURE_2_SAMPLED_IMAGE_DEPTH_COMPARISON_BIT;
}
/* Don't support blitting surfaces with depth/stencil. */
if (vk_format_has_depth(format) && vk_format_has_stencil(format))
tiled &= ~VK_FORMAT_FEATURE_2_BLIT_DST_BIT_KHR;
tiled &= ~VK_FORMAT_FEATURE_2_BLIT_DST_BIT;
/* Don't support linear depth surfaces */
linear = 0;
@@ -779,33 +779,33 @@ radv_physical_device_get_format_properties(struct radv_physical_device *physical
} else {
bool linear_sampling;
if (radv_is_sampler_format_supported(format, &linear_sampling)) {
linear |= VK_FORMAT_FEATURE_2_SAMPLED_IMAGE_BIT_KHR | VK_FORMAT_FEATURE_2_BLIT_SRC_BIT_KHR;
tiled |= VK_FORMAT_FEATURE_2_SAMPLED_IMAGE_BIT_KHR | VK_FORMAT_FEATURE_2_BLIT_SRC_BIT_KHR;
linear |= VK_FORMAT_FEATURE_2_SAMPLED_IMAGE_BIT | VK_FORMAT_FEATURE_2_BLIT_SRC_BIT;
tiled |= VK_FORMAT_FEATURE_2_SAMPLED_IMAGE_BIT | VK_FORMAT_FEATURE_2_BLIT_SRC_BIT;
if (radv_is_filter_minmax_format_supported(format))
tiled |= VK_FORMAT_FEATURE_2_SAMPLED_IMAGE_FILTER_MINMAX_BIT_KHR;
tiled |= VK_FORMAT_FEATURE_2_SAMPLED_IMAGE_FILTER_MINMAX_BIT;
if (linear_sampling) {
linear |= VK_FORMAT_FEATURE_2_SAMPLED_IMAGE_FILTER_LINEAR_BIT_KHR;
tiled |= VK_FORMAT_FEATURE_2_SAMPLED_IMAGE_FILTER_LINEAR_BIT_KHR;
linear |= VK_FORMAT_FEATURE_2_SAMPLED_IMAGE_FILTER_LINEAR_BIT;
tiled |= VK_FORMAT_FEATURE_2_SAMPLED_IMAGE_FILTER_LINEAR_BIT;
}
/* Don't support blitting for R32G32B32 formats. */
if (format == VK_FORMAT_R32G32B32_SFLOAT || format == VK_FORMAT_R32G32B32_UINT ||
format == VK_FORMAT_R32G32B32_SINT) {
linear &= ~VK_FORMAT_FEATURE_2_BLIT_SRC_BIT_KHR;
linear &= ~VK_FORMAT_FEATURE_2_BLIT_SRC_BIT;
}
}
if (radv_is_colorbuffer_format_supported(physical_device, format, &blendable)) {
linear |= VK_FORMAT_FEATURE_2_COLOR_ATTACHMENT_BIT_KHR | VK_FORMAT_FEATURE_2_BLIT_DST_BIT_KHR;
tiled |= VK_FORMAT_FEATURE_2_COLOR_ATTACHMENT_BIT_KHR | VK_FORMAT_FEATURE_2_BLIT_DST_BIT_KHR;
linear |= VK_FORMAT_FEATURE_2_COLOR_ATTACHMENT_BIT | VK_FORMAT_FEATURE_2_BLIT_DST_BIT;
tiled |= VK_FORMAT_FEATURE_2_COLOR_ATTACHMENT_BIT | VK_FORMAT_FEATURE_2_BLIT_DST_BIT;
if (blendable) {
linear |= VK_FORMAT_FEATURE_2_COLOR_ATTACHMENT_BLEND_BIT_KHR;
tiled |= VK_FORMAT_FEATURE_2_COLOR_ATTACHMENT_BLEND_BIT_KHR;
linear |= VK_FORMAT_FEATURE_2_COLOR_ATTACHMENT_BLEND_BIT;
tiled |= VK_FORMAT_FEATURE_2_COLOR_ATTACHMENT_BLEND_BIT;
}
}
if (tiled && !scaled) {
tiled |= VK_FORMAT_FEATURE_2_TRANSFER_SRC_BIT_KHR | VK_FORMAT_FEATURE_2_TRANSFER_DST_BIT_KHR;
tiled |= VK_FORMAT_FEATURE_2_TRANSFER_SRC_BIT | VK_FORMAT_FEATURE_2_TRANSFER_DST_BIT;
}
/* Tiled formatting does not support NPOT pixel sizes */
@@ -814,13 +814,13 @@ radv_physical_device_get_format_properties(struct radv_physical_device *physical
}
if (linear && !scaled) {
linear |= VK_FORMAT_FEATURE_2_TRANSFER_SRC_BIT_KHR | VK_FORMAT_FEATURE_2_TRANSFER_DST_BIT_KHR;
linear |= VK_FORMAT_FEATURE_2_TRANSFER_SRC_BIT | VK_FORMAT_FEATURE_2_TRANSFER_DST_BIT;
}
if (radv_is_atomic_format_supported(format)) {
buffer |= VK_FORMAT_FEATURE_2_STORAGE_TEXEL_BUFFER_ATOMIC_BIT_KHR;
linear |= VK_FORMAT_FEATURE_2_STORAGE_IMAGE_ATOMIC_BIT_KHR;
tiled |= VK_FORMAT_FEATURE_2_STORAGE_IMAGE_ATOMIC_BIT_KHR;
buffer |= VK_FORMAT_FEATURE_2_STORAGE_TEXEL_BUFFER_ATOMIC_BIT;
linear |= VK_FORMAT_FEATURE_2_STORAGE_IMAGE_ATOMIC_BIT;
tiled |= VK_FORMAT_FEATURE_2_STORAGE_IMAGE_ATOMIC_BIT;
}
switch (format) {
@@ -831,7 +831,7 @@ radv_physical_device_get_format_properties(struct radv_physical_device *physical
case VK_FORMAT_A2R10G10B10_SINT_PACK32:
case VK_FORMAT_A2B10G10R10_SINT_PACK32:
buffer &=
~(VK_FORMAT_FEATURE_2_UNIFORM_TEXEL_BUFFER_BIT_KHR | VK_FORMAT_FEATURE_2_STORAGE_TEXEL_BUFFER_BIT_KHR);
~(VK_FORMAT_FEATURE_2_UNIFORM_TEXEL_BUFFER_BIT | VK_FORMAT_FEATURE_2_STORAGE_TEXEL_BUFFER_BIT);
linear = 0;
tiled = 0;
break;
@@ -860,7 +860,7 @@ radv_physical_device_get_format_properties(struct radv_physical_device *physical
/* From the Vulkan spec 1.2.163:
*
* "VK_FORMAT_FEATURE_2_FRAGMENT_SHADING_RATE_ATTACHMENT_BIT_KHR must be supported for the
* "VK_FORMAT_FEATURE_2_FRAGMENT_SHADING_RATE_ATTACHMENT_BIT must be supported for the
* following formats if the attachmentFragmentShadingRate feature is supported:"
*
* - VK_FORMAT_R8_UINT
@@ -1189,11 +1189,11 @@ static const struct ac_modifier_options radv_modifier_options = {
.dcc_retile = true,
};
static VkFormatFeatureFlags2KHR
static VkFormatFeatureFlags2
radv_get_modifier_flags(struct radv_physical_device *dev, VkFormat format, uint64_t modifier,
const VkFormatProperties3KHR *props)
const VkFormatProperties3 *props)
{
VkFormatFeatureFlags2KHR features;
VkFormatFeatureFlags2 features;
if (vk_format_is_compressed(format) || vk_format_is_depth_or_stencil(format))
return 0;
@@ -1208,7 +1208,7 @@ radv_get_modifier_flags(struct radv_physical_device *dev, VkFormat format, uint6
* do not support DCC image stores.
*/
if (!ac_modifier_supports_dcc_image_stores(modifier) || radv_is_atomic_format_supported(format))
features &= ~VK_FORMAT_FEATURE_2_STORAGE_IMAGE_BIT_KHR;
features &= ~VK_FORMAT_FEATURE_2_STORAGE_IMAGE_BIT;
if (dev->instance->debug_flags & (RADV_DEBUG_NO_DCC | RADV_DEBUG_NO_DISPLAY_DCC))
return 0;
@@ -1218,14 +1218,14 @@ radv_get_modifier_flags(struct radv_physical_device *dev, VkFormat format, uint6
}
static VkFormatFeatureFlags
features2_to_features(VkFormatFeatureFlags2KHR features2)
features2_to_features(VkFormatFeatureFlags2 features2)
{
return features2 & VK_ALL_FORMAT_FEATURE_FLAG_BITS;
}
static void
radv_list_drm_format_modifiers(struct radv_physical_device *dev, VkFormat format,
const VkFormatProperties3KHR *format_props,
const VkFormatProperties3 *format_props,
VkDrmFormatModifierPropertiesListEXT *mod_list)
{
unsigned mod_count;
@@ -1255,7 +1255,7 @@ radv_list_drm_format_modifiers(struct radv_physical_device *dev, VkFormat format
vk_format_to_pipe_format(format), &mod_count, mods);
for (unsigned i = 0; i < mod_count; ++i) {
VkFormatFeatureFlags2KHR features =
VkFormatFeatureFlags2 features =
radv_get_modifier_flags(dev, format, mods[i], format_props);
unsigned planes = vk_format_get_plane_count(format);
if (planes == 1) {
@@ -1282,7 +1282,7 @@ radv_list_drm_format_modifiers(struct radv_physical_device *dev, VkFormat format
static void
radv_list_drm_format_modifiers_2(struct radv_physical_device *dev, VkFormat format,
const VkFormatProperties3KHR *format_props,
const VkFormatProperties3 *format_props,
VkDrmFormatModifierPropertiesList2EXT *mod_list)
{
unsigned mod_count;
@@ -1312,7 +1312,7 @@ radv_list_drm_format_modifiers_2(struct radv_physical_device *dev, VkFormat form
vk_format_to_pipe_format(format), &mod_count, mods);
for (unsigned i = 0; i < mod_count; ++i) {
VkFormatFeatureFlags2KHR features =
VkFormatFeatureFlags2 features =
radv_get_modifier_flags(dev, format, mods[i], format_props);
unsigned planes = vk_format_get_plane_count(format);
if (planes == 1) {
@@ -1423,7 +1423,7 @@ radv_GetPhysicalDeviceFormatProperties2(VkPhysicalDevice physicalDevice, VkForma
VkFormatProperties2 *pFormatProperties)
{
RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
VkFormatProperties3KHR format_props;
VkFormatProperties3 format_props;
radv_physical_device_get_format_properties(physical_device, format, &format_props);
@@ -1434,8 +1434,8 @@ radv_GetPhysicalDeviceFormatProperties2(VkPhysicalDevice physicalDevice, VkForma
pFormatProperties->formatProperties.bufferFeatures =
features2_to_features(format_props.bufferFeatures);
VkFormatProperties3KHR *format_props_extended =
vk_find_struct(pFormatProperties, FORMAT_PROPERTIES_3_KHR);
VkFormatProperties3 *format_props_extended =
vk_find_struct(pFormatProperties, FORMAT_PROPERTIES_3);
if (format_props_extended) {
format_props_extended->linearTilingFeatures = format_props.linearTilingFeatures;
format_props_extended->optimalTilingFeatures = format_props.optimalTilingFeatures;
@@ -1456,8 +1456,8 @@ radv_get_image_format_properties(struct radv_physical_device *physical_device,
VkImageFormatProperties *pImageFormatProperties)
{
VkFormatProperties3KHR format_props;
VkFormatFeatureFlags2KHR format_feature_flags;
VkFormatProperties3 format_props;
VkFormatFeatureFlags2 format_feature_flags;
VkExtent3D maxExtent;
uint32_t maxMipLevels;
uint32_t maxArraySize;
@@ -1526,8 +1526,8 @@ radv_get_image_format_properties(struct radv_physical_device *physical_device,
}
if (tiling == VK_IMAGE_TILING_OPTIMAL && info->type == VK_IMAGE_TYPE_2D &&
(format_feature_flags & (VK_FORMAT_FEATURE_2_COLOR_ATTACHMENT_BIT_KHR |
VK_FORMAT_FEATURE_2_DEPTH_STENCIL_ATTACHMENT_BIT_KHR)) &&
(format_feature_flags & (VK_FORMAT_FEATURE_2_COLOR_ATTACHMENT_BIT |
VK_FORMAT_FEATURE_2_DEPTH_STENCIL_ATTACHMENT_BIT)) &&
!(info->flags & VK_IMAGE_CREATE_CUBE_COMPATIBLE_BIT) &&
!(info->usage & VK_IMAGE_USAGE_FRAGMENT_SHADING_RATE_ATTACHMENT_BIT_KHR)) {
sampleCounts |= VK_SAMPLE_COUNT_2_BIT | VK_SAMPLE_COUNT_4_BIT | VK_SAMPLE_COUNT_8_BIT;
@@ -1551,7 +1551,7 @@ radv_get_image_format_properties(struct radv_physical_device *physical_device,
vk_format_get_blocksizebits(format) == 128 && vk_format_is_compressed(format) &&
(info->flags & VK_IMAGE_CREATE_BLOCK_TEXEL_VIEW_COMPATIBLE_BIT) &&
((info->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT) ||
(info->usage & VK_FORMAT_FEATURE_2_COLOR_ATTACHMENT_BIT_KHR))) {
(info->usage & VK_FORMAT_FEATURE_2_COLOR_ATTACHMENT_BIT))) {
goto unsupported;
}
@@ -1566,44 +1566,44 @@ radv_get_image_format_properties(struct radv_physical_device *physical_device,
image_usage = 0;
if (image_usage & VK_IMAGE_USAGE_SAMPLED_BIT) {
if (!(format_feature_flags & VK_FORMAT_FEATURE_2_SAMPLED_IMAGE_BIT_KHR)) {
if (!(format_feature_flags & VK_FORMAT_FEATURE_2_SAMPLED_IMAGE_BIT)) {
goto unsupported;
}
}
if (image_usage & VK_IMAGE_USAGE_STORAGE_BIT) {
if (!(format_feature_flags & VK_FORMAT_FEATURE_2_STORAGE_IMAGE_BIT_KHR)) {
if (!(format_feature_flags & VK_FORMAT_FEATURE_2_STORAGE_IMAGE_BIT)) {
goto unsupported;
}
}
if (image_usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT) {
if (!(format_feature_flags & VK_FORMAT_FEATURE_2_COLOR_ATTACHMENT_BIT_KHR)) {
if (!(format_feature_flags & VK_FORMAT_FEATURE_2_COLOR_ATTACHMENT_BIT)) {
goto unsupported;
}
}
if (image_usage & VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT) {
if (!(format_feature_flags & VK_FORMAT_FEATURE_2_DEPTH_STENCIL_ATTACHMENT_BIT_KHR)) {
if (!(format_feature_flags & VK_FORMAT_FEATURE_2_DEPTH_STENCIL_ATTACHMENT_BIT)) {
goto unsupported;
}
}
if (image_usage & VK_IMAGE_USAGE_TRANSFER_SRC_BIT) {
if (!(format_feature_flags & VK_FORMAT_FEATURE_2_TRANSFER_SRC_BIT_KHR)) {
if (!(format_feature_flags & VK_FORMAT_FEATURE_2_TRANSFER_SRC_BIT)) {
goto unsupported;
}
}
if (image_usage & VK_IMAGE_USAGE_TRANSFER_DST_BIT) {
if (!(format_feature_flags & VK_FORMAT_FEATURE_2_TRANSFER_DST_BIT_KHR)) {
if (!(format_feature_flags & VK_FORMAT_FEATURE_2_TRANSFER_DST_BIT)) {
goto unsupported;
}
}
if (image_usage & VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT) {
if (!(format_feature_flags & (VK_FORMAT_FEATURE_2_COLOR_ATTACHMENT_BIT_KHR |
VK_FORMAT_FEATURE_2_DEPTH_STENCIL_ATTACHMENT_BIT_KHR))) {
if (!(format_feature_flags & (VK_FORMAT_FEATURE_2_COLOR_ATTACHMENT_BIT |
VK_FORMAT_FEATURE_2_DEPTH_STENCIL_ATTACHMENT_BIT))) {
goto unsupported;
}
}
@@ -1975,10 +1975,10 @@ radv_GetImageSparseMemoryRequirements2(VkDevice _device,
}
VKAPI_ATTR void VKAPI_CALL
radv_GetDeviceImageSparseMemoryRequirementsKHR(VkDevice device,
const VkDeviceImageMemoryRequirementsKHR* pInfo,
uint32_t *pSparseMemoryRequirementCount,
VkSparseImageMemoryRequirements2 *pSparseMemoryRequirements)
radv_GetDeviceImageSparseMemoryRequirements(VkDevice device,
const VkDeviceImageMemoryRequirements* pInfo,
uint32_t *pSparseMemoryRequirementCount,
VkSparseImageMemoryRequirements2 *pSparseMemoryRequirements)
{
UNUSED VkResult result;
VkImage image;
src/amd/vulkan/radv_image.c
+2 -2
View File
@@ -2196,7 +2196,7 @@ radv_layout_is_htile_compressed(const struct radv_device *device, const struct r
case VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL:
case VK_IMAGE_LAYOUT_DEPTH_ATTACHMENT_OPTIMAL:
case VK_IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL:
case VK_IMAGE_LAYOUT_ATTACHMENT_OPTIMAL_KHR:
case VK_IMAGE_LAYOUT_ATTACHMENT_OPTIMAL:
return radv_image_has_htile(image);
case VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL:
return radv_image_is_tc_compat_htile(image) ||
@@ -2249,7 +2249,7 @@ radv_layout_can_fast_clear(const struct radv_device *device, const struct radv_i
return false;
if (layout != VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL &&
layout != VK_IMAGE_LAYOUT_ATTACHMENT_OPTIMAL_KHR)
layout != VK_IMAGE_LAYOUT_ATTACHMENT_OPTIMAL)
return false;
/* Exclusive images with CMASK or DCC can always be fast-cleared on the gfx queue. Concurrent
src/amd/vulkan/radv_meta.h
+3 -3
View File
@@ -239,18 +239,18 @@ void radv_meta_resolve_compute_image(struct radv_cmd_buffer *cmd_buffer,
struct radv_image *src_image, VkFormat src_format,
VkImageLayout src_image_layout, struct radv_image *dest_image,
VkFormat dest_format, VkImageLayout dest_image_layout,
const VkImageResolve2KHR *region);
const VkImageResolve2 *region);
void radv_meta_resolve_fragment_image(struct radv_cmd_buffer *cmd_buffer,
struct radv_image *src_image, VkImageLayout src_image_layout,
struct radv_image *dest_image,
VkImageLayout dest_image_layout,
const VkImageResolve2KHR *region);
const VkImageResolve2 *region);
void radv_decompress_resolve_subpass_src(struct radv_cmd_buffer *cmd_buffer);
void radv_decompress_resolve_src(struct radv_cmd_buffer *cmd_buffer, struct radv_image *src_image,
VkImageLayout src_image_layout, const VkImageResolve2KHR *region);
VkImageLayout src_image_layout, const VkImageResolve2 *region);
uint32_t radv_clear_cmask(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
const VkImageSubresourceRange *range, uint32_t value);
src/amd/vulkan/radv_meta_blit.c
+2 -2
View File
@@ -464,7 +464,7 @@ flip_coords(unsigned *src0, unsigned *src1, unsigned *dst0, unsigned *dst1)
static void
blit_image(struct radv_cmd_buffer *cmd_buffer, struct radv_image *src_image,
VkImageLayout src_image_layout, struct radv_image *dst_image,
VkImageLayout dst_image_layout, const VkImageBlit2KHR *region, VkFilter filter)
VkImageLayout dst_image_layout, const VkImageBlit2 *region, VkFilter filter)
{
const VkImageSubresourceLayers *src_res = &region->srcSubresource;
const VkImageSubresourceLayers *dst_res = &region->dstSubresource;
@@ -624,7 +624,7 @@ blit_image(struct radv_cmd_buffer *cmd_buffer, struct radv_image *src_image,
}
VKAPI_ATTR void VKAPI_CALL
radv_CmdBlitImage2KHR(VkCommandBuffer commandBuffer, const VkBlitImageInfo2KHR *pBlitImageInfo)
radv_CmdBlitImage2(VkCommandBuffer commandBuffer, const VkBlitImageInfo2 *pBlitImageInfo)
{
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
RADV_FROM_HANDLE(radv_image, src_image, pBlitImageInfo->srcImage);
src/amd/vulkan/radv_meta_buffer.c
+4 -4
View File
@@ -312,12 +312,12 @@ radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer, const struct radv_image *im
if (use_compute) {
cmd_buffer->state.flush_bits |=
radv_dst_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_WRITE_BIT_KHR, image);
radv_dst_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_WRITE_BIT, image);
fill_buffer_shader(cmd_buffer, bo, offset, size, value);
flush_bits = RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_INV_VCACHE |
radv_src_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_WRITE_BIT_KHR, image);
radv_src_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_WRITE_BIT, image);
} else if (size) {
uint64_t va = radv_buffer_get_va(bo);
va += offset;
@@ -367,7 +367,7 @@ radv_CmdFillBuffer(VkCommandBuffer commandBuffer, VkBuffer dstBuffer, VkDeviceSi
static void
copy_buffer(struct radv_cmd_buffer *cmd_buffer, struct radv_buffer *src_buffer,
struct radv_buffer *dst_buffer, const VkBufferCopy2KHR *region)
struct radv_buffer *dst_buffer, const VkBufferCopy2 *region)
{
bool old_predicating;
@@ -386,7 +386,7 @@ copy_buffer(struct radv_cmd_buffer *cmd_buffer, struct radv_buffer *src_buffer,
}
VKAPI_ATTR void VKAPI_CALL
radv_CmdCopyBuffer2KHR(VkCommandBuffer commandBuffer, const VkCopyBufferInfo2KHR *pCopyBufferInfo)
radv_CmdCopyBuffer2(VkCommandBuffer commandBuffer, const VkCopyBufferInfo2 *pCopyBufferInfo)
{
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
RADV_FROM_HANDLE(radv_buffer, src_buffer, pCopyBufferInfo->srcBuffer);
src/amd/vulkan/radv_meta_clear.c
+7 -7
View File
@@ -872,7 +872,7 @@ clear_htile_mask(struct radv_cmd_buffer *cmd_buffer, const struct radv_image *im
radv_meta_restore(&saved_state, cmd_buffer);
return RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
radv_src_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_WRITE_BIT_KHR, image);
radv_src_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_WRITE_BIT, image);
}
static uint32_t
@@ -1021,10 +1021,10 @@ radv_fast_clear_depth(struct radv_cmd_buffer *cmd_buffer, const struct radv_imag
if (pre_flush) {
enum radv_cmd_flush_bits bits =
radv_src_access_flush(cmd_buffer, VK_ACCESS_2_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT_KHR,
radv_src_access_flush(cmd_buffer, VK_ACCESS_2_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT,
iview->image) |
radv_dst_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_WRITE_BIT_KHR |
VK_ACCESS_2_SHADER_READ_BIT_KHR, iview->image);
radv_dst_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_WRITE_BIT |
VK_ACCESS_2_SHADER_READ_BIT, iview->image);
cmd_buffer->state.flush_bits |= bits & ~*pre_flush;
*pre_flush |= cmd_buffer->state.flush_bits;
}
@@ -1623,7 +1623,7 @@ radv_clear_dcc_comp_to_single(struct radv_cmd_buffer *cmd_buffer,
radv_meta_restore(&saved_state, cmd_buffer);
return RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
radv_src_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_WRITE_BIT_KHR, image);
radv_src_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_WRITE_BIT, image);
}
uint32_t
@@ -1875,8 +1875,8 @@ radv_fast_clear_color(struct radv_cmd_buffer *cmd_buffer, const struct radv_imag
if (pre_flush) {
enum radv_cmd_flush_bits bits =
radv_src_access_flush(cmd_buffer, VK_ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT_KHR, iview->image) |
radv_dst_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_WRITE_BIT_KHR, iview->image);
radv_src_access_flush(cmd_buffer, VK_ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT, iview->image) |
radv_dst_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_WRITE_BIT, iview->image);
cmd_buffer->state.flush_bits |= bits & ~*pre_flush;
*pre_flush |= cmd_buffer->state.flush_bits;
}
src/amd/vulkan/radv_meta_copy.c
+8 -8
View File
@@ -125,7 +125,7 @@ radv_image_is_renderable(struct radv_device *device, struct radv_image *image)
static void
copy_buffer_to_image(struct radv_cmd_buffer *cmd_buffer, struct radv_buffer *buffer,
struct radv_image *image, VkImageLayout layout,
const VkBufferImageCopy2KHR *region)
const VkBufferImageCopy2 *region)
{
struct radv_meta_saved_state saved_state;
bool old_predicating;
@@ -244,8 +244,8 @@ copy_buffer_to_image(struct radv_cmd_buffer *cmd_buffer, struct radv_buffer *buf
}
VKAPI_ATTR void VKAPI_CALL
radv_CmdCopyBufferToImage2KHR(VkCommandBuffer commandBuffer,
const VkCopyBufferToImageInfo2KHR *pCopyBufferToImageInfo)
radv_CmdCopyBufferToImage2(VkCommandBuffer commandBuffer,
const VkCopyBufferToImageInfo2 *pCopyBufferToImageInfo)
{
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
RADV_FROM_HANDLE(radv_buffer, src_buffer, pCopyBufferToImageInfo->srcBuffer);
@@ -276,7 +276,7 @@ radv_CmdCopyBufferToImage2KHR(VkCommandBuffer commandBuffer,
static void
copy_image_to_buffer(struct radv_cmd_buffer *cmd_buffer, struct radv_buffer *buffer,
struct radv_image *image, VkImageLayout layout,
const VkBufferImageCopy2KHR *region)
const VkBufferImageCopy2 *region)
{
if (cmd_buffer->qf == RADV_QUEUE_TRANSFER) {
/* RADV_QUEUE_TRANSFER should only be used for the prime blit */
@@ -390,8 +390,8 @@ copy_image_to_buffer(struct radv_cmd_buffer *cmd_buffer, struct radv_buffer *buf
}
VKAPI_ATTR void VKAPI_CALL
radv_CmdCopyImageToBuffer2KHR(VkCommandBuffer commandBuffer,
const VkCopyImageToBufferInfo2KHR *pCopyImageToBufferInfo)
radv_CmdCopyImageToBuffer2(VkCommandBuffer commandBuffer,
const VkCopyImageToBufferInfo2 *pCopyImageToBufferInfo)
{
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
RADV_FROM_HANDLE(radv_image, src_image, pCopyImageToBufferInfo->srcImage);
@@ -407,7 +407,7 @@ radv_CmdCopyImageToBuffer2KHR(VkCommandBuffer commandBuffer,
static void
copy_image(struct radv_cmd_buffer *cmd_buffer, struct radv_image *src_image,
VkImageLayout src_image_layout, struct radv_image *dst_image,
VkImageLayout dst_image_layout, const VkImageCopy2KHR *region)
VkImageLayout dst_image_layout, const VkImageCopy2 *region)
{
struct radv_meta_saved_state saved_state;
bool old_predicating;
@@ -610,7 +610,7 @@ copy_image(struct radv_cmd_buffer *cmd_buffer, struct radv_image *src_image,
}
VKAPI_ATTR void VKAPI_CALL
radv_CmdCopyImage2KHR(VkCommandBuffer commandBuffer, const VkCopyImageInfo2KHR *pCopyImageInfo)
radv_CmdCopyImage2(VkCommandBuffer commandBuffer, const VkCopyImageInfo2 *pCopyImageInfo)
{
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
RADV_FROM_HANDLE(radv_image, src_image, pCopyImageInfo->srcImage);
src/amd/vulkan/radv_meta_copy_vrs_htile.c
+3 -3
View File
@@ -231,8 +231,8 @@ radv_copy_vrs_htile(struct radv_cmd_buffer *cmd_buffer, struct radv_image *vrs_i
}
cmd_buffer->state.flush_bits |=
radv_src_access_flush(cmd_buffer, VK_ACCESS_2_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT_KHR, NULL) |
radv_dst_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_READ_BIT_KHR, NULL);
radv_src_access_flush(cmd_buffer, VK_ACCESS_2_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT, NULL) |
radv_dst_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_READ_BIT, NULL);
radv_meta_save(
&saved_state, cmd_buffer,
@@ -300,5 +300,5 @@ radv_copy_vrs_htile(struct radv_cmd_buffer *cmd_buffer, struct radv_image *vrs_i
cmd_buffer->state.flush_bits |=
RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_INV_VCACHE |
radv_src_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_WRITE_BIT_KHR, NULL);
radv_src_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_WRITE_BIT, NULL);
}
src/amd/vulkan/radv_meta_dcc_retile.c
+3 -3
View File
@@ -191,8 +191,8 @@ radv_retile_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image)
struct radv_cmd_state *state = &cmd_buffer->state;
state->flush_bits |= radv_dst_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_READ_BIT_KHR, image) |
radv_dst_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_WRITE_BIT_KHR, image);
state->flush_bits |= radv_dst_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_READ_BIT, image) |
radv_dst_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_WRITE_BIT, image);
unsigned swizzle_mode = image->planes[0].surface.u.gfx9.swizzle_mode;
@@ -284,5 +284,5 @@ radv_retile_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image)
radv_meta_restore(&saved_state, cmd_buffer);
state->flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
radv_src_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_WRITE_BIT_KHR, image);
radv_src_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_WRITE_BIT, image);
}
src/amd/vulkan/radv_meta_decompress.c
+2 -2
View File
@@ -620,7 +620,7 @@ radv_expand_depth_stencil_compute(struct radv_cmd_buffer *cmd_buffer, struct rad
assert(radv_image_is_tc_compat_htile(image));
cmd_buffer->state.flush_bits |=
radv_dst_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_WRITE_BIT_KHR, image);
radv_dst_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_WRITE_BIT, image);
radv_meta_save(&saved_state, cmd_buffer,
RADV_META_SAVE_DESCRIPTORS | RADV_META_SAVE_COMPUTE_PIPELINE);
@@ -709,7 +709,7 @@ radv_expand_depth_stencil_compute(struct radv_cmd_buffer *cmd_buffer, struct rad
cmd_buffer->state.flush_bits |=
RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_INV_VCACHE |
radv_src_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_WRITE_BIT_KHR, image);
radv_src_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_WRITE_BIT, image);
/* Initialize the HTILE metadata as "fully expanded". */
uint32_t htile_value = radv_get_htile_initial_value(cmd_buffer->device, image);
src/amd/vulkan/radv_meta_fast_clear.c
+4 -4
View File
@@ -608,13 +608,13 @@ radv_process_color_image_layer(struct radv_cmd_buffer *cmd_buffer, struct radv_i
if (flush_cb)
cmd_buffer->state.flush_bits |=
radv_dst_access_flush(cmd_buffer, VK_ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT_KHR, image);
radv_dst_access_flush(cmd_buffer, VK_ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT, image);
radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer), 3, 1, 0, 0);
if (flush_cb)
cmd_buffer->state.flush_bits |=
radv_src_access_flush(cmd_buffer, VK_ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT_KHR, image);
radv_src_access_flush(cmd_buffer, VK_ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT, image);
radv_cmd_buffer_end_render_pass(cmd_buffer);
@@ -805,7 +805,7 @@ radv_decompress_dcc_compute(struct radv_cmd_buffer *cmd_buffer, struct radv_imag
struct radv_device *device = cmd_buffer->device;
cmd_buffer->state.flush_bits |=
radv_dst_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_WRITE_BIT_KHR, image);
radv_dst_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_WRITE_BIT, image);
if (!cmd_buffer->device->meta_state.fast_clear_flush.cmask_eliminate_pipeline) {
VkResult ret = radv_device_init_meta_fast_clear_flush_state_internal(cmd_buffer->device);
@@ -905,7 +905,7 @@ radv_decompress_dcc_compute(struct radv_cmd_buffer *cmd_buffer, struct radv_imag
cmd_buffer->state.flush_bits |=
RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_INV_VCACHE |
radv_src_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_WRITE_BIT_KHR, image);
radv_src_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_WRITE_BIT, image);
/* Initialize the DCC metadata as "fully expanded". */
cmd_buffer->state.flush_bits |= radv_init_dcc(cmd_buffer, image, subresourceRange, 0xffffffff);
src/amd/vulkan/radv_meta_fmask_expand.c
+2 -2
View File
@@ -106,7 +106,7 @@ radv_expand_fmask_image_inplace(struct radv_cmd_buffer *cmd_buffer, struct radv_
pipeline);
cmd_buffer->state.flush_bits |= radv_dst_access_flush(
cmd_buffer, VK_ACCESS_2_SHADER_READ_BIT_KHR | VK_ACCESS_2_SHADER_WRITE_BIT_KHR, image);
cmd_buffer, VK_ACCESS_2_SHADER_READ_BIT | VK_ACCESS_2_SHADER_WRITE_BIT, image);
radv_image_view_init(&iview, device,
&(VkImageViewCreateInfo){
@@ -159,7 +159,7 @@ radv_expand_fmask_image_inplace(struct radv_cmd_buffer *cmd_buffer, struct radv_
cmd_buffer->state.flush_bits |=
RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
radv_src_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_WRITE_BIT_KHR, image);
radv_src_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_WRITE_BIT, image);
/* Re-initialize FMASK in fully expanded mode. */
cmd_buffer->state.flush_bits |= radv_init_fmask(cmd_buffer, image, subresourceRange);
src/amd/vulkan/radv_meta_resolve.c
+24 -24
View File
@@ -322,9 +322,9 @@ emit_resolve(struct radv_cmd_buffer *cmd_buffer, const struct radv_image *src_im
unsigned fs_key = radv_format_meta_fs_key(device, vk_format);
cmd_buffer->state.flush_bits |=
radv_src_access_flush(cmd_buffer, VK_ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT_KHR, src_image) |
radv_dst_access_flush(cmd_buffer, VK_ACCESS_2_COLOR_ATTACHMENT_READ_BIT_KHR, src_image) |
radv_dst_access_flush(cmd_buffer, VK_ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT_KHR, dst_image);
radv_src_access_flush(cmd_buffer, VK_ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT, src_image) |
radv_dst_access_flush(cmd_buffer, VK_ACCESS_2_COLOR_ATTACHMENT_READ_BIT, src_image) |
radv_dst_access_flush(cmd_buffer, VK_ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT, dst_image);
radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
device->meta_state.resolve.pipeline[fs_key]);
@@ -345,7 +345,7 @@ emit_resolve(struct radv_cmd_buffer *cmd_buffer, const struct radv_image *src_im
radv_CmdDraw(cmd_buffer_h, 3, 1, 0, 0);
cmd_buffer->state.flush_bits |=
radv_src_access_flush(cmd_buffer, VK_ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT_KHR, dst_image);
radv_src_access_flush(cmd_buffer, VK_ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT, dst_image);
}
enum radv_resolve_method {
@@ -443,7 +443,7 @@ fail:
static void
radv_meta_resolve_hardware_image(struct radv_cmd_buffer *cmd_buffer, struct radv_image *src_image,
VkImageLayout src_image_layout, struct radv_image *dst_image,
VkImageLayout dst_image_layout, const VkImageResolve2KHR *region)
VkImageLayout dst_image_layout, const VkImageResolve2 *region)
{
struct radv_device *device = cmd_buffer->device;
struct radv_meta_saved_state saved_state;
@@ -611,7 +611,7 @@ radv_meta_resolve_hardware_image(struct radv_cmd_buffer *cmd_buffer, struct radv
static void
resolve_image(struct radv_cmd_buffer *cmd_buffer, struct radv_image *src_image,
VkImageLayout src_image_layout, struct radv_image *dst_image,
VkImageLayout dst_image_layout, const VkImageResolve2KHR *region,
VkImageLayout dst_image_layout, const VkImageResolve2 *region,
enum radv_resolve_method resolve_method)
{
switch (resolve_method) {
@@ -633,8 +633,8 @@ resolve_image(struct radv_cmd_buffer *cmd_buffer, struct radv_image *src_image,
}
VKAPI_ATTR void VKAPI_CALL
radv_CmdResolveImage2KHR(VkCommandBuffer commandBuffer,
const VkResolveImageInfo2KHR *pResolveImageInfo)
radv_CmdResolveImage2(VkCommandBuffer commandBuffer,
const VkResolveImageInfo2 *pResolveImageInfo)
{
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
RADV_FROM_HANDLE(radv_image, src_image, pResolveImageInfo->srcImage);
@@ -659,7 +659,7 @@ radv_CmdResolveImage2KHR(VkCommandBuffer commandBuffer,
resolve_method = RESOLVE_COMPUTE;
for (uint32_t r = 0; r < pResolveImageInfo->regionCount; r++) {
const VkImageResolve2KHR *region = &pResolveImageInfo->pRegions[r];
const VkImageResolve2 *region = &pResolveImageInfo->pRegions[r];
radv_pick_resolve_method_images(cmd_buffer->device, src_image, src_image->vk_format, dst_image,
region->dstSubresource.mipLevel, dst_image_layout, false,
@@ -763,7 +763,7 @@ radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer)
dst_att.in_render_loop, cmd_buffer, &resolve_method);
if ((src_iview->aspect_mask & VK_IMAGE_ASPECT_DEPTH_BIT) &&
subpass->depth_resolve_mode != VK_RESOLVE_MODE_NONE_KHR) {
subpass->depth_resolve_mode != VK_RESOLVE_MODE_NONE) {
if (resolve_method == RESOLVE_FRAGMENT) {
radv_depth_stencil_resolve_subpass_fs(cmd_buffer, VK_IMAGE_ASPECT_DEPTH_BIT,
subpass->depth_resolve_mode);
@@ -775,7 +775,7 @@ radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer)
}
if ((src_iview->aspect_mask & VK_IMAGE_ASPECT_STENCIL_BIT) &&
subpass->stencil_resolve_mode != VK_RESOLVE_MODE_NONE_KHR) {
subpass->stencil_resolve_mode != VK_RESOLVE_MODE_NONE) {
if (resolve_method == RESOLVE_FRAGMENT) {
radv_depth_stencil_resolve_subpass_fs(cmd_buffer, VK_IMAGE_ASPECT_STENCIL_BIT,
subpass->stencil_resolve_mode);
@@ -788,7 +788,7 @@ radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer *cmd_buffer)
/* From the Vulkan spec 1.2.165:
*
* "VK_ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT_KHR specifies
* "VK_ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT specifies
* write access to a color, resolve, or depth/stencil
* resolve attachment during a render pass or via
* certain subpass load and store operations."
@@ -876,8 +876,8 @@ radv_decompress_resolve_subpass_src(struct radv_cmd_buffer *cmd_buffer)
struct radv_image_view *src_iview = cmd_buffer->state.attachments[src_att.attachment].iview;
struct radv_image *src_image = src_iview->image;
VkImageResolve2KHR region = {0};
region.sType = VK_STRUCTURE_TYPE_IMAGE_RESOLVE_2_KHR;
VkImageResolve2 region = {0};
region.sType = VK_STRUCTURE_TYPE_IMAGE_RESOLVE_2;
region.srcSubresource.aspectMask = src_iview->aspect_mask;
region.srcSubresource.mipLevel = 0;
region.srcSubresource.baseArrayLayer = src_iview->base_layer;
@@ -906,17 +906,17 @@ radv_get_resolve_sample_locations(struct radv_cmd_buffer *cmd_buffer)
*/
void
radv_decompress_resolve_src(struct radv_cmd_buffer *cmd_buffer, struct radv_image *src_image,
VkImageLayout src_image_layout, const VkImageResolve2KHR *region)
VkImageLayout src_image_layout, const VkImageResolve2 *region)
{
const uint32_t src_base_layer =
radv_meta_get_iview_layer(src_image, &region->srcSubresource, &region->srcOffset);
VkImageMemoryBarrier2KHR barrier = {
.sType = VK_STRUCTURE_TYPE_IMAGE_MEMORY_BARRIER_2_KHR,
.srcStageMask = VK_PIPELINE_STAGE_2_TOP_OF_PIPE_BIT_KHR,
.srcAccessMask = VK_ACCESS_2_TRANSFER_WRITE_BIT_KHR,
.dstStageMask = VK_PIPELINE_STAGE_2_BOTTOM_OF_PIPE_BIT_KHR,
.dstAccessMask = VK_ACCESS_2_TRANSFER_READ_BIT_KHR,
VkImageMemoryBarrier2 barrier = {
.sType = VK_STRUCTURE_TYPE_IMAGE_MEMORY_BARRIER_2,
.srcStageMask = VK_PIPELINE_STAGE_2_TOP_OF_PIPE_BIT,
.srcAccessMask = VK_ACCESS_2_TRANSFER_WRITE_BIT,
.dstStageMask = VK_PIPELINE_STAGE_2_BOTTOM_OF_PIPE_BIT,
.dstAccessMask = VK_ACCESS_2_TRANSFER_READ_BIT,
.oldLayout = src_image_layout,
.newLayout = VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL,
.image = radv_image_to_handle(src_image),
@@ -945,11 +945,11 @@ radv_decompress_resolve_src(struct radv_cmd_buffer *cmd_buffer, struct radv_imag
};
}
VkDependencyInfoKHR dep_info = {
.sType = VK_STRUCTURE_TYPE_DEPENDENCY_INFO_KHR,
VkDependencyInfo dep_info = {
.sType = VK_STRUCTURE_TYPE_DEPENDENCY_INFO,
.imageMemoryBarrierCount = 1,
.pImageMemoryBarriers = &barrier,
};
radv_CmdPipelineBarrier2KHR(radv_cmd_buffer_to_handle(cmd_buffer), &dep_info);
radv_CmdPipelineBarrier2(radv_cmd_buffer_to_handle(cmd_buffer), &dep_info);
}
src/amd/vulkan/radv_meta_resolve_cs.c
+33 -33
View File
@@ -113,13 +113,13 @@ static const char *
get_resolve_mode_str(VkResolveModeFlagBits resolve_mode)
{
switch (resolve_mode) {
case VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR:
case VK_RESOLVE_MODE_SAMPLE_ZERO_BIT:
return "zero";
case VK_RESOLVE_MODE_AVERAGE_BIT_KHR:
case VK_RESOLVE_MODE_AVERAGE_BIT:
return "average";
case VK_RESOLVE_MODE_MIN_BIT_KHR:
case VK_RESOLVE_MODE_MIN_BIT:
return "min";
case VK_RESOLVE_MODE_MAX_BIT_KHR:
case VK_RESOLVE_MODE_MAX_BIT:
return "max";
default:
unreachable("invalid resolve mode");
@@ -172,7 +172,7 @@ build_depth_stencil_resolve_compute_shader(struct radv_device *dev, int samples,
nir_ssa_def *outval = &tex->dest.ssa;
if (resolve_mode != VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR) {
if (resolve_mode != VK_RESOLVE_MODE_SAMPLE_ZERO_BIT) {
for (int i = 1; i < samples; i++) {
nir_tex_instr *tex_add = nir_tex_instr_create(b.shader, 3);
tex_add->sampler_dim = GLSL_SAMPLER_DIM_MS;
@@ -191,17 +191,17 @@ build_depth_stencil_resolve_compute_shader(struct radv_device *dev, int samples,
nir_builder_instr_insert(&b, &tex_add->instr);
switch (resolve_mode) {
case VK_RESOLVE_MODE_AVERAGE_BIT_KHR:
case VK_RESOLVE_MODE_AVERAGE_BIT:
assert(index == DEPTH_RESOLVE);
outval = nir_fadd(&b, outval, &tex_add->dest.ssa);
break;
case VK_RESOLVE_MODE_MIN_BIT_KHR:
case VK_RESOLVE_MODE_MIN_BIT:
if (index == DEPTH_RESOLVE)
outval = nir_fmin(&b, outval, &tex_add->dest.ssa);
else
outval = nir_umin(&b, outval, &tex_add->dest.ssa);
break;
case VK_RESOLVE_MODE_MAX_BIT_KHR:
case VK_RESOLVE_MODE_MAX_BIT:
if (index == DEPTH_RESOLVE)
outval = nir_fmax(&b, outval, &tex_add->dest.ssa);
else
@@ -212,7 +212,7 @@ build_depth_stencil_resolve_compute_shader(struct radv_device *dev, int samples,
}
}
if (resolve_mode == VK_RESOLVE_MODE_AVERAGE_BIT_KHR)
if (resolve_mode == VK_RESOLVE_MODE_AVERAGE_BIT)
outval = nir_fdiv(&b, outval, nir_imm_float(&b, samples));
}
@@ -397,44 +397,44 @@ radv_device_init_meta_resolve_compute_state(struct radv_device *device, bool on_
goto fail;
res = create_depth_stencil_resolve_pipeline(
device, samples, DEPTH_RESOLVE, VK_RESOLVE_MODE_AVERAGE_BIT_KHR,
device, samples, DEPTH_RESOLVE, VK_RESOLVE_MODE_AVERAGE_BIT,
&state->resolve_compute.depth[i].average_pipeline);
if (res != VK_SUCCESS)
goto fail;
res = create_depth_stencil_resolve_pipeline(device, samples, DEPTH_RESOLVE,
VK_RESOLVE_MODE_MAX_BIT_KHR,
VK_RESOLVE_MODE_MAX_BIT,
&state->resolve_compute.depth[i].max_pipeline);
if (res != VK_SUCCESS)
goto fail;
res = create_depth_stencil_resolve_pipeline(device, samples, DEPTH_RESOLVE,
VK_RESOLVE_MODE_MIN_BIT_KHR,
VK_RESOLVE_MODE_MIN_BIT,
&state->resolve_compute.depth[i].min_pipeline);
if (res != VK_SUCCESS)
goto fail;
res = create_depth_stencil_resolve_pipeline(device, samples, STENCIL_RESOLVE,
VK_RESOLVE_MODE_MAX_BIT_KHR,
VK_RESOLVE_MODE_MAX_BIT,
&state->resolve_compute.stencil[i].max_pipeline);
if (res != VK_SUCCESS)
goto fail;
res = create_depth_stencil_resolve_pipeline(device, samples, STENCIL_RESOLVE,
VK_RESOLVE_MODE_MIN_BIT_KHR,
VK_RESOLVE_MODE_MIN_BIT,
&state->resolve_compute.stencil[i].min_pipeline);
if (res != VK_SUCCESS)
goto fail;
}
res = create_depth_stencil_resolve_pipeline(device, 0, DEPTH_RESOLVE,
VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR,
VK_RESOLVE_MODE_SAMPLE_ZERO_BIT,
&state->resolve_compute.depth_zero_pipeline);
if (res != VK_SUCCESS)
goto fail;
res = create_depth_stencil_resolve_pipeline(device, 0, STENCIL_RESOLVE,
VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR,
VK_RESOLVE_MODE_SAMPLE_ZERO_BIT,
&state->resolve_compute.stencil_zero_pipeline);
if (res != VK_SUCCESS)
goto fail;
@@ -609,23 +609,23 @@ emit_depth_stencil_resolve(struct radv_cmd_buffer *cmd_buffer, struct radv_image
}}});
switch (resolve_mode) {
case VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR:
case VK_RESOLVE_MODE_SAMPLE_ZERO_BIT:
if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT)
pipeline = &device->meta_state.resolve_compute.depth_zero_pipeline;
else
pipeline = &device->meta_state.resolve_compute.stencil_zero_pipeline;
break;
case VK_RESOLVE_MODE_AVERAGE_BIT_KHR:
case VK_RESOLVE_MODE_AVERAGE_BIT:
assert(aspects == VK_IMAGE_ASPECT_DEPTH_BIT);
pipeline = &device->meta_state.resolve_compute.depth[samples_log2].average_pipeline;
break;
case VK_RESOLVE_MODE_MIN_BIT_KHR:
case VK_RESOLVE_MODE_MIN_BIT:
if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT)
pipeline = &device->meta_state.resolve_compute.depth[samples_log2].min_pipeline;
else
pipeline = &device->meta_state.resolve_compute.stencil[samples_log2].min_pipeline;
break;
case VK_RESOLVE_MODE_MAX_BIT_KHR:
case VK_RESOLVE_MODE_MAX_BIT:
if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT)
pipeline = &device->meta_state.resolve_compute.depth[samples_log2].max_pipeline;
else
@@ -657,7 +657,7 @@ void
radv_meta_resolve_compute_image(struct radv_cmd_buffer *cmd_buffer, struct radv_image *src_image,
VkFormat src_format, VkImageLayout src_image_layout,
struct radv_image *dest_image, VkFormat dest_format,
VkImageLayout dest_image_layout, const VkImageResolve2KHR *region)
VkImageLayout dest_image_layout, const VkImageResolve2 *region)
{
struct radv_meta_saved_state saved_state;
@@ -789,9 +789,9 @@ radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer)
/* Resolves happen before the end-of-subpass barriers get executed, so
* we have to make the attachment shader-readable.
*/
barrier.src_stage_mask = VK_PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT_KHR;
barrier.src_access_mask = VK_ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT_KHR;
barrier.dst_access_mask = VK_ACCESS_2_SHADER_READ_BIT_KHR | VK_ACCESS_2_SHADER_WRITE_BIT_KHR;
barrier.src_stage_mask = VK_PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT;
barrier.src_access_mask = VK_ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT;
barrier.dst_access_mask = VK_ACCESS_2_SHADER_READ_BIT | VK_ACCESS_2_SHADER_WRITE_BIT;
radv_emit_subpass_barrier(cmd_buffer, &barrier);
for (uint32_t i = 0; i < subpass->color_count; ++i) {
@@ -804,8 +804,8 @@ radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer)
struct radv_image_view *src_iview = cmd_buffer->state.attachments[src_att.attachment].iview;
struct radv_image_view *dst_iview = cmd_buffer->state.attachments[dst_att.attachment].iview;
VkImageResolve2KHR region = {
.sType = VK_STRUCTURE_TYPE_IMAGE_RESOLVE_2_KHR,
VkImageResolve2 region = {
.sType = VK_STRUCTURE_TYPE_IMAGE_RESOLVE_2,
.extent = (VkExtent3D){fb->width, fb->height, 1},
.srcSubresource =
(VkImageSubresourceLayers){
@@ -832,7 +832,7 @@ radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer)
cmd_buffer->state.flush_bits |=
RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_INV_VCACHE |
radv_src_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_WRITE_BIT_KHR, NULL);
radv_src_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_WRITE_BIT, NULL);
}
void
@@ -852,16 +852,16 @@ radv_depth_stencil_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer,
* we have to make the attachment shader-readable.
*/
cmd_buffer->state.flush_bits |=
radv_src_access_flush(cmd_buffer, VK_ACCESS_2_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT_KHR, NULL) |
radv_dst_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_READ_BIT_KHR, NULL) |
radv_dst_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_WRITE_BIT_KHR, NULL);
radv_src_access_flush(cmd_buffer, VK_ACCESS_2_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT, NULL) |
radv_dst_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_READ_BIT, NULL) |
radv_dst_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_WRITE_BIT, NULL);
struct radv_subpass_attachment src_att = *subpass->depth_stencil_attachment;
struct radv_image_view *src_iview = cmd_buffer->state.attachments[src_att.attachment].iview;
struct radv_image *src_image = src_iview->image;
VkImageResolve2KHR region = {0};
region.sType = VK_STRUCTURE_TYPE_IMAGE_RESOLVE_2_KHR;
VkImageResolve2 region = {0};
region.sType = VK_STRUCTURE_TYPE_IMAGE_RESOLVE_2;
region.srcSubresource.aspectMask = aspects;
region.srcSubresource.mipLevel = 0;
region.srcSubresource.baseArrayLayer = src_iview->base_layer;
@@ -918,7 +918,7 @@ radv_depth_stencil_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer,
cmd_buffer->state.flush_bits |=
RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_INV_VCACHE |
radv_src_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_WRITE_BIT_KHR, NULL);
radv_src_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_WRITE_BIT, NULL);
VkImageLayout layout = cmd_buffer->state.attachments[dest_att.attachment].current_layout;
uint32_t queue_mask = radv_image_queue_family_mask(dst_image, cmd_buffer->qf,
src/amd/vulkan/radv_meta_resolve_fs.c
+36 -36
View File
@@ -308,13 +308,13 @@ static const char *
get_resolve_mode_str(VkResolveModeFlagBits resolve_mode)
{
switch (resolve_mode) {
case VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR:
case VK_RESOLVE_MODE_SAMPLE_ZERO_BIT:
return "zero";
case VK_RESOLVE_MODE_AVERAGE_BIT_KHR:
case VK_RESOLVE_MODE_AVERAGE_BIT:
return "average";
case VK_RESOLVE_MODE_MIN_BIT_KHR:
case VK_RESOLVE_MODE_MIN_BIT:
return "min";
case VK_RESOLVE_MODE_MAX_BIT_KHR:
case VK_RESOLVE_MODE_MAX_BIT:
return "max";
default:
unreachable("invalid resolve mode");
@@ -368,7 +368,7 @@ build_depth_stencil_resolve_fragment_shader(struct radv_device *dev, int samples
nir_ssa_def *outval = &tex->dest.ssa;
if (resolve_mode != VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR) {
if (resolve_mode != VK_RESOLVE_MODE_SAMPLE_ZERO_BIT) {
for (int i = 1; i < samples; i++) {
nir_tex_instr *tex_add = nir_tex_instr_create(b.shader, 3);
tex_add->sampler_dim = GLSL_SAMPLER_DIM_MS;
@@ -387,17 +387,17 @@ build_depth_stencil_resolve_fragment_shader(struct radv_device *dev, int samples
nir_builder_instr_insert(&b, &tex_add->instr);
switch (resolve_mode) {
case VK_RESOLVE_MODE_AVERAGE_BIT_KHR:
case VK_RESOLVE_MODE_AVERAGE_BIT:
assert(index == DEPTH_RESOLVE);
outval = nir_fadd(&b, outval, &tex_add->dest.ssa);
break;
case VK_RESOLVE_MODE_MIN_BIT_KHR:
case VK_RESOLVE_MODE_MIN_BIT:
if (index == DEPTH_RESOLVE)
outval = nir_fmin(&b, outval, &tex_add->dest.ssa);
else
outval = nir_umin(&b, outval, &tex_add->dest.ssa);
break;
case VK_RESOLVE_MODE_MAX_BIT_KHR:
case VK_RESOLVE_MODE_MAX_BIT:
if (index == DEPTH_RESOLVE)
outval = nir_fmax(&b, outval, &tex_add->dest.ssa);
else
@@ -408,7 +408,7 @@ build_depth_stencil_resolve_fragment_shader(struct radv_device *dev, int samples
}
}
if (resolve_mode == VK_RESOLVE_MODE_AVERAGE_BIT_KHR)
if (resolve_mode == VK_RESOLVE_MODE_AVERAGE_BIT)
outval = nir_fdiv(&b, outval, nir_imm_float(&b, samples));
}
@@ -429,23 +429,23 @@ create_depth_stencil_resolve_pipeline(struct radv_device *device, int samples_lo
mtx_lock(&device->meta_state.mtx);
switch (resolve_mode) {
case VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR:
case VK_RESOLVE_MODE_SAMPLE_ZERO_BIT:
if (index == DEPTH_RESOLVE)
pipeline = &device->meta_state.resolve_fragment.depth_zero_pipeline;
else
pipeline = &device->meta_state.resolve_fragment.stencil_zero_pipeline;
break;
case VK_RESOLVE_MODE_AVERAGE_BIT_KHR:
case VK_RESOLVE_MODE_AVERAGE_BIT:
assert(index == DEPTH_RESOLVE);
pipeline = &device->meta_state.resolve_fragment.depth[samples_log2].average_pipeline;
break;
case VK_RESOLVE_MODE_MIN_BIT_KHR:
case VK_RESOLVE_MODE_MIN_BIT:
if (index == DEPTH_RESOLVE)
pipeline = &device->meta_state.resolve_fragment.depth[samples_log2].min_pipeline;
else
pipeline = &device->meta_state.resolve_fragment.stencil[samples_log2].min_pipeline;
break;
case VK_RESOLVE_MODE_MAX_BIT_KHR:
case VK_RESOLVE_MODE_MAX_BIT:
if (index == DEPTH_RESOLVE)
pipeline = &device->meta_state.resolve_fragment.depth[samples_log2].max_pipeline;
else
@@ -665,38 +665,38 @@ radv_device_init_meta_resolve_fragment_state(struct radv_device *device, bool on
}
res = create_depth_stencil_resolve_pipeline(device, i, DEPTH_RESOLVE,
VK_RESOLVE_MODE_AVERAGE_BIT_KHR);
VK_RESOLVE_MODE_AVERAGE_BIT);
if (res != VK_SUCCESS)
goto fail;
res = create_depth_stencil_resolve_pipeline(device, i, DEPTH_RESOLVE,
VK_RESOLVE_MODE_MIN_BIT_KHR);
VK_RESOLVE_MODE_MIN_BIT);
if (res != VK_SUCCESS)
goto fail;
res = create_depth_stencil_resolve_pipeline(device, i, DEPTH_RESOLVE,
VK_RESOLVE_MODE_MAX_BIT_KHR);
VK_RESOLVE_MODE_MAX_BIT);
if (res != VK_SUCCESS)
goto fail;
res = create_depth_stencil_resolve_pipeline(device, i, STENCIL_RESOLVE,
VK_RESOLVE_MODE_MIN_BIT_KHR);
VK_RESOLVE_MODE_MIN_BIT);
if (res != VK_SUCCESS)
goto fail;
res = create_depth_stencil_resolve_pipeline(device, i, STENCIL_RESOLVE,
VK_RESOLVE_MODE_MAX_BIT_KHR);
VK_RESOLVE_MODE_MAX_BIT);
if (res != VK_SUCCESS)
goto fail;
}
res = create_depth_stencil_resolve_pipeline(device, 0, DEPTH_RESOLVE,
VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR);
VK_RESOLVE_MODE_SAMPLE_ZERO_BIT);
if (res != VK_SUCCESS)
goto fail;
res = create_depth_stencil_resolve_pipeline(device, 0, STENCIL_RESOLVE,
VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR);
VK_RESOLVE_MODE_SAMPLE_ZERO_BIT);
if (res != VK_SUCCESS)
goto fail;
@@ -806,8 +806,8 @@ emit_resolve(struct radv_cmd_buffer *cmd_buffer, struct radv_image_view *src_ivi
});
cmd_buffer->state.flush_bits |=
radv_dst_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_READ_BIT_KHR, src_iview->image) |
radv_dst_access_flush(cmd_buffer, VK_ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT_KHR, dest_iview->image);
radv_dst_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_READ_BIT, src_iview->image) |
radv_dst_access_flush(cmd_buffer, VK_ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT, dest_iview->image);
unsigned push_constants[2] = {
src_offset->x - dest_offset->x,
@@ -837,7 +837,7 @@ emit_resolve(struct radv_cmd_buffer *cmd_buffer, struct radv_image_view *src_ivi
radv_CmdDraw(cmd_buffer_h, 3, 1, 0, 0);
cmd_buffer->state.flush_bits |=
radv_src_access_flush(cmd_buffer, VK_ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT_KHR, dest_iview->image);
radv_src_access_flush(cmd_buffer, VK_ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT, dest_iview->image);
}
static void
@@ -871,23 +871,23 @@ emit_depth_stencil_resolve(struct radv_cmd_buffer *cmd_buffer, struct radv_image
});
switch (resolve_mode) {
case VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR:
case VK_RESOLVE_MODE_SAMPLE_ZERO_BIT:
if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT)
pipeline = &device->meta_state.resolve_fragment.depth_zero_pipeline;
else
pipeline = &device->meta_state.resolve_fragment.stencil_zero_pipeline;
break;
case VK_RESOLVE_MODE_AVERAGE_BIT_KHR:
case VK_RESOLVE_MODE_AVERAGE_BIT:
assert(aspects == VK_IMAGE_ASPECT_DEPTH_BIT);
pipeline = &device->meta_state.resolve_fragment.depth[samples_log2].average_pipeline;
break;
case VK_RESOLVE_MODE_MIN_BIT_KHR:
case VK_RESOLVE_MODE_MIN_BIT:
if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT)
pipeline = &device->meta_state.resolve_fragment.depth[samples_log2].min_pipeline;
else
pipeline = &device->meta_state.resolve_fragment.stencil[samples_log2].min_pipeline;
break;
case VK_RESOLVE_MODE_MAX_BIT_KHR:
case VK_RESOLVE_MODE_MAX_BIT:
if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT)
pipeline = &device->meta_state.resolve_fragment.depth[samples_log2].max_pipeline;
else
@@ -931,7 +931,7 @@ emit_depth_stencil_resolve(struct radv_cmd_buffer *cmd_buffer, struct radv_image
void
radv_meta_resolve_fragment_image(struct radv_cmd_buffer *cmd_buffer, struct radv_image *src_image,
VkImageLayout src_image_layout, struct radv_image *dest_image,
VkImageLayout dest_image_layout, const VkImageResolve2KHR *region)
VkImageLayout dest_image_layout, const VkImageResolve2 *region)
{
struct radv_device *device = cmd_buffer->device;
struct radv_meta_saved_state saved_state;
@@ -1075,9 +1075,9 @@ radv_cmd_buffer_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer)
/* Resolves happen before the end-of-subpass barriers get executed,
* so we have to make the attachment shader-readable */
barrier.src_stage_mask = VK_PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT_KHR;
barrier.src_access_mask = VK_ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT_KHR;
barrier.dst_access_mask = VK_ACCESS_2_INPUT_ATTACHMENT_READ_BIT_KHR;
barrier.src_stage_mask = VK_PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT;
barrier.src_access_mask = VK_ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT;
barrier.dst_access_mask = VK_ACCESS_2_INPUT_ATTACHMENT_READ_BIT;
radv_emit_subpass_barrier(cmd_buffer, &barrier);
radv_decompress_resolve_subpass_src(cmd_buffer);
@@ -1128,17 +1128,17 @@ radv_depth_stencil_resolve_subpass_fs(struct radv_cmd_buffer *cmd_buffer,
/* Resolves happen before the end-of-subpass barriers get executed,
* so we have to make the attachment shader-readable */
barrier.src_stage_mask = VK_PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT_KHR;
barrier.src_access_mask = VK_ACCESS_2_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT_KHR;
barrier.dst_access_mask = VK_ACCESS_2_INPUT_ATTACHMENT_READ_BIT_KHR;
barrier.src_stage_mask = VK_PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT;
barrier.src_access_mask = VK_ACCESS_2_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT;
barrier.dst_access_mask = VK_ACCESS_2_INPUT_ATTACHMENT_READ_BIT;
radv_emit_subpass_barrier(cmd_buffer, &barrier);
struct radv_subpass_attachment src_att = *subpass->depth_stencil_attachment;
struct radv_image_view *src_iview = cmd_buffer->state.attachments[src_att.attachment].iview;
struct radv_image *src_image = src_iview->image;
VkImageResolve2KHR region = {0};
region.sType = VK_STRUCTURE_TYPE_IMAGE_RESOLVE_2_KHR;
VkImageResolve2 region = {0};
region.sType = VK_STRUCTURE_TYPE_IMAGE_RESOLVE_2;
region.srcSubresource.aspectMask = aspects;
region.srcSubresource.mipLevel = 0;
region.srcSubresource.baseArrayLayer = 0;
src/amd/vulkan/radv_nir_apply_pipeline_layout.c
+2 -2
View File
@@ -179,12 +179,12 @@ load_buffer_descriptor(nir_builder *b, apply_layout_state *state, nir_ssa_def *r
nir_binding binding = nir_chase_binding(nir_src_for_ssa(rsrc));
/* If binding.success=false, then this is a variable pointer, which we don't support with
* VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT.
* VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK.
*/
if (binding.success) {
struct radv_descriptor_set_layout *layout =
state->pipeline_layout->set[binding.desc_set].layout;
if (layout->binding[binding.binding].type == VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT) {
if (layout->binding[binding.binding].type == VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK) {
rsrc = nir_iadd(b, nir_channel(b, rsrc, 0), nir_channel(b, rsrc, 1));
return load_inline_buffer_descriptor(b, state, rsrc);
}
src/amd/vulkan/radv_pass.c
+8 -8
View File
@@ -52,20 +52,20 @@ radv_render_pass_add_subpass_dep(struct radv_render_pass *pass, const VkSubpassD
* dstStageMask, srcAccessMask, and dstAccessMask parameters are ignored. The synchronization
* and access scopes instead are defined by the parameters of VkMemoryBarrier2."
*/
const VkMemoryBarrier2KHR *barrier =
vk_find_struct_const(dep->pNext, MEMORY_BARRIER_2_KHR);
VkPipelineStageFlags2KHR src_stage_mask = barrier ? barrier->srcStageMask : dep->srcStageMask;
VkAccessFlags2KHR src_access_mask = barrier ? barrier->srcAccessMask : dep->srcAccessMask;
VkPipelineStageFlags2KHR dst_stage_mask = barrier ? barrier->dstStageMask : dep->dstStageMask;
VkAccessFlags2KHR dst_access_mask = barrier ? barrier->dstAccessMask : dep->dstAccessMask;
const VkMemoryBarrier2 *barrier =
vk_find_struct_const(dep->pNext, MEMORY_BARRIER_2);
VkPipelineStageFlags2 src_stage_mask = barrier ? barrier->srcStageMask : dep->srcStageMask;
VkAccessFlags2 src_access_mask = barrier ? barrier->srcAccessMask : dep->srcAccessMask;
VkPipelineStageFlags2 dst_stage_mask = barrier ? barrier->dstStageMask : dep->dstStageMask;
VkAccessFlags2 dst_access_mask = barrier ? barrier->dstAccessMask : dep->dstAccessMask;
if (dst == VK_SUBPASS_EXTERNAL) {
if (dst_stage_mask != VK_PIPELINE_STAGE_2_BOTTOM_OF_PIPE_BIT_KHR)
if (dst_stage_mask != VK_PIPELINE_STAGE_2_BOTTOM_OF_PIPE_BIT)
pass->end_barrier.src_stage_mask |= src_stage_mask;
pass->end_barrier.src_access_mask |= src_access_mask;
pass->end_barrier.dst_access_mask |= dst_access_mask;
} else {
if (dst_stage_mask != VK_PIPELINE_STAGE_2_BOTTOM_OF_PIPE_BIT_KHR)
if (dst_stage_mask != VK_PIPELINE_STAGE_2_BOTTOM_OF_PIPE_BIT)
pass->subpasses[dst].start_barrier.src_stage_mask |= src_stage_mask;
pass->subpasses[dst].start_barrier.src_access_mask |= src_access_mask;
pass->subpasses[dst].start_barrier.dst_access_mask |= dst_access_mask;
src/amd/vulkan/radv_pipeline.c
+58 -58
View File
@@ -105,7 +105,7 @@ static const VkPipelineMultisampleStateCreateInfo *
radv_pipeline_get_multisample_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
{
if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable ||
radv_is_state_dynamic(pCreateInfo, VK_DYNAMIC_STATE_RASTERIZER_DISCARD_ENABLE_EXT))
radv_is_state_dynamic(pCreateInfo, VK_DYNAMIC_STATE_RASTERIZER_DISCARD_ENABLE))
return pCreateInfo->pMultisampleState;
return NULL;
}
@@ -125,8 +125,8 @@ radv_pipeline_get_tessellation_state(const VkGraphicsPipelineCreateInfo *pCreate
static bool
radv_pipeline_has_ds_attachments(const VkGraphicsPipelineCreateInfo *pCreateInfo)
{
const VkPipelineRenderingCreateInfoKHR *render_create_info =
vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RENDERING_CREATE_INFO_KHR);
const VkPipelineRenderingCreateInfo *render_create_info =
vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RENDERING_CREATE_INFO);
return render_create_info &&
(render_create_info->depthAttachmentFormat != VK_FORMAT_UNDEFINED ||
render_create_info->stencilAttachmentFormat != VK_FORMAT_UNDEFINED);
@@ -138,7 +138,7 @@ radv_pipeline_get_depth_stencil_state(const VkGraphicsPipelineCreateInfo *pCreat
bool has_ds_att = radv_pipeline_has_ds_attachments(pCreateInfo);
if ((!pCreateInfo->pRasterizationState->rasterizerDiscardEnable && has_ds_att) ||
radv_is_state_dynamic(pCreateInfo, VK_DYNAMIC_STATE_RASTERIZER_DISCARD_ENABLE_EXT))
radv_is_state_dynamic(pCreateInfo, VK_DYNAMIC_STATE_RASTERIZER_DISCARD_ENABLE))
return pCreateInfo->pDepthStencilState;
return NULL;
}
@@ -146,8 +146,8 @@ radv_pipeline_get_depth_stencil_state(const VkGraphicsPipelineCreateInfo *pCreat
static bool
radv_pipeline_has_color_attachments(const VkGraphicsPipelineCreateInfo *pCreateInfo)
{
const VkPipelineRenderingCreateInfoKHR *render_create_info =
vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RENDERING_CREATE_INFO_KHR);
const VkPipelineRenderingCreateInfo *render_create_info =
vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RENDERING_CREATE_INFO);
if (render_create_info) {
for (uint32_t i = 0; i < render_create_info->colorAttachmentCount; ++i) {
@@ -165,7 +165,7 @@ radv_pipeline_get_color_blend_state(const VkGraphicsPipelineCreateInfo *pCreateI
bool has_color_att = radv_pipeline_has_color_attachments(pCreateInfo);
if ((!pCreateInfo->pRasterizationState->rasterizerDiscardEnable && has_color_att) ||
radv_is_state_dynamic(pCreateInfo, VK_DYNAMIC_STATE_RASTERIZER_DISCARD_ENABLE_EXT))
radv_is_state_dynamic(pCreateInfo, VK_DYNAMIC_STATE_RASTERIZER_DISCARD_ENABLE))
return pCreateInfo->pColorBlendState;
return NULL;
}
@@ -535,8 +535,8 @@ radv_pipeline_compute_spi_color_formats(const struct radv_pipeline *pipeline,
const VkGraphicsPipelineCreateInfo *pCreateInfo,
struct radv_blend_state *blend)
{
const VkPipelineRenderingCreateInfoKHR *render_create_info =
vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RENDERING_CREATE_INFO_KHR);
const VkPipelineRenderingCreateInfo *render_create_info =
vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RENDERING_CREATE_INFO);
unsigned col_format = 0, is_int8 = 0, is_int10 = 0;
unsigned num_targets;
@@ -867,8 +867,8 @@ radv_pipeline_color_samples(const VkGraphicsPipelineCreateInfo *pCreateInfo)
{
const VkAttachmentSampleCountInfoAMD *sample_info =
vk_find_struct_const(pCreateInfo->pNext, ATTACHMENT_SAMPLE_COUNT_INFO_AMD);
const VkPipelineRenderingCreateInfoKHR *render_create_info =
vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RENDERING_CREATE_INFO_KHR);
const VkPipelineRenderingCreateInfo *render_create_info =
vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RENDERING_CREATE_INFO);
if (sample_info && render_create_info && sample_info->colorAttachmentCount > 0) {
unsigned samples = 1;
for (uint32_t i = 0; i < sample_info->colorAttachmentCount; ++i) {
@@ -887,8 +887,8 @@ radv_pipeline_depth_samples(const VkGraphicsPipelineCreateInfo *pCreateInfo)
{
const VkAttachmentSampleCountInfoAMD *sample_info =
vk_find_struct_const(pCreateInfo->pNext, ATTACHMENT_SAMPLE_COUNT_INFO_AMD);
const VkPipelineRenderingCreateInfoKHR *render_create_info =
vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RENDERING_CREATE_INFO_KHR);
const VkPipelineRenderingCreateInfo *render_create_info =
vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RENDERING_CREATE_INFO);
if (sample_info && render_create_info) {
if (render_create_info->depthAttachmentFormat != VK_FORMAT_UNDEFINED ||
render_create_info->stencilAttachmentFormat != VK_FORMAT_UNDEFINED) {
@@ -973,9 +973,9 @@ static bool
radv_pipeline_has_dynamic_ds_states(const VkGraphicsPipelineCreateInfo *pCreateInfo)
{
VkDynamicState ds_states[] = {
VK_DYNAMIC_STATE_DEPTH_TEST_ENABLE_EXT, VK_DYNAMIC_STATE_DEPTH_WRITE_ENABLE_EXT,
VK_DYNAMIC_STATE_DEPTH_COMPARE_OP_EXT, VK_DYNAMIC_STATE_STENCIL_TEST_ENABLE_EXT,
VK_DYNAMIC_STATE_STENCIL_OP_EXT,
VK_DYNAMIC_STATE_DEPTH_TEST_ENABLE, VK_DYNAMIC_STATE_DEPTH_WRITE_ENABLE,
VK_DYNAMIC_STATE_DEPTH_COMPARE_OP, VK_DYNAMIC_STATE_STENCIL_TEST_ENABLE,
VK_DYNAMIC_STATE_STENCIL_OP,
};
for (uint32_t i = 0; i < ARRAY_SIZE(ds_states); i++) {
@@ -991,8 +991,8 @@ radv_pipeline_out_of_order_rast(struct radv_pipeline *pipeline,
const struct radv_blend_state *blend,
const VkGraphicsPipelineCreateInfo *pCreateInfo)
{
const VkPipelineRenderingCreateInfoKHR *render_create_info =
vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RENDERING_CREATE_INFO_KHR);
const VkPipelineRenderingCreateInfo *render_create_info =
vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RENDERING_CREATE_INFO);
const VkPipelineDepthStencilStateCreateInfo *vkds =
radv_pipeline_get_depth_stencil_state(pCreateInfo);
const VkPipelineColorBlendStateCreateInfo *vkblend =
@@ -1324,10 +1324,10 @@ radv_dynamic_state_mask(VkDynamicState state)
{
switch (state) {
case VK_DYNAMIC_STATE_VIEWPORT:
case VK_DYNAMIC_STATE_VIEWPORT_WITH_COUNT_EXT:
case VK_DYNAMIC_STATE_VIEWPORT_WITH_COUNT:
return RADV_DYNAMIC_VIEWPORT;
case VK_DYNAMIC_STATE_SCISSOR:
case VK_DYNAMIC_STATE_SCISSOR_WITH_COUNT_EXT:
case VK_DYNAMIC_STATE_SCISSOR_WITH_COUNT:
return RADV_DYNAMIC_SCISSOR;
case VK_DYNAMIC_STATE_LINE_WIDTH:
return RADV_DYNAMIC_LINE_WIDTH;
@@ -1349,37 +1349,37 @@ radv_dynamic_state_mask(VkDynamicState state)
return RADV_DYNAMIC_SAMPLE_LOCATIONS;
case VK_DYNAMIC_STATE_LINE_STIPPLE_EXT:
return RADV_DYNAMIC_LINE_STIPPLE;
case VK_DYNAMIC_STATE_CULL_MODE_EXT:
case VK_DYNAMIC_STATE_CULL_MODE:
return RADV_DYNAMIC_CULL_MODE;
case VK_DYNAMIC_STATE_FRONT_FACE_EXT:
case VK_DYNAMIC_STATE_FRONT_FACE:
return RADV_DYNAMIC_FRONT_FACE;
case VK_DYNAMIC_STATE_PRIMITIVE_TOPOLOGY_EXT:
case VK_DYNAMIC_STATE_PRIMITIVE_TOPOLOGY:
return RADV_DYNAMIC_PRIMITIVE_TOPOLOGY;
case VK_DYNAMIC_STATE_DEPTH_TEST_ENABLE_EXT:
case VK_DYNAMIC_STATE_DEPTH_TEST_ENABLE:
return RADV_DYNAMIC_DEPTH_TEST_ENABLE;
case VK_DYNAMIC_STATE_DEPTH_WRITE_ENABLE_EXT:
case VK_DYNAMIC_STATE_DEPTH_WRITE_ENABLE:
return RADV_DYNAMIC_DEPTH_WRITE_ENABLE;
case VK_DYNAMIC_STATE_DEPTH_COMPARE_OP_EXT:
case VK_DYNAMIC_STATE_DEPTH_COMPARE_OP:
return RADV_DYNAMIC_DEPTH_COMPARE_OP;
case VK_DYNAMIC_STATE_DEPTH_BOUNDS_TEST_ENABLE_EXT:
case VK_DYNAMIC_STATE_DEPTH_BOUNDS_TEST_ENABLE:
return RADV_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE;
case VK_DYNAMIC_STATE_STENCIL_TEST_ENABLE_EXT:
case VK_DYNAMIC_STATE_STENCIL_TEST_ENABLE:
return RADV_DYNAMIC_STENCIL_TEST_ENABLE;
case VK_DYNAMIC_STATE_STENCIL_OP_EXT:
case VK_DYNAMIC_STATE_STENCIL_OP:
return RADV_DYNAMIC_STENCIL_OP;
case VK_DYNAMIC_STATE_VERTEX_INPUT_BINDING_STRIDE_EXT:
case VK_DYNAMIC_STATE_VERTEX_INPUT_BINDING_STRIDE:
return RADV_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE;
case VK_DYNAMIC_STATE_FRAGMENT_SHADING_RATE_KHR:
return RADV_DYNAMIC_FRAGMENT_SHADING_RATE;
case VK_DYNAMIC_STATE_PATCH_CONTROL_POINTS_EXT:
return RADV_DYNAMIC_PATCH_CONTROL_POINTS;
case VK_DYNAMIC_STATE_RASTERIZER_DISCARD_ENABLE_EXT:
case VK_DYNAMIC_STATE_RASTERIZER_DISCARD_ENABLE:
return RADV_DYNAMIC_RASTERIZER_DISCARD_ENABLE;
case VK_DYNAMIC_STATE_DEPTH_BIAS_ENABLE_EXT:
case VK_DYNAMIC_STATE_DEPTH_BIAS_ENABLE:
return RADV_DYNAMIC_DEPTH_BIAS_ENABLE;
case VK_DYNAMIC_STATE_LOGIC_OP_EXT:
return RADV_DYNAMIC_LOGIC_OP;
case VK_DYNAMIC_STATE_PRIMITIVE_RESTART_ENABLE_EXT:
case VK_DYNAMIC_STATE_PRIMITIVE_RESTART_ENABLE:
return RADV_DYNAMIC_PRIMITIVE_RESTART_ENABLE;
case VK_DYNAMIC_STATE_COLOR_WRITE_ENABLE_EXT:
return RADV_DYNAMIC_COLOR_WRITE_ENABLE;
@@ -1413,7 +1413,7 @@ radv_pipeline_needed_dynamic_state(const struct radv_pipeline *pipeline,
bool has_color_att = radv_pipeline_has_color_attachments(pCreateInfo);
bool has_static_rasterizer_discard =
pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
!radv_is_state_dynamic(pCreateInfo, VK_DYNAMIC_STATE_RASTERIZER_DISCARD_ENABLE_EXT);
!radv_is_state_dynamic(pCreateInfo, VK_DYNAMIC_STATE_RASTERIZER_DISCARD_ENABLE);
uint64_t states = RADV_DYNAMIC_ALL;
/* Disable dynamic states that are useless to mesh shading. */
@@ -1437,17 +1437,17 @@ radv_pipeline_needed_dynamic_state(const struct radv_pipeline *pipeline,
}
if (!pCreateInfo->pRasterizationState->depthBiasEnable &&
!radv_is_state_dynamic(pCreateInfo, VK_DYNAMIC_STATE_DEPTH_BIAS_ENABLE_EXT))
!radv_is_state_dynamic(pCreateInfo, VK_DYNAMIC_STATE_DEPTH_BIAS_ENABLE))
states &= ~RADV_DYNAMIC_DEPTH_BIAS;
if (!pCreateInfo->pDepthStencilState ||
(!pCreateInfo->pDepthStencilState->depthBoundsTestEnable &&
!radv_is_state_dynamic(pCreateInfo, VK_DYNAMIC_STATE_DEPTH_BOUNDS_TEST_ENABLE_EXT)))
!radv_is_state_dynamic(pCreateInfo, VK_DYNAMIC_STATE_DEPTH_BOUNDS_TEST_ENABLE)))
states &= ~RADV_DYNAMIC_DEPTH_BOUNDS;
if (!pCreateInfo->pDepthStencilState ||
(!pCreateInfo->pDepthStencilState->stencilTestEnable &&
!radv_is_state_dynamic(pCreateInfo, VK_DYNAMIC_STATE_STENCIL_TEST_ENABLE_EXT)))
!radv_is_state_dynamic(pCreateInfo, VK_DYNAMIC_STATE_STENCIL_TEST_ENABLE)))
states &= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK | RADV_DYNAMIC_STENCIL_WRITE_MASK |
RADV_DYNAMIC_STENCIL_REFERENCE);
@@ -1891,8 +1891,8 @@ radv_pipeline_init_depth_stencil_state(struct radv_pipeline *pipeline,
{
const VkPipelineDepthStencilStateCreateInfo *ds_info =
radv_pipeline_get_depth_stencil_state(pCreateInfo);
const VkPipelineRenderingCreateInfoKHR *render_create_info =
vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RENDERING_CREATE_INFO_KHR);
const VkPipelineRenderingCreateInfo *render_create_info =
vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RENDERING_CREATE_INFO);
struct radv_shader *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
struct radv_depth_stencil_state ds_state = {0};
uint32_t db_depth_control = 0;
@@ -2869,8 +2869,8 @@ radv_generate_graphics_pipeline_key(const struct radv_pipeline *pipeline,
const VkGraphicsPipelineCreateInfo *pCreateInfo,
const struct radv_blend_state *blend)
{
const VkPipelineRenderingCreateInfoKHR *render_create_info =
vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RENDERING_CREATE_INFO_KHR);
const VkPipelineRenderingCreateInfo *render_create_info =
vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RENDERING_CREATE_INFO);
bool uses_dynamic_stride = false;
struct radv_pipeline_key key;
@@ -2889,7 +2889,7 @@ radv_generate_graphics_pipeline_key(const struct radv_pipeline *pipeline,
/* we don't care about use_dynamic_stride in this case */
break;
} else if (pCreateInfo->pDynamicState->pDynamicStates[i] ==
VK_DYNAMIC_STATE_VERTEX_INPUT_BINDING_STRIDE_EXT) {
VK_DYNAMIC_STATE_VERTEX_INPUT_BINDING_STRIDE) {
uses_dynamic_stride = true;
}
}
@@ -2955,7 +2955,7 @@ radv_generate_graphics_pipeline_key(const struct radv_pipeline *pipeline,
*
* "If the bound pipeline state object was created
* with the
* VK_DYNAMIC_STATE_VERTEX_INPUT_BINDING_STRIDE_EXT
* VK_DYNAMIC_STATE_VERTEX_INPUT_BINDING_STRIDE
* dynamic state enabled then pStrides[i] specifies
* the distance in bytes between two consecutive
* elements within the corresponding buffer. In this
@@ -3484,7 +3484,7 @@ gather_tess_info(struct radv_device *device, nir_shader **nir, struct radv_shade
}
static void
radv_init_feedback(const VkPipelineCreationFeedbackCreateInfoEXT *ext)
radv_init_feedback(const VkPipelineCreationFeedbackCreateInfo *ext)
{
if (!ext)
return;
@@ -4758,8 +4758,8 @@ radv_gfx9_compute_bin_size(const struct radv_pipeline *pipeline,
},
};
const VkPipelineRenderingCreateInfoKHR *render_create_info =
vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RENDERING_CREATE_INFO_KHR);
const VkPipelineRenderingCreateInfo *render_create_info =
vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RENDERING_CREATE_INFO);
VkExtent2D extent = {512, 512};
unsigned log_num_rb_per_se =
@@ -4821,8 +4821,8 @@ static VkExtent2D
radv_gfx10_compute_bin_size(const struct radv_pipeline *pipeline,
const VkGraphicsPipelineCreateInfo *pCreateInfo)
{
const VkPipelineRenderingCreateInfoKHR *render_create_info =
vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RENDERING_CREATE_INFO_KHR);
const VkPipelineRenderingCreateInfo *render_create_info =
vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RENDERING_CREATE_INFO);
VkExtent2D extent = {512, 512};
const unsigned db_tag_size = 64;
@@ -4919,8 +4919,8 @@ radv_pipeline_init_disabled_binning_state(struct radv_pipeline *pipeline,
S_028C44_DISABLE_START_OF_PRIM(1);
if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
const VkPipelineRenderingCreateInfoKHR *render_create_info =
vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RENDERING_CREATE_INFO_KHR);
const VkPipelineRenderingCreateInfo *render_create_info =
vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RENDERING_CREATE_INFO);
const VkPipelineColorBlendStateCreateInfo *vkblend =
radv_pipeline_get_color_blend_state(pCreateInfo);
unsigned min_bytes_per_pixel = 0;
@@ -6325,8 +6325,8 @@ radv_pipeline_init_extra(struct radv_pipeline *pipeline,
struct radv_depth_stencil_state *ds_state,
uint32_t *vgt_gs_out_prim_type)
{
const VkPipelineRenderingCreateInfoKHR *render_create_info =
vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RENDERING_CREATE_INFO_KHR);
const VkPipelineRenderingCreateInfo *render_create_info =
vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RENDERING_CREATE_INFO);
bool has_depth_attachment =
render_create_info && render_create_info->depthAttachmentFormat != VK_FORMAT_UNDEFINED;
@@ -6383,8 +6383,8 @@ radv_pipeline_init(struct radv_pipeline *pipeline, struct radv_device *device,
struct radv_blend_state blend = radv_pipeline_init_blend_state(pipeline, pCreateInfo);
const VkPipelineCreationFeedbackCreateInfoEXT *creation_feedback =
vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT);
const VkPipelineCreationFeedbackCreateInfo *creation_feedback =
vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO);
radv_init_feedback(creation_feedback);
VkPipelineCreationFeedback *pipeline_feedback =
@@ -6532,7 +6532,7 @@ radv_graphics_pipeline_create(VkDevice _device, VkPipelineCache _cache,
{
VkGraphicsPipelineCreateInfo create_info = *pCreateInfo;
VkPipelineRenderingCreateInfoKHR rendering_create_info;
VkPipelineRenderingCreateInfo rendering_create_info;
VkFormat color_formats[MAX_RTS];
VkAttachmentSampleCountInfoAMD sample_info;
VkSampleCountFlagBits samples[MAX_RTS];
@@ -6540,7 +6540,7 @@ radv_graphics_pipeline_create(VkDevice _device, VkPipelineCache _cache,
RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
rendering_create_info.sType = VK_STRUCTURE_TYPE_PIPELINE_RENDERING_CREATE_INFO_KHR;
rendering_create_info.sType = VK_STRUCTURE_TYPE_PIPELINE_RENDERING_CREATE_INFO;
rendering_create_info.pNext = create_info.pNext;
create_info.pNext = &rendering_create_info;
@@ -6735,8 +6735,8 @@ radv_compute_pipeline_create(VkDevice _device, VkPipelineCache _cache,
pipeline->compute.rt_stack_sizes = rt_stack_sizes;
pipeline->compute.group_count = rt_group_count;
const VkPipelineCreationFeedbackCreateInfoEXT *creation_feedback =
vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT);
const VkPipelineCreationFeedbackCreateInfo *creation_feedback =
vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO);
radv_init_feedback(creation_feedback);
VkPipelineCreationFeedback *pipeline_feedback =
src/amd/vulkan/radv_pipeline_cache.c
+2 -2
View File
@@ -46,7 +46,7 @@ struct cache_entry {
static void
radv_pipeline_cache_lock(struct radv_pipeline_cache *cache)
{
if (cache->flags & VK_PIPELINE_CACHE_CREATE_EXTERNALLY_SYNCHRONIZED_BIT_EXT)
if (cache->flags & VK_PIPELINE_CACHE_CREATE_EXTERNALLY_SYNCHRONIZED_BIT)
return;
mtx_lock(&cache->mutex);
@@ -55,7 +55,7 @@ radv_pipeline_cache_lock(struct radv_pipeline_cache *cache)
static void
radv_pipeline_cache_unlock(struct radv_pipeline_cache *cache)
{
if (cache->flags & VK_PIPELINE_CACHE_CREATE_EXTERNALLY_SYNCHRONIZED_BIT_EXT)
if (cache->flags & VK_PIPELINE_CACHE_CREATE_EXTERNALLY_SYNCHRONIZED_BIT)
return;
mtx_unlock(&cache->mutex);
src/amd/vulkan/radv_pipeline_rt.c
+5 -5
View File
@@ -1824,8 +1824,8 @@ radv_rt_pipeline_create(VkDevice _device, VkPipelineCache _cache,
radv_hash_rt_shaders(hash, &local_create_info, radv_get_hash_flags(device, keep_statistic_info));
struct vk_shader_module module = {.base.type = VK_OBJECT_TYPE_SHADER_MODULE};
VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT subgroup_size = {
.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_REQUIRED_SUBGROUP_SIZE_CREATE_INFO_EXT,
VkPipelineShaderStageRequiredSubgroupSizeCreateInfo subgroup_size = {
.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_REQUIRED_SUBGROUP_SIZE_CREATE_INFO,
.pNext = NULL,
.requiredSubgroupSize = device->physical_device->rt_wave_size,
};
@@ -1833,7 +1833,7 @@ radv_rt_pipeline_create(VkDevice _device, VkPipelineCache _cache,
VkComputePipelineCreateInfo compute_info = {
.sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,
.pNext = NULL,
.flags = pCreateInfo->flags | VK_PIPELINE_CREATE_FAIL_ON_PIPELINE_COMPILE_REQUIRED_BIT_EXT,
.flags = pCreateInfo->flags | VK_PIPELINE_CREATE_FAIL_ON_PIPELINE_COMPILE_REQUIRED_BIT,
.stage =
{
.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
@@ -1849,7 +1849,7 @@ radv_rt_pipeline_create(VkDevice _device, VkPipelineCache _cache,
* generating the nir. */
result = radv_compute_pipeline_create(_device, _cache, &compute_info, pAllocator, hash,
stack_sizes, local_create_info.groupCount, pPipeline);
if (result == VK_PIPELINE_COMPILE_REQUIRED_EXT) {
if (result == VK_PIPELINE_COMPILE_REQUIRED) {
stack_sizes = calloc(sizeof(*stack_sizes), local_create_info.groupCount);
if (!stack_sizes) {
result = VK_ERROR_OUT_OF_HOST_MEMORY;
@@ -1927,7 +1927,7 @@ radv_CreateRayTracingPipelinesKHR(VkDevice _device, VkDeferredOperationKHR defer
result = r;
pPipelines[i] = VK_NULL_HANDLE;
if (pCreateInfos[i].flags & VK_PIPELINE_CREATE_EARLY_RETURN_ON_FAILURE_BIT_EXT)
if (pCreateInfos[i].flags & VK_PIPELINE_CREATE_EARLY_RETURN_ON_FAILURE_BIT)
break;
}
}
src/amd/vulkan/radv_private.h
+6 -6
View File
@@ -1663,10 +1663,10 @@ void radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer, struct radv_im
void radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
const VkImageSubresourceRange *range, bool value);
enum radv_cmd_flush_bits radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
VkAccessFlags2KHR src_flags,
VkAccessFlags2 src_flags,
const struct radv_image *image);
enum radv_cmd_flush_bits radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
VkAccessFlags2KHR dst_flags,
VkAccessFlags2 dst_flags,
const struct radv_image *image);
uint32_t radv_fill_buffer(struct radv_cmd_buffer *cmd_buffer, const struct radv_image *image,
struct radeon_winsys_bo *bo, uint64_t offset, uint64_t size,
@@ -2514,9 +2514,9 @@ struct radv_framebuffer {
};
struct radv_subpass_barrier {
VkPipelineStageFlags2KHR src_stage_mask;
VkAccessFlags2KHR src_access_mask;
VkAccessFlags2KHR dst_access_mask;
VkPipelineStageFlags2 src_stage_mask;
VkAccessFlags2 src_access_mask;
VkAccessFlags2 dst_access_mask;
};
void radv_emit_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
@@ -2663,7 +2663,7 @@ void radv_emit_thread_trace_userdata(const struct radv_device *device, struct ra
bool radv_is_instruction_timing_enabled(void);
bool radv_sdma_copy_image(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
struct radv_buffer *buffer, const VkBufferImageCopy2KHR *region);
struct radv_buffer *buffer, const VkBufferImageCopy2 *region);
/* radv_sqtt_layer_.c */
struct radv_barrier_data {
src/amd/vulkan/radv_query.c
+3 -3
View File
@@ -1615,8 +1615,8 @@ radv_CmdEndQuery(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t
}
VKAPI_ATTR void VKAPI_CALL
radv_CmdWriteTimestamp2KHR(VkCommandBuffer commandBuffer, VkPipelineStageFlags2KHR stage,
VkQueryPool queryPool, uint32_t query)
radv_CmdWriteTimestamp2(VkCommandBuffer commandBuffer, VkPipelineStageFlags2 stage,
VkQueryPool queryPool, uint32_t query)
{
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
RADV_FROM_HANDLE(radv_query_pool, pool, queryPool);
@@ -1636,7 +1636,7 @@ radv_CmdWriteTimestamp2KHR(VkCommandBuffer commandBuffer, VkPipelineStageFlags2K
ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 28 * num_queries);
for (unsigned i = 0; i < num_queries; i++) {
if (stage == VK_PIPELINE_STAGE_2_TOP_OF_PIPE_BIT_KHR) {
if (stage == VK_PIPELINE_STAGE_2_TOP_OF_PIPE_BIT) {
radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
radeon_emit(cs, COPY_DATA_COUNT_SEL | COPY_DATA_WR_CONFIRM |
COPY_DATA_SRC_SEL(COPY_DATA_TIMESTAMP) | COPY_DATA_DST_SEL(V_370_MEM));
src/amd/vulkan/radv_sdma_copy_image.c
+2 -2
View File
@@ -70,7 +70,7 @@ radv_translate_format_to_hw(struct radeon_info *info, VkFormat format, unsigned
static bool
radv_sdma_v4_v5_copy_image_to_buffer(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
struct radv_buffer *buffer,
const VkBufferImageCopy2KHR *region)
const VkBufferImageCopy2 *region)
{
assert(image->plane_count == 1);
struct radv_device *device = cmd_buffer->device;
@@ -189,7 +189,7 @@ radv_sdma_v4_v5_copy_image_to_buffer(struct radv_cmd_buffer *cmd_buffer, struct
bool
radv_sdma_copy_image(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
struct radv_buffer *buffer, const VkBufferImageCopy2KHR *region)
struct radv_buffer *buffer, const VkBufferImageCopy2 *region)
{
assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9);
return radv_sdma_v4_v5_copy_image_to_buffer(cmd_buffer, image, buffer, region);