From 2af3ef9305ba86733bfb138fdc361beb8de2b951 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Thu, 3 Jul 2025 10:44:06 +0200 Subject: [PATCH] ac/surface: select a different swizzle mode for ASTC formats on GFX12 It seems only 4KiB swizzle works fine with ASTC. Cc: mesa-stable Signed-off-by: Samuel Pitoiset Part-of: --- src/amd/common/ac_surface.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c index a01bce48dd7..840b6ec0898 100644 --- a/src/amd/common/ac_surface.c +++ b/src/amd/common/ac_surface.c @@ -804,6 +804,29 @@ static unsigned bpe_to_format(struct radeon_surf *surf) return ADDR_FMT_INVALID; } +static bool +is_astc_format(unsigned format) +{ + switch (format) { + case ADDR_FMT_ASTC_5x4: + case ADDR_FMT_ASTC_5x5: + case ADDR_FMT_ASTC_6x5: + case ADDR_FMT_ASTC_6x6: + case ADDR_FMT_ASTC_8x5: + case ADDR_FMT_ASTC_8x6: + case ADDR_FMT_ASTC_8x8: + case ADDR_FMT_ASTC_10x5: + case ADDR_FMT_ASTC_10x6: + case ADDR_FMT_ASTC_10x8: + case ADDR_FMT_ASTC_10x10: + case ADDR_FMT_ASTC_12x10: + case ADDR_FMT_ASTC_12x12: + return true; + default: + return false; + } +} + /* The addrlib pitch alignment is forced to this number for all chips to support interop * between any 2 chips. */ @@ -3376,6 +3399,8 @@ static bool gfx12_compute_surface(struct ac_addrlib *addrlib, const struct radeo AddrSurfInfoIn.swizzleMode = ADDR3_LINEAR; } else if (surf->flags & RADEON_SURF_VIDEO_REFERENCE) { AddrSurfInfoIn.swizzleMode = ADDR3_256B_2D; + } else if (is_astc_format(AddrSurfInfoIn.format)) { + AddrSurfInfoIn.swizzleMode = config->is_3d ? ADDR3_4KB_3D : ADDR3_4KB_2D; } else { AddrSurfInfoIn.swizzleMode = gfx12_select_swizzle_mode(addrlib, info, config, surf, &AddrSurfInfoIn, surf->flags);