From 2ab3d5f436c1d6d4012ae20c773273511bd14316 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?= Date: Tue, 14 Mar 2023 12:34:36 -0700 Subject: [PATCH] intel: Move memory aligment information to intel_device_info MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This same information is also used in ANV, so intel_device_info is a better place to have it. Signed-off-by: José Roberto de Souza Reviewed-by: Lionel Landwerlin Part-of: --- src/gallium/drivers/iris/iris_bufmgr.c | 7 +------ src/intel/dev/i915/intel_device_info.c | 7 +++++++ src/intel/dev/intel_device_info.h | 5 +++++ 3 files changed, 13 insertions(+), 6 deletions(-) diff --git a/src/gallium/drivers/iris/iris_bufmgr.c b/src/gallium/drivers/iris/iris_bufmgr.c index 42400fa5248..2be7146b906 100644 --- a/src/gallium/drivers/iris/iris_bufmgr.c +++ b/src/gallium/drivers/iris/iris_bufmgr.c @@ -226,7 +226,6 @@ struct iris_bufmgr { struct util_vma_heap vma_allocator[IRIS_MEMZONE_COUNT]; - uint64_t vma_min_align; struct iris_memregion vram, sys; /* Used only when use_global_vm is true. */ @@ -400,7 +399,7 @@ vma_alloc(struct iris_bufmgr *bufmgr, /* Force minimum alignment based on device requirements */ assert((alignment & (alignment - 1)) == 0); - alignment = MAX2(alignment, bufmgr->vma_min_align); + alignment = MAX2(alignment, bufmgr->devinfo.mem_alignment); if (memzone == IRIS_MEMZONE_BORDER_COLOR_POOL) return IRIS_BORDER_COLOR_POOL_ADDRESS; @@ -2250,10 +2249,6 @@ iris_bufmgr_create(struct intel_device_info *devinfo, int fd, bool bo_reuse) bufmgr->handle_table = _mesa_hash_table_create(NULL, _mesa_hash_uint, _mesa_key_uint_equal); - bufmgr->vma_min_align = - devinfo->verx10 >= 125 ? 2 * 1024 * 1024 : - (devinfo->has_local_mem ? 64 * 1024 : PAGE_SIZE); - if (devinfo->has_aux_map) { bufmgr->aux_map_ctx = intel_aux_map_init(bufmgr, &aux_map_allocator, devinfo); diff --git a/src/intel/dev/i915/intel_device_info.c b/src/intel/dev/i915/intel_device_info.c index 5cbb62209fb..982c81ee153 100644 --- a/src/intel/dev/i915/intel_device_info.c +++ b/src/intel/dev/i915/intel_device_info.c @@ -610,5 +610,12 @@ bool intel_device_info_i915_get_info_from_fd(int fd, struct intel_device_info *d if (getparam(fd, I915_PARAM_HAS_CONTEXT_ISOLATION, &val)) devinfo->has_context_isolation = val; + if (devinfo->verx10 >= 125) + devinfo->mem_alignment = 2 * 1024 * 1024; + else if (devinfo->has_local_mem) + devinfo->mem_alignment = 64 * 1024; + else + devinfo->mem_alignment = 4096; + return true; } diff --git a/src/intel/dev/intel_device_info.h b/src/intel/dev/intel_device_info.h index 1766130c418..6b5f61ebffc 100644 --- a/src/intel/dev/intel_device_info.h +++ b/src/intel/dev/intel_device_info.h @@ -383,6 +383,11 @@ struct intel_device_info */ unsigned engine_class_prefetch[INTEL_ENGINE_CLASS_COMPUTE + 1]; + /** + * Memory alignment requirement for this device. + */ + unsigned mem_alignment; + /** * For the longest time the timestamp frequency for Gen's timestamp counter * could be assumed to be 12.5MHz, where the least significant bit neatly