From 2a0b9839ca81b5c070da7136fc1fb940999f32e8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Sun, 14 Apr 2024 14:24:43 -0400 Subject: [PATCH] radeonsi: add use_aco into CS blit shader key it will be set in a future commit Reviewed-by: Pierre-Eric Pelloux-Prayer Part-of: --- src/gallium/drivers/radeonsi/si_compute_blit.c | 4 +++- src/gallium/drivers/radeonsi/si_pipe.h | 1 + src/gallium/drivers/radeonsi/si_shaderlib_nir.c | 6 ++++-- 3 files changed, 8 insertions(+), 3 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_compute_blit.c b/src/gallium/drivers/radeonsi/si_compute_blit.c index df777a13952..47361d89587 100644 --- a/src/gallium/drivers/radeonsi/si_compute_blit.c +++ b/src/gallium/drivers/radeonsi/si_compute_blit.c @@ -1402,6 +1402,8 @@ bool si_compute_blit(struct si_context *sctx, const struct pipe_blit_info *info, union si_compute_blit_shader_key options; options.key = 0; + /* Only ACO can form VMEM clauses for image stores, which is a requirement for performance. */ + options.use_aco = true; options.is_clear = is_clear; options.wg_dim = wg_dim; options.has_start_xyz = start_x || start_y || start_z; @@ -1419,7 +1421,7 @@ bool si_compute_blit(struct si_context *sctx, const struct pipe_blit_info *info, options.last_dst_channel = util_format_get_last_component(info->dst.format); /* ACO doesn't support D16 on GFX8 */ - bool has_d16 = sctx->gfx_level >= (sctx->screen->use_aco ? GFX9 : GFX8); + bool has_d16 = sctx->gfx_level >= (options.use_aco || sctx->screen->use_aco ? GFX9 : GFX8); if (is_clear) { assert(dst_samples <= 8); diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h index 8166993b66d..f750295fef7 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.h +++ b/src/gallium/drivers/radeonsi/si_pipe.h @@ -1640,6 +1640,7 @@ void *si_clear_image_dcc_single_shader(struct si_context *sctx, bool is_msaa, un union si_compute_blit_shader_key { struct { + bool use_aco:1; /* Workgroup settings. */ uint8_t wg_dim:2; /* 1, 2, or 3 */ bool has_start_xyz:1; diff --git a/src/gallium/drivers/radeonsi/si_shaderlib_nir.c b/src/gallium/drivers/radeonsi/si_shaderlib_nir.c index 7572ef317a2..35e2f6e61c5 100644 --- a/src/gallium/drivers/radeonsi/si_shaderlib_nir.c +++ b/src/gallium/drivers/radeonsi/si_shaderlib_nir.c @@ -9,7 +9,7 @@ #include "ac_surface.h" #include "si_pipe.h" #include "si_query.h" - +#include "aco_interface.h" #include "nir_format_convert.h" static void *create_shader_state(struct si_context *sctx, nir_shader *nir) @@ -326,6 +326,7 @@ void *si_create_blit_cs(struct si_context *sctx, const union si_compute_blit_sha { if (si_can_dump_shader(sctx->screen, MESA_SHADER_COMPUTE, SI_DUMP_SHADER_KEY)) { fprintf(stderr, "Internal shader: compute_blit\n"); + fprintf(stderr, " options.use_aco = %u\n", options->use_aco); fprintf(stderr, " options.wg_dim = %u\n", options->wg_dim); fprintf(stderr, " options.has_start_xyz = %u\n", options->has_start_xyz); fprintf(stderr, " options.log_lane_width = %u\n", options->log_lane_width); @@ -360,7 +361,8 @@ void *si_create_blit_cs(struct si_context *sctx, const union si_compute_blit_sha nir_builder b = nir_builder_init_simple_shader(MESA_SHADER_COMPUTE, nir_options, "blit_non_scaled_cs"); - b.shader->info.use_aco_amd = sctx->screen->use_aco; + b.shader->info.use_aco_amd = sctx->screen->use_aco || + (options->use_aco && aco_is_gpu_supported(&sctx->screen->info)); b.shader->info.num_images = options->is_clear ? 1 : 2; unsigned image_dst_index = b.shader->info.num_images - 1; if (!options->is_clear && options->src_is_msaa)